Add a new do_arch_prctl to handle arch_prctls that are not specific to 64
bits. Call it from the syscall entry point, but not any of the other
callsites in the kernel, which all want one of the existing 64 bit only
arch_prctls.
Signed-off-by: Kyle Huey
---
arch/x86/include/asm/proto.h | 1
Hook up arch_prctl to call do_arch_prctl on x86-32, and in 32 bit compat
mode on x86-64. This allows us to have arch_prctls that are not specific to
64 bits.
On UML, simply stub out this syscall.
Signed-off-by: Kyle Huey <kh...@kylehuey.com>
---
arch/x86/entry/syscalls/syscall_32.t
ure. It is
documented in detail in Section 2.3.2 of
http://www.intel.com/content/dam/www/public/us/en/documents/application-notes/virtualization-technology-flexmigration-application-note.pdf
Detect support for this feature and expose it as X86_FEATURE_CPUID_FAULT.
Signed-off-by: Kyle Huey
rr (http://rr-project.org/), a userspace record-and-replay reverse-
execution debugger, would like to trap and emulate the CPUID instruction.
This would allow us to a) mask away certain hardware features that rr does
not support (e.g. RDRAND) and b) enable trace portability across machines
by
Hook up arch_prctl to call do_arch_prctl on x86-32, and in 32 bit compat
mode on x86-64. This allows us to have arch_prctls that are not specific to
64 bits.
On UML, simply stub out this syscall.
Signed-off-by: Kyle Huey
---
arch/x86/entry/syscalls/syscall_32.tbl | 1 +
arch/x86/kernel
ure. It is
documented in detail in Section 2.3.2 of
http://www.intel.com/content/dam/www/public/us/en/documents/application-notes/virtualization-technology-flexmigration-application-note.pdf
Detect support for this feature and expose it as X86_FEATURE_CPUID_FAULT.
Signed-off-by: Kyle Huey
Revie
rr (http://rr-project.org/), a userspace record-and-replay reverse-
execution debugger, would like to trap and emulate the CPUID instruction.
This would allow us to a) mask away certain hardware features that rr does
not support (e.g. RDRAND) and b) enable trace portability across machines
by
rg2 is
another value or CPUID faulting is not supported on this system.
The state of the CPUID faulting flag is propagated across forks, but reset
upon exec.
Signed-off-by: Kyle Huey <kh...@kylehuey.com>
---
arch/x86/include/asm/msr-index.h | 1 +
arch/x86/include/asm/thread_info.h
rg2 is
another value or CPUID faulting is not supported on this system.
The state of the CPUID faulting flag is propagated across forks, but reset
upon exec.
Signed-off-by: Kyle Huey
---
arch/x86/include/asm/msr-index.h | 1 +
arch/x86/include/asm/thread_info.h| 6 +-
arch/
Hook up arch_prctl to call do_arch_prctl on x86-32, and in 32 bit compat
mode on x86-64. This allows us to have arch_prctls that are not specific to
64 bits.
On UML, simply stub out this syscall.
Signed-off-by: Kyle Huey <kh...@kylehuey.com>
---
arch/x86/entry/syscalls/syscall_32.t
Add a new do_arch_prctl to handle arch_prctls that are not specific to 64
bits. Call it from the syscall entry point, but not any of the other
callsites in the kernel, which all want one of the existing 64 bit only
arch_prctls.
Signed-off-by: Kyle Huey <kh...@kylehuey.com>
---
arch/x86/i
Hook up arch_prctl to call do_arch_prctl on x86-32, and in 32 bit compat
mode on x86-64. This allows us to have arch_prctls that are not specific to
64 bits.
On UML, simply stub out this syscall.
Signed-off-by: Kyle Huey
---
arch/x86/entry/syscalls/syscall_32.tbl | 1 +
arch/x86/kernel
Add a new do_arch_prctl to handle arch_prctls that are not specific to 64
bits. Call it from the syscall entry point, but not any of the other
callsites in the kernel, which all want one of the existing 64 bit only
arch_prctls.
Signed-off-by: Kyle Huey
---
arch/x86/include/asm/proto.h | 1
In order to introduce new arch_prctls that are not 64 bit only, rename the
existing 64 bit implementation to do_arch_prctl_64. Also rename the second
argument to arch_prctl, which will no longer always be an address.
Signed-off-by: Kyle Huey <kh...@kylehuey.com>
---
arch/x86/include/asm/p
ure. It is
documented in detail in Section 2.3.2 of
http://www.intel.com/content/dam/www/public/us/en/documents/application-notes/virtualization-technology-flexmigration-application-note.pdf
Detect support for this feature and expose it as X86_FEATURE_CPUID_FAULT.
Signed-off-by: Kyle Huey
ure. It is
documented in detail in Section 2.3.2 of
http://www.intel.com/content/dam/www/public/us/en/documents/application-notes/virtualization-technology-flexmigration-application-note.pdf
Detect support for this feature and expose it as X86_FEATURE_CPUID_FAULT.
Signed-off-by: Kyle Huey
Revie
In order to introduce new arch_prctls that are not 64 bit only, rename the
existing 64 bit implementation to do_arch_prctl_64. Also rename the second
argument to arch_prctl, which will no longer always be an address.
Signed-off-by: Kyle Huey
---
arch/x86/include/asm/proto.h | 4 +++-
arch/x86
Signed-off-by: Kyle Huey <kh...@kylehuey.com>
---
arch/x86/kernel/process_64.c | 3 ++-
arch/x86/um/syscalls_64.c| 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
index 63236d8..4d6363c 100644
--- a/ar
Signed-off-by: Kyle Huey
---
arch/x86/kernel/process_64.c | 3 ++-
arch/x86/um/syscalls_64.c| 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
index 63236d8..4d6363c 100644
--- a/arch/x86/kernel/process_64.c
rr (http://rr-project.org/), a userspace record-and-replay reverse-
execution debugger, would like to trap and emulate the CPUID instruction.
This would allow us to a) mask away certain hardware features that rr does
not support (e.g. RDRAND) and b) enable trace portability across machines
by
rr (http://rr-project.org/), a userspace record-and-replay reverse-
execution debugger, would like to trap and emulate the CPUID instruction.
This would allow us to a) mask away certain hardware features that rr does
not support (e.g. RDRAND) and b) enable trace portability across machines
by
On Fri, Sep 16, 2016 at 12:50 AM, Thomas Gleixner <t...@linutronix.de> wrote:
> On Thu, 15 Sep 2016, Kyle Huey wrote:
>
> First of all, please add a cover letter [PATCH 0/N] to your patch series
> and send it with something which provides proper mail threading.
> See: git-sen
On Fri, Sep 16, 2016 at 12:50 AM, Thomas Gleixner wrote:
> On Thu, 15 Sep 2016, Kyle Huey wrote:
>
> First of all, please add a cover letter [PATCH 0/N] to your patch series
> and send it with something which provides proper mail threading.
> See: git-send-email, quilt
I did ... s
On Thu, Sep 15, 2016 at 5:07 PM, Andy Lutomirski <l...@amacapital.net> wrote:
> On Thu, Sep 15, 2016 at 4:33 PM, Kyle Huey <m...@kylehuey.com> wrote:
>> +int get_cpuid_mode(unsigned long adr)
>> +{
>> + unsigned int val;
>> +
>
On Thu, Sep 15, 2016 at 5:07 PM, Andy Lutomirski wrote:
> On Thu, Sep 15, 2016 at 4:33 PM, Kyle Huey wrote:
>> +int get_cpuid_mode(unsigned long adr)
>> +{
>> + unsigned int val;
>> +
>> + if (test_thread_flag(TIF_NOCPUID))
>> + va
On Thu, Sep 15, 2016 at 12:37 PM, Andy Lutomirski <l...@amacapital.net> wrote:
> On Thu, Sep 15, 2016 at 12:11 PM, Kyle Huey <m...@kylehuey.com> wrote:
>> On Thu, Sep 15, 2016 at 3:25 AM, Jan Beulich <jbeul...@suse.com> wrote:
>>>>>> On 15.09
On Thu, Sep 15, 2016 at 12:37 PM, Andy Lutomirski wrote:
> On Thu, Sep 15, 2016 at 12:11 PM, Kyle Huey wrote:
>> On Thu, Sep 15, 2016 at 3:25 AM, Jan Beulich wrote:
>>>>>> On 15.09.16 at 12:05, wrote:
>>>> On 14/09/16 22:01, Kyle Huey wrote:
>
-off-by: Kyle Huey <kh...@kylehuey.com>
---
arch/x86/include/asm/msr-index.h | 1 +
arch/x86/include/asm/thread_info.h| 5 +-
arch/x86/include/uapi/asm/prctl.h | 6 +
arch/x86/kernel/process.c | 98 -
fs/
-off-by: Kyle Huey
---
arch/x86/include/asm/msr-index.h | 1 +
arch/x86/include/asm/thread_info.h| 5 +-
arch/x86/include/uapi/asm/prctl.h | 6 +
arch/x86/kernel/process.c | 98 -
fs/exec.c | 6 +
tools
Signed-off-by: Kyle Huey <kh...@kylehuey.com>
---
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/include/asm/msr-index.h | 1 +
arch/x86/kernel/cpu/scattered.c| 14 ++
3 files changed, 16 insertions(+)
diff --git a/arch/x86/include/asm/cpufeatures.h
b/arch/x86/i
arch_prctl is currently 64-bit only. Wire it up for 32-bits, as a no-op for
now. Rename the second arg to a more generic name.
Signed-off-by: Kyle Huey <kh...@kylehuey.com>
---
arch/x86/entry/syscalls/syscall_32.tbl | 1 +
arch/x86/include/asm/proto.h | 5 -
arch/x86/
Signed-off-by: Kyle Huey
---
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/include/asm/msr-index.h | 1 +
arch/x86/kernel/cpu/scattered.c| 14 ++
3 files changed, 16 insertions(+)
diff --git a/arch/x86/include/asm/cpufeatures.h
b/arch/x86/include/asm/cpufeatures.h
arch_prctl is currently 64-bit only. Wire it up for 32-bits, as a no-op for
now. Rename the second arg to a more generic name.
Signed-off-by: Kyle Huey
---
arch/x86/entry/syscalls/syscall_32.tbl | 1 +
arch/x86/include/asm/proto.h | 5 -
arch/x86/kernel/process.c
rr (http://rr-project.org/), a userspace record-and-replay reverse-
execution debugger, would like to trap and emulate the CPUID instruction.
This would allow us to a) mask away certain hardware features that rr does
not support (e.g. RDRAND) and b) enable trace portability across machines
by
rr (http://rr-project.org/), a userspace record-and-replay reverse-
execution debugger, would like to trap and emulate the CPUID instruction.
This would allow us to a) mask away certain hardware features that rr does
not support (e.g. RDRAND) and b) enable trace portability across machines
by
On Thu, Sep 15, 2016 at 3:25 AM, Jan Beulich <jbeul...@suse.com> wrote:
>>>> On 15.09.16 at 12:05, <david.vra...@citrix.com> wrote:
>> On 14/09/16 22:01, Kyle Huey wrote:
>>> Xen advertises the underlying support for CPUID faulting but not does pass
>>&
On Thu, Sep 15, 2016 at 3:25 AM, Jan Beulich wrote:
>>>> On 15.09.16 at 12:05, wrote:
>> On 14/09/16 22:01, Kyle Huey wrote:
>>> Xen advertises the underlying support for CPUID faulting but not does pass
>>> through writes to the relevant MSR, n
On Wed, Sep 14, 2016 at 6:17 PM, Andy Lutomirski <l...@amacapital.net> wrote:
> On Wed, Sep 14, 2016 at 3:03 PM, Kyle Huey <m...@kylehuey.com> wrote:
>> On Wed, Sep 14, 2016 at 2:35 PM, Dave Hansen
>> <dave.han...@linux.intel.com> wrote:
>>> On 09/14/20
On Wed, Sep 14, 2016 at 6:17 PM, Andy Lutomirski wrote:
> On Wed, Sep 14, 2016 at 3:03 PM, Kyle Huey wrote:
>> On Wed, Sep 14, 2016 at 2:35 PM, Dave Hansen
>> wrote:
>>> On 09/14/2016 02:01 PM, Kyle Huey wrote:
>
>>> Is any of this useful to optimize a
On Wed, Sep 14, 2016 at 6:54 PM, Andy Lutomirski <l...@amacapital.net> wrote:
> On Wed, Sep 14, 2016 at 6:47 PM, Kyle Huey <m...@kylehuey.com> wrote:
>> On Wed, Sep 14, 2016 at 6:29 PM, Andy Lutomirski <l...@amacapital.net> wrote:
>>> On Wed, Sep 14, 2016 at 2
On Wed, Sep 14, 2016 at 6:54 PM, Andy Lutomirski wrote:
> On Wed, Sep 14, 2016 at 6:47 PM, Kyle Huey wrote:
>> On Wed, Sep 14, 2016 at 6:29 PM, Andy Lutomirski wrote:
>>> On Wed, Sep 14, 2016 at 2:01 PM, Kyle Huey wrote:
>
>>>> +
>>>> +int set_cpuid
On Wed, Sep 14, 2016 at 6:29 PM, Andy Lutomirski <l...@amacapital.net> wrote:
> On Wed, Sep 14, 2016 at 2:01 PM, Kyle Huey <m...@kylehuey.com> wrote:
>> Intel supports faulting on the CPUID instruction in newer processors. Bit
>> 31 of MSR_PLATFORM_INFO advertis
On Wed, Sep 14, 2016 at 6:29 PM, Andy Lutomirski wrote:
> On Wed, Sep 14, 2016 at 2:01 PM, Kyle Huey wrote:
>> Intel supports faulting on the CPUID instruction in newer processors. Bit
>> 31 of MSR_PLATFORM_INFO advertises support for this feature. It is
>> documented in de
On Wed, Sep 14, 2016 at 3:29 PM, Dmitry Safonov <0x7f454...@gmail.com> wrote:
> 2016-09-15 1:08 GMT+03:00 Kyle Huey <m...@kylehuey.com>:
>> On Wed, Sep 14, 2016 at 2:59 PM, Dmitry Safonov <0x7f454...@gmail.com> wrote:
>>> 2016-09-15 0:08 GMT+03:00 Kyle Huey
On Wed, Sep 14, 2016 at 3:29 PM, Dmitry Safonov <0x7f454...@gmail.com> wrote:
> 2016-09-15 1:08 GMT+03:00 Kyle Huey :
>> On Wed, Sep 14, 2016 at 2:59 PM, Dmitry Safonov <0x7f454...@gmail.com> wrote:
>>> 2016-09-15 0:08 GMT+03:00 Kyle Huey :
>>>> Signed-
On Wed, Sep 14, 2016 at 2:59 PM, Dmitry Safonov <0x7f454...@gmail.com> wrote:
> 2016-09-15 0:08 GMT+03:00 Kyle Huey <m...@kylehuey.com>:
>> Signed-off-by: Kyle Huey <kh...@kylehuey.com>
>> ---
>> arch/x86/entry/syscalls/syscall_32.tbl | 1 +
>>
On Wed, Sep 14, 2016 at 2:59 PM, Dmitry Safonov <0x7f454...@gmail.com> wrote:
> 2016-09-15 0:08 GMT+03:00 Kyle Huey :
>> Signed-off-by: Kyle Huey
>> ---
>> arch/x86/entry/syscalls/syscall_32.tbl | 1 +
>> arch/x86/k
On Wed, Sep 14, 2016 at 2:35 PM, Dave Hansen
<dave.han...@linux.intel.com> wrote:
> On 09/14/2016 02:01 PM, Kyle Huey wrote:
>> Xen advertises the underlying support for CPUID faulting but not does pass
>> through writes to the relevant MSR, nor does it virtualize it, so it
On Wed, Sep 14, 2016 at 2:35 PM, Dave Hansen
wrote:
> On 09/14/2016 02:01 PM, Kyle Huey wrote:
>> Xen advertises the underlying support for CPUID faulting but not does pass
>> through writes to the relevant MSR, nor does it virtualize it, so it does
>> not actually w
On Wed, Sep 14, 2016 at 2:46 PM, Dave Hansen
<dave.han...@linux.intel.com> wrote:
> On 09/14/2016 02:35 PM, Kyle Huey wrote:
>> It's not quite a plain move. To leave the existing arch_prctls only
>> accessible to 64 bit callers, I added the is_32 bit and the four earl
On Wed, Sep 14, 2016 at 2:46 PM, Dave Hansen
wrote:
> On 09/14/2016 02:35 PM, Kyle Huey wrote:
>> It's not quite a plain move. To leave the existing arch_prctls only
>> accessible to 64 bit callers, I added the is_32 bit and the four early
>> returns for each existing AR
On Wed, Sep 14, 2016 at 2:29 PM, Dave Hansen
<dave.han...@linux.intel.com> wrote:
> On 09/14/2016 02:01 PM, Kyle Huey wrote:
>> Signed-off-by: Kyle Huey <kh...@kylehuey.com>
>> ---
>> arch/x86/entry/syscalls/syscall_32.tbl | 1 +
>> arch
On Wed, Sep 14, 2016 at 2:29 PM, Dave Hansen
wrote:
> On 09/14/2016 02:01 PM, Kyle Huey wrote:
>> Signed-off-by: Kyle Huey
>> ---
>> arch/x86/entry/syscalls/syscall_32.tbl | 1 +
>> arch/x86/kernel/process.c | 80
>> +
Signed-off-by: Kyle Huey <kh...@kylehuey.com>
---
man2/arch_prctl.2 | 73 +--
1 file changed, 60 insertions(+), 13 deletions(-)
diff --git a/man2/arch_prctl.2 b/man2/arch_prctl.2
index 989d369..c388797 100644
--- a/man2/arch_prctl.2
+++
-flexmigration-application-note.pdf
Signed-off-by: Kyle Huey <kh...@kylehuey.com>
---
arch/x86/include/asm/msr-index.h | 1 +
arch/x86/include/asm/thread_info.h| 4 +-
arch/x86/include/uapi/asm/prctl.h | 6 +
arch/x86/kernel/process.c | 81 +++
Signed-off-by: Kyle Huey
---
man2/arch_prctl.2 | 73 +--
1 file changed, 60 insertions(+), 13 deletions(-)
diff --git a/man2/arch_prctl.2 b/man2/arch_prctl.2
index 989d369..c388797 100644
--- a/man2/arch_prctl.2
+++ b/man2/arch_prctl.2
-flexmigration-application-note.pdf
Signed-off-by: Kyle Huey
---
arch/x86/include/asm/msr-index.h | 1 +
arch/x86/include/asm/thread_info.h| 4 +-
arch/x86/include/uapi/asm/prctl.h | 6 +
arch/x86/kernel/process.c | 81 +++
tools/testing/selftests/x86
Xen advertises the underlying support for CPUID faulting but not does pass
through writes to the relevant MSR, nor does it virtualize it, so it does
not actually work. For now mask off the relevant bit on MSR_PLATFORM_INFO.
Signed-off-by: Kyle Huey <kh...@kylehuey.com>
---
arch/x86/inclu
Xen advertises the underlying support for CPUID faulting but not does pass
through writes to the relevant MSR, nor does it virtualize it, so it does
not actually work. For now mask off the relevant bit on MSR_PLATFORM_INFO.
Signed-off-by: Kyle Huey
---
arch/x86/include/asm/cpufeatures.h | 1
Signed-off-by: Kyle Huey <kh...@kylehuey.com>
---
arch/x86/entry/syscalls/syscall_32.tbl | 1 +
arch/x86/kernel/process.c | 80 ++
arch/x86/kernel/process_64.c | 66
3 files changed, 81 insertions(
Signed-off-by: Kyle Huey
---
arch/x86/entry/syscalls/syscall_32.tbl | 1 +
arch/x86/kernel/process.c | 80 ++
arch/x86/kernel/process_64.c | 66
3 files changed, 81 insertions(+), 66 deletions(-)
diff --git
(Resending because I screwed up the cover email, sorry about that.)
rr (http://rr-project.org/), a userspace record-and-replay reverse-
execution debugger, would like to trap and emulate the CPUID instruction.
This would allow us to a) mask away certain hardware features that rr does
not support
(Resending because I screwed up the cover email, sorry about that.)
rr (http://rr-project.org/), a userspace record-and-replay reverse-
execution debugger, would like to trap and emulate the CPUID instruction.
This would allow us to a) mask away certain hardware features that rr does
not support
-flexmigration-application-note.pdf
Signed-off-by: Kyle Huey <kh...@kylehuey.com>
---
arch/x86/include/asm/msr-index.h | 1 +
arch/x86/include/asm/thread_info.h| 4 +-
arch/x86/include/uapi/asm/prctl.h | 6 +
arch/x86/kernel/process.c | 81 +++
-flexmigration-application-note.pdf
Signed-off-by: Kyle Huey
---
arch/x86/include/asm/msr-index.h | 1 +
arch/x86/include/asm/thread_info.h| 4 +-
arch/x86/include/uapi/asm/prctl.h | 6 +
arch/x86/kernel/process.c | 81 +++
tools/testing/selftests/x86
Signed-off-by: Kyle Huey <kh...@kylehuey.com>
---
arch/x86/entry/syscalls/syscall_32.tbl | 1 +
arch/x86/kernel/process.c | 80 ++
arch/x86/kernel/process_64.c | 66
3 files changed, 81 insertions(
Xen advertises the underlying support for CPUID faulting but not does pass
through writes to the relevant MSR, nor does it virtualize it, so it does
not actually work. For now mask off the relevant bit on MSR_PLATFORM_INFO.
Signed-off-by: Kyle Huey <kh...@kylehuey.com>
---
arch/x86/inclu
Signed-off-by: Kyle Huey
---
arch/x86/entry/syscalls/syscall_32.tbl | 1 +
arch/x86/kernel/process.c | 80 ++
arch/x86/kernel/process_64.c | 66
3 files changed, 81 insertions(+), 66 deletions(-)
diff --git
Xen advertises the underlying support for CPUID faulting but not does pass
through writes to the relevant MSR, nor does it virtualize it, so it does
not actually work. For now mask off the relevant bit on MSR_PLATFORM_INFO.
Signed-off-by: Kyle Huey
---
arch/x86/include/asm/cpufeatures.h | 1
On Mon, Sep 12, 2016 at 9:56 AM, Andy Lutomirski wrote:
> You should explicitly check that, if the
> feature is set under Xen PV, then the MSR actually works as
> advertised. This may require talking to the Xen folks to make sure
> you're testing the right configuration.
On Mon, Sep 12, 2016 at 9:56 AM, Andy Lutomirski wrote:
> You should explicitly check that, if the
> feature is set under Xen PV, then the MSR actually works as
> advertised. This may require talking to the Xen folks to make sure
> you're testing the right configuration.
This is interesting.
On Mon, Sep 12, 2016 at 7:15 AM, Kyle Huey <m...@kylehuey.com> wrote:
> On Mon, Sep 12, 2016 at 2:07 AM, Borislav Petkov <b...@suse.de> wrote:
>> On Sun, Sep 11, 2016 at 05:29:23PM -0700, Kyle Huey wrote:
>>> @@ -2162,6 +2168,12 @@ SYSCALL_DEFINE5(prctl, int, op
On Mon, Sep 12, 2016 at 7:15 AM, Kyle Huey wrote:
> On Mon, Sep 12, 2016 at 2:07 AM, Borislav Petkov wrote:
>> On Sun, Sep 11, 2016 at 05:29:23PM -0700, Kyle Huey wrote:
>>> @@ -2162,6 +2168,12 @@ SYSCALL_DEFINE5(prctl, int, option, unsigned long,
>>> arg2, unsigned
Thanks for the review!
On Mon, Sep 12, 2016 at 2:07 AM, Borislav Petkov <b...@suse.de> wrote:
> On Sun, Sep 11, 2016 at 05:29:23PM -0700, Kyle Huey wrote:
>> rr (http://rr-project.org/), a userspace record-and-replay reverse-
>> execution debugger, would like to trap
Thanks for the review!
On Mon, Sep 12, 2016 at 2:07 AM, Borislav Petkov wrote:
> On Sun, Sep 11, 2016 at 05:29:23PM -0700, Kyle Huey wrote:
>> rr (http://rr-project.org/), a userspace record-and-replay reverse-
>> execution debugger, would like to trap and emulate the CP
-technology-flexmigration-application-note.pdf.
I would like to thank Trevor Saunders <tbsau...@tbsaunde.org> for drafting
an earlier version of this patch.
Signed-off-by Kyle Huey <kh...@kylehuey.com>
---
arch/x86/include/asm/msr-index.h | 1 +
arch/x86/include/asm/proces
-technology-flexmigration-application-note.pdf.
I would like to thank Trevor Saunders for drafting
an earlier version of this patch.
Signed-off-by Kyle Huey
---
arch/x86/include/asm/msr-index.h | 1 +
arch/x86/include/asm/processor.h | 7
arch/x86/include/asm/thread_info.h | 4
On Thu, Aug 11, 2016 at 11:18 AM, Kees Cook wrote:
> On Thu, Aug 11, 2016 at 8:12 AM, Oleg Nesterov wrote:
>> On 08/10, Kees Cook wrote:
>>>
>>> This fixes a ptrace vs fatal pending signals bug as manifested in seccomp
>>> now that ptrace was reordered to
On Thu, Aug 11, 2016 at 11:18 AM, Kees Cook wrote:
> On Thu, Aug 11, 2016 at 8:12 AM, Oleg Nesterov wrote:
>> On 08/10, Kees Cook wrote:
>>>
>>> This fixes a ptrace vs fatal pending signals bug as manifested in seccomp
>>> now that ptrace was reordered to happen after ptrace. The short version
at there is a fatal
> signal pending and changes its state from TASK_TRACED to TASK_RUNNING.
> That prevents the ptracer's waitpid() from returning the ptrace event.
> A more detailed analysis is here:
> https://github.com/mozilla/rr/issues/1762#issuecomment-237396255.
>
> R
l
> signal pending and changes its state from TASK_TRACED to TASK_RUNNING.
> That prevents the ptracer's waitpid() from returning the ptrace event.
> A more detailed analysis is here:
> https://github.com/mozilla/rr/issues/1762#issuecomment-237396255.
>
> Reported-by: Robert O'Callahan
>
/khuey/3c43ac247c72cef8c956c does pass.
I don't see any obvious way to dequeue only the fatal signal, so instead I
dequeue them all. Since none of these signals will ever be delivered it
shouldn't affect the executing task.
Suggested-by: Robert O'Callahan <rob...@ocallahan.org>
Signed-off-by
/khuey/3c43ac247c72cef8c956c does pass.
I don't see any obvious way to dequeue only the fatal signal, so instead I
dequeue them all. Since none of these signals will ever be delivered it
shouldn't affect the executing task.
Suggested-by: Robert O'Callahan
Signed-off-by: Kyle Huey
---
kernel
On Sat, Jul 18, 2015 at 6:54 AM, Kyle Huey wrote:
> On Fri, Jul 17, 2015 at 4:59 PM, Thierry Reding
> wrote:
>> On Mon, Jul 13, 2015 at 10:35:45AM -0700, Kyle Huey wrote:
>>> This patch modifies the device tree for tegra124 based devices to enable
>>> the Cortex A
On Sat, Jul 18, 2015 at 6:54 AM, Kyle Huey m...@kylehuey.com wrote:
On Fri, Jul 17, 2015 at 4:59 PM, Thierry Reding
thierry.red...@gmail.com wrote:
On Mon, Jul 13, 2015 at 10:35:45AM -0700, Kyle Huey wrote:
This patch modifies the device tree for tegra124 based devices to enable
the Cortex
it to be
present if PTRACE_SYSEMU is present. Attempting to use PTRACE_SYSEMU_SINGLESTEP
will fail at runtime on ARM with EIO since there is no single stepping on ARM.
Signed-off-by: Kyle Huey
---
arch/arm/include/asm/thread_info.h | 8 ++--
arch/arm/include/uapi/asm/ptrace.h | 32
it to be
present if PTRACE_SYSEMU is present. Attempting to use PTRACE_SYSEMU_SINGLESTEP
will fail at runtime on ARM with EIO since there is no single stepping on ARM.
Signed-off-by: Kyle Huey kh...@kylehuey.com
---
arch/arm/include/asm/thread_info.h | 8 ++--
arch/arm/include/uapi/asm/ptrace.h | 32
On Fri, Jul 17, 2015 at 4:59 PM, Thierry Reding
wrote:
> On Mon, Jul 13, 2015 at 10:35:45AM -0700, Kyle Huey wrote:
>> This patch modifies the device tree for tegra124 based devices to enable
>> the Cortex A15 PMU. The interrupt numbers are taken from NVIDIA TRM
>> DP-06905-
On Fri, Jul 17, 2015 at 4:59 PM, Thierry Reding
thierry.red...@gmail.com wrote:
On Mon, Jul 13, 2015 at 10:35:45AM -0700, Kyle Huey wrote:
This patch modifies the device tree for tegra124 based devices to enable
the Cortex A15 PMU. The interrupt numbers are taken from NVIDIA TRM
DP-06905
This patch modifies the device tree for tegra124 based devices to enable
the Cortex A15 PMU. The interrupt numbers are taken from NVIDIA TRM
DP-06905-001_v03p. This patch was tested on a Jetson TK1.
Updated for proper ordering and to add interrupt-affinity values.
Signed-off-by: Kyle Huey
This patch modifies the device tree for tegra124 based devices to enable
the Cortex A15 PMU. The interrupt numbers are taken from NVIDIA TRM
DP-06905-001_v03p. This patch was tested on a Jetson TK1.
Updated for proper ordering and to add interrupt-affinity values.
Signed-off-by: Kyle Huey kh
This patch modifies the device tree for tegra124 based devices to enable the
Cortex A15 PMU. The interrupt numbers are taken from NVIDIA TRM
DP-06905-001_v03p. This patch was tested on a Jetson TK1.
Updated for proper ordering and to add interrupt-affinity values.
Signed-off-by: Kyle Huey
This patch modifies the device tree for tegra124 based devices to enable the
Cortex A15 PMU. The interrupt numbers are taken from NVIDIA TRM
DP-06905-001_v03p. This patch was tested on a Jetson TK1.
Updated for proper ordering and to add interrupt-affinity values.
Signed-off-by: Kyle Huey kh
This patch modifies the device tree for tegra124 based devices to enable the
Cortex A15 PMU. The interrupt numbers are taken from NVIDIA TRM
DP-06905-001_v03p. This patch was tested on a Jetson TK1.
Signed-off-by: Kyle Huey
---
arch/arm/boot/dts/tegra124.dtsi | 8
1 file changed, 8
This patch modifies the device tree for tegra124 based devices to enable the
Cortex A15 PMU. The interrupt numbers are taken from NVIDIA TRM
DP-06905-001_v03p. This patch was tested on a Jetson TK1.
Signed-off-by: Kyle Huey kh...@kylehuey.com
---
arch/arm/boot/dts/tegra124.dtsi | 8
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