From: huang lin
Refactor Innolux P079ZCA panel driver, let it support
multi panel.
Change-Id: If89be5e56dba8cb498e2d50c1bbeb0e8016123a2
Signed-off-by: Lin Huang
---
Changes in v2:
- Change regulator property name to meet the panel datasheet
Changes in v3:
- this patch only refactor P079ZCA
From: huang lin
The Innolux P097PFG panel is 9.7" panel with 1536X2048
resolution, it reuse P079ZCA panel driver, so improve
p079ZCA dt-binding to support P097PFG.
Change-Id: I8704914898fe53b734d31fbe646df8aa5fd8b30d
Signed-off-by: Lin Huang
---
Changes in v2:
- None
Changes in v3:
-
Support Innolux P097PFG 9.7" 1536x2048 TFT LCD panel, it reuse
the Innolux P079ZCA panel driver.
Change-Id: I97923aa3735f707332681691b0231c9421b427d0
Signed-off-by: Lin Huang
---
Changes in v2:
- None
Changes in v3:
- None
Changes in v4:
- download panel initial code
drivers/gpu/drm/
From: Chris Zhong
We may support training outside firmware, so we need support
dpcd read/write to get the message or do some setting with
display.
Signed-off-by: Chris Zhong
Signed-off-by: Lin Huang
Reviewed-by: Sean Paul
Reviewed-by: Enric Balletbo
---
Changes in v2:
- update patch
If want to do training outside DP Firmware, need phy voltage swing
and pre_emphasis value.
Signed-off-by: Lin Huang
---
Changes in v2:
- rebase
Changes in v3:
- modify property description and add this property to example
.../devicetree/bindings/phy/phy-rockchip-typec.txt | 29
as a fallback if sw training fails.
Signed-off-by: Chris Zhong
Signed-off-by: Lin Huang
---
Changes in v2:
- update patch following Enric suggest
Changes in v3:
- use variable fw_training instead sw_training_success
- base on DP SPCE, if training fail use lower link rate to retry training
drivers
the phy config values used to fix in dp firmware, but some boards
need change these values to do training and get the better eye diagram
result. So support that in phy driver.
Signed-off-by: Chris Zhong
Signed-off-by: Lin Huang
---
Changes in v2:
- update patch following Enric suggest
Changes
From: Chris Zhong
We may support training outside firmware, so we need support
dpcd read/write to get the message or do some setting with
display.
Signed-off-by: Chris Zhong
Signed-off-by: Lin Huang
Reviewed-by: Sean Paul
Reviewed-by: Enric Balletbo
---
Changes in v2:
- update patch
as a fallback if sw training fails.
Signed-off-by: Chris Zhong
Signed-off-by: Lin Huang
---
Changes in v2:
- update patch following Enric suggest
Changes in v3:
- use variable fw_training instead sw_training_success
- base on DP SPCE, if training fail use lower link rate to retry training
Changes in v4
If want to do training outside DP Firmware, need phy voltage swing
and pre_emphasis value.
Signed-off-by: Lin Huang
---
Changes in v2:
- None
Changes in v3:
- modify property description and add this property to Example
Change in v4:
- None
.../devicetree/bindings/phy/phy-rockchip-typec.txt
the phy config values used to fix in dp firmware, but some boards
need change these values to do training and get the better eye diagram
result. So support that in phy driver.
Signed-off-by: Chris Zhong
Signed-off-by: Lin Huang
---
Changes in v2:
- update patch following Enric suggest
Changes
.
Signed-off-by: Chris Zhong
Signed-off-by: Lin Huang
---
drivers/gpu/drm/rockchip/Makefile | 3 +-
drivers/gpu/drm/rockchip/cdn-dp-core.c | 23 +-
drivers/gpu/drm/rockchip/cdn-dp-core.h | 2 +
drivers/gpu/drm/rockchip/cdn-dp-link-training.c | 398
From: Chris Zhong
We may support training outside firmware, so we need support
dpcd read/write to get the message or do some setting with
display.
Signed-off-by: Chris Zhong
Signed-off-by: Lin Huang
---
drivers/gpu/drm/rockchip/cdn-dp-core.c | 55
drivers/gpu/drm
the phy config values used to fix in dp firmware, but some boards
need change these values to do training and get the better eye diagram
result. So support that in phy driver.
Signed-off-by: Chris Zhong
Signed-off-by: Lin Huang
---
drivers/phy/rockchip/phy-rockchip-typec.c | 286
If want to do training outside DP Firmware, need phy voltage swing
and pre_emphasis value.
Signed-off-by: Lin Huang
---
Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/phy
From: Chris Zhong
We may support training outside firmware, so we need support
dpcd read/write to get the message or do some setting with
display.
Signed-off-by: Chris Zhong
Signed-off-by: Lin Huang
Reviewed-by: Sean Paul
Reviewed-by: Enric Balletbo
---
Changes in v2:
- update patch
If want to do training outside DP Firmware, need phy voltage swing
and pre_emphasis value.
Signed-off-by: Lin Huang
---
Changes in v2:
- None
Changes in v3:
- modify property description and add this property to Example
Change in v4:
- None
Change in v5:
- None
.../devicetree/bindings/phy/phy
the phy config values used to fix in dp firmware, but some boards
need change these values to do training and get the better eye diagram
result. So support that in phy driver.
Signed-off-by: Chris Zhong
Signed-off-by: Lin Huang
---
Changes in v2:
- update patch following Enric suggest
Changes
as a fallback if sw training fails.
Signed-off-by: Chris Zhong
Signed-off-by: Lin Huang
---
Changes in v2:
- update patch following Enric suggest
Changes in v3:
- use variable fw_training instead sw_training_success
- base on DP SPCE, if training fail use lower link rate to retry training
Changes in v4
From: Chris Zhong
We may support training outside firmware, so we need support
dpcd read/write to get the message or do some setting with
display.
Signed-off-by: Chris Zhong
Signed-off-by: Lin Huang
---
Changes in v2:
- update patch following Enric suggest
drivers/gpu/drm/rockchip/cdn-dp
the phy config values used to fix in dp firmware, but some boards
need change these values to do training and get the better eye diagram
result. So support that in phy driver.
Signed-off-by: Chris Zhong
Signed-off-by: Lin Huang
---
Changes in v2:
- update patch following Enric suggest
drivers
If want to do training outside DP Firmware, need phy voltage swing
and pre_emphasis value.
Signed-off-by: Lin Huang
---
Changes in v2:
- rebase
Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation
as a fallback if sw training fails.
Signed-off-by: Chris Zhong
Signed-off-by: Lin Huang
---
Changes in v2:
- update patch following Enric suggest
drivers/gpu/drm/rockchip/Makefile | 3 +-
drivers/gpu/drm/rockchip/cdn-dp-core.c | 24 +-
drivers/gpu/drm/rockchip/cdn-dp
From: Chris Zhong
We may support training outside firmware, so we need support
dpcd read/write to get the message or do some setting with
display.
Signed-off-by: Chris Zhong
Signed-off-by: Lin Huang
Reviewed-by: Sean Paul
Reviewed-by: Enric Balletbo
---
Changes in v2:
- update patch
If want to do training outside DP Firmware, need phy voltage swing
and pre_emphasis value.
Signed-off-by: Lin Huang
---
Changes in v2:
- None
Changes in v3:
- modify property description and add this property to Example
Changes in v4:
- None
Changes in v5:
- None
Changes in v6:
- change
we may use rockchip_phy_typec struct in other driver, so split
it to separate header.
Signed-off-by: Lin Huang
---
Changes in v2:
- None
Changes in v3:
- None
Changes in v4:
- None
Changes in v5:
- None
Changes in v6:
- new patch here
drivers/phy/rockchip/phy-rockchip-typec.c | 47
the phy config values used to fix in dp firmware, but some boards
need change these values to do training and get the better eye diagram
result. So support that in phy driver.
Signed-off-by: Chris Zhong
Signed-off-by: Lin Huang
---
Changes in v2:
- update patch following Enric suggest
Changes
as a fallback if sw training fails.
Signed-off-by: Chris Zhong
Signed-off-by: Lin Huang
Reviewed-by: Sean Paul
---
Changes in v2:
- update patch following Enric suggest
Changes in v3:
- use variable fw_training instead sw_training_success
- base on DP SPCE, if training fail use lower link rate to retry
From: huang lin
there may use enable pin to control dmic start and stop,
so add this property in dt-bindings.
Signed-off-by: Lin Huang
---
Documentation/devicetree/bindings/sound/dmic.txt | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/sound/dmic.txt
From: huang lin
on some board use enable pin to control dmic start and stop,
so add this feature in dmic driver.
Signed-off-by: Lin Huang
---
sound/soc/codecs/Kconfig | 2 +-
sound/soc/codecs/dmic.c | 46 ++
2 files changed, 47 insertions(+), 1
some i2c hid devices have reset gpio, need to control
it in the driver.
Signed-off-by: Lin Huang
---
Changes in v2:
- Add 10us in usleep_range() upper range
- reuse post_power_delay_ms as deassert reset delay
- delete deassert_reset_us property
drivers/hid/i2c-hid/i2c-hid.c | 61
Document a "reset" and "assert-reset-us", it can be used for
driver control reset property. And reuse post-power-on-delay-ms
for deassert reset delay.
Signed-off-by: Lin Huang
---
Documentation/devicetree/bindings/input/hid-over-i2c.txt | 4 +++-
1 file changed, 3 inser
some i2c hid devices have reset gpio, need to control
it in the driver.
Change-Id: I87bca954bffc7eb7b35711406f522cb3d0fc2ded
Signed-off-by: Lin Huang
---
drivers/hid/i2c-hid/i2c-hid.c | 63 +++
include/linux/platform_data/i2c-hid.h | 4 +++
2 files
there may use enable pin to control dmic start and stop,
so add this property in dt-bindings.
Signed-off-by: Lin Huang
---
Documentation/devicetree/bindings/sound/dmic.txt | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/sound/dmic.txt
b/Documentation
on some board use enable pin to control dmic start and stop,
so add this feature in dmic driver.
Signed-off-by: Lin Huang
---
sound/soc/codecs/Kconfig | 2 +-
sound/soc/codecs/dmic.c | 61
2 files changed, 62 insertions(+), 1 deletion(-)
diff
The Innolux P097PFG panel is 9.7" panel with 1536X2048
resolution, it reuse P079ZCA panel driver, so improve
p079ZCA dt-binding to support P097PFG.
Signed-off-by: Lin Huang
---
.../devicetree/bindings/display/panel/innolux,p079zca.txt | 11 +--
1 file changed, 9 insertions(
Support Innolux P097PFG 9.7" 1536x2048 TFT LCD panel,
it refactor Innolux P079ZCA panel driver, let it support
multi panel, and add support P097PFG panel in this driver.
Signed-off-by: Lin Huang
---
Changes in v2:
- change regulator property name to meet the panel datasheet
drivers/gp
Support Innolux P097PFG 9.7" 1536x2048 TFT LCD panel, it reuse
the Innolux P079ZCA panel driver.
Signed-off-by: Lin Huang
---
drivers/gpu/drm/panel/Kconfig | 9
drivers/gpu/drm/panel/panel-innolux-p079zca.c | 31 +++
2 files change
The Innolux P097PFG panel is 9.7" panel with 1536X2048
resolution, it reuse P079ZCA panel driver, so improve
p079ZCA dt-binding to support P097PFG.
Change-Id: I8704914898fe53b734d31fbe646df8aa5fd8b30d
Signed-off-by: Lin Huang
---
.../devicetree/bindings/display/panel/innolux,p079zc
Refactor Innolux P079ZCA panel driver, let it support
multi panel.
Signed-off-by: Lin Huang
---
Changes in v2:
- Change regulator property name to meet the panel datasheet
Changes in v3:
- this patch only refactor P079ZCA panel to support multi panel, support
P097PFG panel in another patch
Refactor Innolux P079ZCA panel driver, let it support
multi panel.
Signed-off-by: Lin Huang
---
Changes in v2:
- Change regulator property name to meet the panel datasheet
Changes in v3:
- this patch only refactor P079ZCA panel to support multi panel, support
P097PFG panel in another patch
Support Innolux P097PFG 9.7" 1536x2048 TFT LCD panel, it reuse
the Innolux P079ZCA panel driver.
Signed-off-by: Lin Huang
---
drivers/gpu/drm/panel/Kconfig | 9
drivers/gpu/drm/panel/panel-innolux-p079zca.c | 31 +++
2 files change
The Innolux P097PFG panel is 9.7" panel with 1536X2048
resolution, it reuse P079ZCA panel driver, so improve
p079ZCA dt-binding to support P097PFG.
Signed-off-by: Lin Huang
---
.../devicetree/bindings/display/panel/innolux,p079zca.txt | 11 +--
1 file changed, 9 insertions(
Support Innolux P097PFG 9.7" 1536x2048 TFT LCD panel,
it refactor Innolux P079ZCA panel driver, let it support
multi panel, and add support P097PFG panel in this driver.
Change-Id: If342e58a3de2861219b0b1313f402b6cb41ffa29
Signed-off-by: Lin Huang
---
drivers/gpu/drm/panel/panel-in
Support Innolux P097PFG 9.7" 1536x2048 TFT LCD panel,
it refactor Innolux P079ZCA panel driver, let it support
multi panel, and add support P097PFG panel in this driver.
Signed-off-by: Lin Huang
---
drivers/gpu/drm/panel/panel-innolux-p079zca.c | 178 --
1 file ch
From: huang lin h...@rock-chips.com
gpio can keep state even the clock disable, for save power
consumption, only enable gpio clock when it setting
Signed-off-by: Heiko Stuebner he...@sntech.de
Signed-off-by: Lin Huang h...@rock-chips.com
---
Changes in v2:
Advices by Douglas Anderson
-use
From: huang lin h...@rock-chips.com
pclk_pd_pmu needs to keep running and with the upcoming gpio clock
handling this is not always the case anymore. So add it to the list
of critical clocks for now.
Signed-off-by: Heiko Stuebner he...@sntech.de
Signed-off-by: Lin Huang h...@rock-chips.com
pclk_pd_pmu needs to keep running and with the upcoming gpio clock
handling this is not always the case anymore. So add it to the list
of critical clocks for now.
Signed-off-by: Heiko Stuebner he...@sntech.de
Signed-off-by: Lin Huang h...@rock-chips.com
---
Changes in v3:
-match the author
gpio can keep state even the clock disable, for save power
consumption, only enable gpio clock when it setting
Signed-off-by: Heiko Stuebner he...@sntech.de
Signed-off-by: Lin Huang h...@rock-chips.com
---
Changes in v3:
-match author and Signed-off-by name
drivers/pinctrl/pinctrl-rockchip.c
gpio can keep state even the clock disable, for save power
consumption, only enable gpio clock when it setting
Signed-off-by: Lin Huang h...@rock-chips.com
Reviewed-by: Heiko Stuebner he...@sntech.de
---
Changes in v5:
-rebase patch
drivers/pinctrl/pinctrl-rockchip.c | 55
From: Heiko Stuebner he...@sntech.de
pclk_pd_pmu needs to keep running and with the upcoming gpio clock
handling this is not always the case anymore. So add it to the list
of critical clocks for now.
Signed-off-by: Heiko Stuebner he...@sntech.de
Signed-off-by: Lin Huang h...@rock-chips.com
gpio can keep state even the clock disable, for save power
consumption, only enable gpio clock when it setting
Signed-off-by: Lin Huang h...@rock-chips.com
Reviewed-by: Heiko Stuebner he...@sntech.de
---
Changes in v4:
-delete some unrelated new blank line
drivers/pinctrl/pinctrl-rockchip.c
pclk_pd_pmu needs to keep running and with the upcoming gpio clock
handling this is not always the case anymore. So add it to the list
of critical clocks for now.
From: Heiko Stuebner he...@sntech.de
Signed-off-by: Lin Huang h...@rock-chips.com
---
Changes in v4:
- Add From: Heiko Stuebner he
rk3399 do ddr frequency scaling use devfreq framework,
use simple_ondemand policy, and use rk3399 dfi controller
to get ddr busy time.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
drivers/devfreq/Kconfig | 1 +
drivers/devfreq/Makefile | 1 +
drivers/d
support rk3399 dmc clock driver. Note, ddr set rate function will
use dcf controller which run in ATF, it need to fishish it when rk3399
arm trust firmware ready.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk-
these patchset bring up rk3399 ddr frequency scaling flow,
use devfreq framework and simple_ondemand policy. Ddr set
rate function will implement in dcf controller which run in
the ATF, and rk3399 ATF not ready now, so we need finish it
when rk3399 ATF ready.
Lin Huang (2):
clk: rockchip: dmc
add ddrc clock setting, so we can do ddr frequency
scaling on rk3399 platform in future.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v2:
- remove clk_ddrc_dpll_src from critical clock list
Changes in v1:
- remove ddrc source CLK_IGNORE_UNUSED flag
- move cl
On new rockchip platform(rk3399 etc), there have dcf controller to
do ddr frequency scaling, and this controller will implement in
arm-trust-firmware. We add a special clock-type to handle that.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v2:
- use GENMASK instead va
on rk3399 platform, there is dfi conroller can monitor
ddr load, base on this result, we can do ddr freqency
scaling.
Signed-off-by: Lin Huang <h...@rock-chips.com>
Acked-by: Chanwoo Choi <cw00.c...@samsung.com>
---
Changes in v2:
- use clk_disable_unprepare and clk_enable_prep
low
| |
| |
wait dcf interrupt<---trigger dcf interrupt
|
|
return
Lin Huang (6):
clk: rockchip: add new clock-type for the ddrclk
clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc
clk: ro
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v2:
- None
Changes in v1:
- None
include/dt-bindings/clock/rk3399-cru.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/rk3399-cru.h
b/include/dt-bindings/clock/rk3399-cru.h
index 50a44cf..8a
when in ddr frequency scaling process, vop can not do
enable or disable operate, since dcf will base on vop vblank
time to do frequency scaling and need to get vop irq if there
have vop enabled. So need register to dmc notifier, and we can
get the dmc status.
Signed-off-by: Lin Huang <h...@r
base on dfi result, we do ddr frequency scaling, register
dmc driver to devfreq framework, and use simple-ondemand
policy.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v2:
- None
Changes in v1:
- move dfi controller to event
- fix set voltage sequence when set rat
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v1:
- None
include/dt-bindings/clock/rk3399-cru.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/rk3399-cru.h
b/include/dt-bindings/clock/rk3399-cru.h
index 50a44cf..8a0f0442 100644
--- a/incl
when in ddr frequency scaling process, vop can not do
enable or disable operate, since dcf will base on vop vblank
time to do frequency scaling and need to get vop irq if there
have vop enabled. So need register to dmc notifier, and we can
get the dmc status.
Signed-off-by: Lin Huang <h...@r
base on dfi result, we do ddr frequency scaling, register
dmc driver to devfreq framework, and use simple-ondemand
policy.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v1:
- move dfi controller to event, Suggestion by Chanwoo Choi
- fix set voltage sequence when set rat
On new rockchip platform(rk3399 etc), there have dcf controller to
do ddr frequency scaling, and this controller will implement in
arm-trust-firmware. We add a special clock-type to handle that.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v1:
- None
drivers/clk/ro
low
| |
| |
wait dcf interrupt<---trigger dcf interrupt
|
|
return
Lin Huang (6):
rockchip: rockchip: add new clock-type for the ddrclk
clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc
on rk3399 platform, there is dfi conroller can monitor
ddr load, base on this result, we can do ddr freqency
scaling.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v1:
- NOne
drivers/devfreq/event/Kconfig| 7 +
drivers/devfreq/event/Makefile | 1 +
d
add ddrc clock setting, so we can do ddr frequency
scaling on rk3399 platform in future.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v1:
- remove ddrc source CLK_IGNORE_UNUSED flag, Suggestion by Doug
- move clk_ddrc and clk_ddrc_dpll_src to critical, Suggestion b
On new rockchip platform(rk3399 etc), there have dcf controller to
do ddr frequency scaling, and this controller will implement in
arm-trust-firmware. We add a special clock-type to handle that.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
drivers/clk/rockchip/Makefile | 1 +
d
there is dfi controller on rk3399 platform, it can monitor
ddr load, register this controller to devfreq framework, and
default to use simple_ondeamnd policy, and do ddr frequency
scaling base on this result.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
drivers/devfreq/K
when in ddr frequency scaling process, vop can not do
enable or disable operate, since dcf will base on vop vblank
time to do frequency scaling and need to get vop irq if there
have vop enabled. So need register to dmc notifier, and we can
get the dmc status.
Signed-off-by: Lin Huang <h...@r
low
| |
| |
wait dcf interrupt<---trigger dcf interrupt
|
|
return
Lin Huang (4):
rockchip: rockchip: add new clock-type for the ddrclk
clk: rockchip: rk3399: add ddrc clock support
PM / d
add ddrc clock setting, so we can do ddr frequency
scaling on rk3399 platform in future.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3399.c | 16
include/dt-bindings/clock/rk3399-cru.h | 1 +
2 files changed, 17 insertions(+)
diff
From: Heiko St??bner <he...@sntech.de>
add clock flag parameter so we can pass specific clock flag
(like CLK_GET_RATE_NOCACHE etc..)to pll driver.
Change-Id: I1e076b3efa6b5da082b6e68e2e2a4c9dfd93e3d4
Signed-off-by: Heiko St??bner <he...@sntech.de>
Signed-off-by: Lin Huang <h...
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v4:
-None
Changes in v3:
-None
Changes in v2:
- None
Changes in v1:
- None
include/dt-bindings/clock/rk3399-cru.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/rk3399-cru.h
b/include/dt-bi
add ddrc clock setting, so we can do ddr frequency
scaling on rk3399 platform in future.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v4:
- None
Changes in v3:
- None
Changes in v2:
- remove clk_ddrc_dpll_src from critical clock list
Changes in v1:
- remove ddrc
enabled, we need
to disable dmc, since dcf only base on one vop vblank time, so the
other panel will flicker when do ddr frequency scaling.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v4:
- register notifier to devfreq_register_notifier
- use DEVFREQ_PRECHANGE and DEVFREQ_POST
base on dfi result, we do ddr frequency scaling, register
dmc driver to devfreq framework, and use simple-ondemand
policy.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v4:
- use arm_smccc_smc() function talk to bl31
- delete rockchip_dmc.c file and config
- delete dmc_
on rk3399 platform, there is dfi conroller can monitor
ddr load, base on this result, we can do ddr freqency
scaling.
Signed-off-by: Lin Huang <h...@rock-chips.com>
Acked-by: Chanwoo Choi <cw00.c...@samsung.com>
---
Changes in v4:
- None
Changes in v3:
- None
Changes
On new rockchip platform(rk3399 etc), there have dcf controller to
do ddr frequency scaling, and this controller will implement in
arm-trust-firmware. We add a special clock-type to handle that.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v4:
- use arm_smccc_smc() to se
From: Heiko Stübner <he...@sntech.de>
add clock flag parameter so we can pass specific clock flag
(like CLK_GET_RATE_NOCACHE etc..)to pll driver.
Signed-off-by: Heiko Stübner <he...@sntech.de>
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v4:
- None
Cha
low
| |
| |
wait dcf interrupt<---trigger dcf interrupt
|
|
return
Lin Huang (6):
clk: rockchip: add new clock-type for the ddrclk
clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc
clk: ro
base on dfi result, we do ddr frequency scaling, register
dmc driver to devfreq framework, and use simple-ondemand
policy.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v5:
- improve dmc driver suggest by Chanwoo Choi
Changes in v4:
- use arm_smccc_smc() function talk t
add ddrc clock setting, so we can do ddr frequency
scaling on rk3399 platform in future.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v5:
- fit for the ddr type
Changes in v4:
- None
Changes in v3:
- None
Changes in v2:
- remove clk_ddrc_dpll_src from critical cloc
on rk3399 platform, there is dfi conroller can monitor
ddr load, base on this result, we can do ddr freqency
scaling.
Signed-off-by: Lin Huang <h...@rock-chips.com>
Acked-by: Chanwoo Choi <cw00.c...@samsung.com>
---
Changes in v5:
-None
Changes in v4:
-None
Changes in v3:
-None
C
enabled, we need
to disable dmc, since dcf only base on one vop vblank time, so the
other panel will flicker when do ddr frequency scaling.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v5:
- improve some nits
Changes in v4:
- register notifier to devfreq_register_notifier
low
| |
| |
wait dcf interrupt<---trigger dcf interrupt
|
|
return
Lin Huang (8):
clk: rockchip: add new clock-type for the ddrclk
clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc
clk: ro
On new rockchip platform(rk3399 etc), there have dcf controller to
do ddr frequency scaling, and this controller will implement in
arm-trust-firmware. We add a special clock-type to handle that.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v5:
- delete unuse mux_flag
This patch adds the documentation for rockchip rk3399 dmc driver.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v5:
-None
Changes in v4:
-None
Changes in v3:
-None
Changes in v2:
-None
Changes in v1:
-None
.../devicetree/bindings/devfreq/rk3399_dmc.txt
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v5:
-None
Changes in v4:
-None
Changes in v3:
-None
Changes in v2:
-None
Changes in v1:
-None
include/dt-bindings/clock/rk3399-cru.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/rk3399-cr
This patch adds the documentation for rockchip dfi devfreq-event driver.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v5:
-None
Changes in v4:
-None
Changes in v3:
-None
Changes in v2:
-None
Changes in v1:
-None
.../bindings/devfreq/event/rockchip-dfi.txt
low
| |
| |
wait dcf interrupt<---trigger dcf interrupt
|
|
return
Lin Huang (6):
clk: rockchip: add new clock-type for the ddrclk
clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc
clk: ro
when in ddr frequency scaling process, vop can not do
enable or disable operate, since dcf will base on vop vblank
time to do frequency scaling and need to get vop irq if there
have vop enabled. So need register to dmc notifier, and we can
get the dmc status.
Signed-off-by: Lin Huang <h...@r
add ddrc clock setting, so we can do ddr frequency
scaling on rk3399 platform in future.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v3:
- None
Changes in v2:
- remove clk_ddrc_dpll_src from critical clock list
Changes in v1:
- remove ddrc source CLK_IGNORE_UNUSED flag
On new rockchip platform(rk3399 etc), there have dcf controller to
do ddr frequency scaling, and this controller will implement in
arm-trust-firmware. We add a special clock-type to handle that.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v3:
- use sip call to set/read dd
on rk3399 platform, there is dfi conroller can monitor
ddr load, base on this result, we can do ddr freqency
scaling.
Signed-off-by: Lin Huang <h...@rock-chips.com>
Acked-by: Chanwoo Choi <cw00.c...@samsung.com>
---
Changes in v3:
- None
Changes in v2:
- use clk_disab
base on dfi result, we do ddr frequency scaling, register
dmc driver to devfreq framework, and use simple-ondemand
policy.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v3:
- operate dram setting through sip call
- imporve set rate flow
Changes in v2:
- None
Changes
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v3:
-None
Changes in v2:
- None
Changes in v1:
- None
include/dt-bindings/clock/rk3399-cru.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/rk3399-cru.h
b/include/dt-bindings/clock/rk3399-cru.h
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