On Mon, Aug 25, 2014 at 07:17:15PM -0700, Stephen Boyd wrote:
On 08/25/14 17:31, Lina Iyer wrote:
On Mon, Aug 25, 2014 at 04:40:33PM -0700, Stephen Boyd wrote:
On 08/19/14 15:15, Lina Iyer wrote:
diff --git a/Documentation/devicetree/bindings/arm/msm/spm.txt
b/Documentation/devicetree
On Mon, 4 Aug 2014, Stephen Boyd wrote:
Architectural changes in the ARM Linux kernel tree mandate
the eventual removal of the mach-* directories. Move the
scm driver to drivers/soc/qcom and the scm header to
include/soc/qcom to support that removal.
Signed-off-by: Stephen Boyd
On Tue, 5 Aug 2014, Bjorn Andersson wrote:
On Mon, Aug 4, 2014 at 9:07 PM, Lina Iyer lina.i...@linaro.org wrote:
On Mon, 4 Aug 2014, Stephen Boyd wrote:
[...]
Could we move scm-boot.c as well to drivers/soc/qcom and scm-boot.h to
include/soc/qcom ?
Yes, we can do
to the core(s) that the IRQ has been
migrated to.
The userspace sysfs interface does not support IRQ affinity.
Signed-off-by: Praveen Chidambaram pchid...@codeaurora.org
Signed-off-by: Lina Iyer lina.i...@linaro.org
[lina.iyer: Split the change from a previous change, add commit text]
diff --git
of the request will continue to be effected on all cores.
The userspace sysfs interface does not support setting cpumask of a PM
QoS request.
Signed-off-by: Praveen Chidambaram pchid...@codeaurora.org
Signed-off-by: Lina Iyer lina.i...@linaro.org
[lina.iyer: rework, add commit text, split changes
the irq_affinity_notify object while the
work function was scheduled, it will not be notified.
Signed-off-by: Lina Iyer lina.i...@linaro.org
diff --git a/drivers/infiniband/hw/qib/qib_iba7322.c
b/drivers/infiniband/hw/qib/qib_iba7322.c
index a7eb325..62cb77d 100644
--- a/drivers/infiniband/hw/qib
to userspace at this point, i.e, userspace cannot specify a QoS
request against a cpu or specify an IRQ to tag this request against.
Thanks,
Lina
Lina Iyer (4):
QoS: Modify data structures and function arguments for scalability.
QoS: Enhance framework to support per-cpu PM QoS request
irq: Allow
to be broken.
Use pm_qos_request objects instead of passing around the protected
priority list object.
Signed-off-by: Praveen Chidambaram pchid...@codeaurora.org
Signed-off-by: Lina Iyer lina.i...@linaro.org
diff --git a/drivers/base/power/qos.c b/drivers/base/power/qos.c
index 36b9eb4..67a66b1 100644
On Wed, Aug 27 2014 at 14:56 -0600, Thomas Gleixner wrote:
On Wed, 27 Aug 2014, Lina Iyer wrote:
PM QoS and other idle frameworks can do a better job of addressing power
and performance requirements for a cpu, knowing the IRQs that are
affine to that cpu. If a performance request is placed
On Tue, Sep 02 2014 at 14:56 -0600, Thomas Gleixner wrote:
On Tue, 2 Sep 2014, Lina Iyer wrote:
On Wed, Aug 27 2014 at 14:56 -0600, Thomas Gleixner wrote:
On Wed, 27 Aug 2014, Lina Iyer wrote:
All you are describing is the fact, that there is only a single
notifier possible right now
Resending...
Hoping to retain the thread information, this time.
On Tue, Sep 02 2014 at 14:56 -0600, Thomas Gleixner wrote:
On Tue, 2 Sep 2014, Lina Iyer wrote:
On Wed, Aug 27 2014 at 14:56 -0600, Thomas Gleixner wrote:
On Wed, 27 Aug 2014, Lina Iyer wrote:
All you are describing
Hi Thomas,
On Fri, Oct 17 2014 at 01:29 -0600, Thomas Gleixner wrote:
On Fri, 10 Oct 2014, Lina Iyer wrote:
On Wed, Oct 08 2014 at 09:03 -0600, Thomas Gleixner wrote:
On Thu, 25 Sep 2014, Lina Iyer wrote:
How would a general keep track of the targets of all interrupts in
the system
.
The userspace sysfs interface does not support setting cpumask of a PM
QoS request.
Signed-off-by: Lina Iyer lina.i...@linaro.org
Based on work by: Praveen Chidambaram pchid...@codeaurora.org
https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/kernel/power?h=LNX.LA.3.7
---
Documentation
. Explore possibility of optimizations.
- Update cpuidle to use the per-cpu PM QoS to query the QoS value of the cpus
interested.
Thanks,
Lina
Lina Iyer (4):
QoS: Modify data structures and function arguments for scalability.
QoS: Enhance PM QoS framework to support per-cpu QoS request
irq
to be broken.
Use pm_qos_request objects instead of passing around the protected
priority list object.
Signed-off-by: Lina Iyer lina.i...@linaro.org
Acked-by: Kevin Hilman khil...@linaro.org
---
drivers/base/power/qos.c | 14 +++---
include/linux/pm_qos.h | 7 ---
kernel/power/qos.c
to.
The userspace sysfs interface does not support IRQ affinity.
Signed-off-by: Lina Iyer lina.i...@linaro.org
Based on work by: Praveen Chidambaram pchid...@codeaurora.org
---
Documentation/power/pm_qos_interface.txt | 4 +++-
include/linux/pm_qos.h | 3 +++
kernel/irq/manage.c
Export irq_get_affinity API for drivers to read the smp affinity of an
IRQ safely.
Signed-off-by: Lina Iyer lina.i...@linaro.org
---
include/linux/interrupt.h | 8
kernel/irq/manage.c | 18 ++
2 files changed, 26 insertions(+)
diff --git a/include/linux
On Wed, Oct 08 2014 at 09:03 -0600, Thomas Gleixner wrote:
On Thu, 25 Sep 2014, Lina Iyer wrote:
How would a general keep track of the targets of all interrupts in
the system mechanism make use of this?
Sorry, I do not understand your question.
PM QoS is only interested in the IRQs specified
On Wed, Jan 28 2015 at 14:42 -0700, Javi Merino wrote:
The power allocator governor is a thermal governor that controls system
and device power allocation to control temperature. Conceptually, the
implementation divides the sustainable power of a thermal zone among
all the heat sources in that
On Tue, Feb 03 2015 at 08:30 -0700, Eduardo Valentin wrote:
On Tue, Feb 03, 2015 at 01:03:37PM +, Javi Merino wrote:
On Mon, Feb 02, 2015 at 11:51:20PM +, Lina Iyer wrote:
On Wed, Jan 28 2015 at 14:42 -0700, Javi Merino wrote:
The power allocator governor is a thermal governor
On Tue, Feb 03 2015 at 02:59 -0700, Stanimir Varbanov wrote:
Hi Gilad,
Thanks for the patch.
On 01/31/2015 02:46 AM, Gilad Avidov wrote:
Qualcomm PMIC Arbiter version-2 changes from version-1 are:
- Some different register offsets.
- New channel register space, one per PMIC peripheral
On Tue, Feb 03 2015 at 12:20 -0700, Eduardo Valentin wrote:
On Tue, Feb 03, 2015 at 10:32:11AM -0700, Lina Iyer wrote:
big cut
Well, I am not convinced drivers really need to be aware of these trip
types. Which kind of drivers are we talking? Thermal zone drivers?
cooling device drivers?
I
On Wed, Mar 18 2015 at 09:56 -0600, Bjorn Andersson wrote:
On Thu 12 Mar 12:31 PDT 2015, Lina Iyer wrote:
On Fri, Feb 27 2015 at 15:30 -0700, Bjorn Andersson wrote:
Add driver for Qualcomm Hardware Mutex block found in many Qualcomm
SoCs.
Based on initial effort by Kumar Gala ga
On Wed, Mar 18 2015 at 10:12 -0600, Bjorn Andersson wrote:
On Thu 12 Mar 15:29 PDT 2015, Lina Iyer wrote:
On Fri, Feb 27 2015 at 15:30 -0700, Bjorn Andersson wrote:
Add driver for Qualcomm Hardware Mutex block found in many Qualcomm
SoCs.
Based on initial effort by Kumar Gala ga
On Fri, Mar 13 2015 at 14:02 -0600, Andy Gross wrote:
On Thu, Mar 12, 2015 at 04:16:00PM -0600, Lina Iyer wrote:
snip
It looks like the remote side unlocks it too? It doesn't seem like this
will work with the framework very well. The framework has a kernel
spinlock attached to the hwspinlock
On Thu, Mar 12 2015 at 14:35 -0600, Stephen Boyd wrote:
On 03/12/15 12:38, Lina Iyer wrote:
---
sign off?
:) I was just hacking it to make it easier to understand. Sure.
drivers/hwspinlock/qcom_hwspinlock.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff
On Thu, Mar 12 2015 at 14:49 -0600, Andy Gross wrote:
On Thu, Mar 12, 2015 at 01:38:28PM -0600, Lina Iyer wrote:
snip
static int qcom_hwspinlock_trylock(struct hwspinlock *lock)
{
struct regmap_field *field = lock-priv;
u32 lock_owner;
int ret;
+ u32 proc_id
---
drivers/hwspinlock/qcom_hwspinlock.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/hwspinlock/qcom_hwspinlock.c
b/drivers/hwspinlock/qcom_hwspinlock.c
index 93b62e0..7642524 100644
--- a/drivers/hwspinlock/qcom_hwspinlock.c
+++
On Fri, Feb 27 2015 at 15:30 -0700, Bjorn Andersson wrote:
Add driver for Qualcomm Hardware Mutex block found in many Qualcomm
SoCs.
Based on initial effort by Kumar Gala ga...@codeaurora.org
Signed-off-by: Bjorn Andersson bjorn.anders...@sonymobile.com
---
[...]
+#include
On Thu, Mar 12 2015 at 13:43 -0600, Andy Gross wrote:
On Thu, Mar 12, 2015 at 01:31:50PM -0600, Lina Iyer wrote:
On Fri, Feb 27 2015 at 15:30 -0700, Bjorn Andersson wrote:
Add driver for Qualcomm Hardware Mutex block found in many Qualcomm
SoCs.
Based on initial effort by Kumar Gala ga
On Thu, Mar 12 2015 at 15:12 -0600, Stephen Boyd wrote:
On 03/12/15 13:48, Lina Iyer wrote:
On Thu, Mar 12 2015 at 14:35 -0600, Stephen Boyd wrote:
On 03/12/15 12:38, Lina Iyer wrote:
---
sign off?
:) I was just hacking it to make it easier to understand. Sure.
drivers/hwspinlock
On Fri, Feb 27 2015 at 15:30 -0700, Bjorn Andersson wrote:
Add driver for Qualcomm Hardware Mutex block found in many Qualcomm
SoCs.
Based on initial effort by Kumar Gala ga...@codeaurora.org
Signed-off-by: Bjorn Andersson bjorn.anders...@sonymobile.com
+config HWSPINLOCK_QCOM
+ tristate
On Wed, Mar 18 2015 at 12:46 -0600, Daniel Lezcano wrote:
Some architectures have some cpus which does not support idle states.
Let the underlying low level code to return -ENOSYS when it is not
possible to set an idle state.
Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
---
On Thu, Mar 19 2015 at 09:33 -0600, Daniel Lezcano wrote:
On 03/19/2015 04:31 PM, Lina Iyer wrote:
On Wed, Mar 18 2015 at 12:46 -0600, Daniel Lezcano wrote:
Some architectures have some cpus which does not support idle states.
Let the underlying low level code to return -ENOSYS when
On Thu, Apr 02 2015 at 15:12 -0600, Kevin Hilman wrote:
On Thu, Apr 2, 2015 at 12:12 PM, Lina Iyer lina.i...@linaro.org wrote:
On Wed, Apr 01 2015 at 15:57 -0600, Kevin Hilman wrote:
Andrew Morton a...@linux-foundation.org writes:
On Wed, 01 Apr 2015 10:47:49 +0100 Marc Zyngier marc.zyng
On Wed, Apr 01 2015 at 15:57 -0600, Kevin Hilman wrote:
Andrew Morton a...@linux-foundation.org writes:
On Wed, 01 Apr 2015 10:47:49 +0100 Marc Zyngier marc.zyng...@arm.com wrote:
-static int unmap_and_move(new_page_t get_new_page, free_page_t put_new_page,
- unsigned long
-a...@ti.com
Cc: Andy Gross agr...@codeaurora.org
Signed-off-by: Lina Iyer lina.i...@linaro.org
---
drivers/hwspinlock/hwspinlock_core.c | 56
include/linux/hwspinlock.h | 1 +
2 files changed, 32 insertions(+), 25 deletions(-)
diff --git a/drivers/hwspinlock
On Fri, May 01 2015 at 11:27 -0600, Jeffrey Hugo wrote:
On 5/1/2015 11:06 AM, Lina Iyer wrote:
diff --git a/drivers/hwspinlock/qcom_hwspinlock.c
b/drivers/hwspinlock/qcom_hwspinlock.c
index 93b62e0..043c62c 100644
--- a/drivers/hwspinlock/qcom_hwspinlock.c
+++ b/drivers/hwspinlock
to be released
since they would have a different proc id. This value is specific for
the lock #7 only.
Cc: Jeffrey Hugo jh...@codeaurora.org
Cc: Bjorn Andersson bjorn.anders...@sonymobile.com
Cc: Andy Gross agr...@codeaurora.org
Signed-off-by: Lina Iyer lina.i...@linaro.org
---
drivers/hwspinlock
On Sat, May 09 2015 at 03:25 -0600, Ohad Ben-Cohen wrote:
Hi Lina,
On Fri, May 1, 2015 at 8:07 PM, Lina Iyer lina.i...@linaro.org wrote:
Some uses of the hwspinlock could be that one entity acquires the lock
and the other entity releases the lock. This allows for a serialized
traversal path
On Sat, May 16 2015 at 03:03 -0600, Ohad Ben-Cohen wrote:
On Mon, May 11, 2015 at 5:46 PM, Lina Iyer lina.i...@linaro.org wrote:
On Sat, May 09 2015 at 03:25 -0600, Ohad Ben-Cohen wrote:
On Fri, May 1, 2015 at 8:07 PM, Lina Iyer lina.i...@linaro.org wrote:
Let's discuss whether we really want
On Tue, Apr 14 2015 at 16:32 -0600, Lorenzo Pieralisi wrote:
On Tue, Apr 14, 2015 at 03:21:17PM +0100, Kumar Gala wrote:
[...]
Looking beyond this set of patches, I can foresee that you won't care
about the generic arm64 cpuidle driver either, or more precisely the
separation between
On Tue, May 19 2015 at 14:13 -0600, Andy Gross wrote:
On Mon, May 18, 2015 at 09:03:02AM -0600, Lina Iyer wrote:
On Sat, May 16 2015 at 03:03 -0600, Ohad Ben-Cohen wrote:
On Mon, May 11, 2015 at 5:46 PM, Lina Iyer lina.i...@linaro.org wrote:
On Sat, May 09 2015 at 03:25 -0600, Ohad Ben-Cohen
to the hwspinlock to ensure
locking correctness.
Drivers may use hwspin_trylock_raw() and hwspin_unlock_raw() api to lock
and unlock a hwlock with raw capability.
Cc: Jeffrey Hugo jh...@codeaurora.org
Cc: Ohad Ben-Cohen o...@wizery.com
Cc: Andy Gross agr...@codeaurora.org
Signed-off-by: Lina Iyer lina.i
capable can be
locked/unlocked through the _raw api
- QCOM patch for making lock #7 raw capable added.
- Add documentation
Thanks,
Lina
[1]. https://patches.linaro.org/47895/
Lina Iyer (2):
hwspinlock: Introduce raw capability for hwspinlocks
hwspinlock: qcom: Lock #7 is special lock, uses
bjorn.anders...@sonymobile.com
Cc: Andy Gross agr...@codeaurora.org
Signed-off-by: Lina Iyer lina.i...@linaro.org
---
drivers/hwspinlock/qcom_hwspinlock.c | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/hwspinlock/qcom_hwspinlock.c
b/drivers/hwspinlock
On Mon, Jun 01 2015 at 13:13 -0600, Lina Iyer wrote:
On Mon, Jun 01 2015 at 13:04 -0600, Kumar Gala wrote:
On Jun 1, 2015, at 1:35 PM, Arnd Bergmann a...@arndb.de wrote:
On Friday 29 May 2015 14:42:01 Arnd Bergmann wrote:
On Thursday 28 May 2015 10:55:39 Kumar Gala wrote:
Qualcomm ARM
Hilman on next-20150601
where the ifc6410 fails to boot a THUMB2 kernel because the
platform's firmware always enters the kernel in ARM mode from
deep idle states.
Reported-by: Kevin Hilman khil...@linaro.org
Cc: Ard Biesheuvel ard.biesheu...@linaro.org
Cc: Lina Iyer lina.i...@linaro.org
Signed-off
Hi Ohad,
Any comments?
Thanks,
Lina
On Tue, Jun 09 2015 at 10:23 -0600, Lina Iyer wrote:
This patch follows the discussion based on the first RFC series posted on the
mailing list [1]. The discussion resulted in a couple of directives for
hwspinlocks that do not want the framework imposing
On Wed, Jun 10 2015 at 11:33 -0600, Bjorn Andersson wrote:
On Tue, Jun 9, 2015 at 9:23 AM, Lina Iyer lina.i...@linaro.org wrote:
Hwspinlocks are widely used between processors in an SoC, and also
between elevation levels within in the same processor. QCOM SoC's use
hwspinlock to serialize
On Mon, Jun 01 2015 at 13:04 -0600, Kumar Gala wrote:
On Jun 1, 2015, at 1:35 PM, Arnd Bergmann a...@arndb.de wrote:
On Friday 29 May 2015 14:42:01 Arnd Bergmann wrote:
On Thursday 28 May 2015 10:55:39 Kumar Gala wrote:
Qualcomm ARM Based SoC Updates for v4.2-1
* Added Subsystem Power
On Sat, Jun 27 2015 at 05:25 -0600, Ohad Ben-Cohen wrote:
Hi Lina,
On Sat, Jun 27, 2015 at 6:05 AM, Lina Iyer lina.i...@linaro.org wrote:
Hi Ohad,
Any comments?
Sorry, I was under the impression the discussion with Bjorn is still open.
I am of the opinion that the platform driver
On Sat, May 23 2015 at 01:36 -0600, Ohad Ben-Cohen wrote:
Hi Lina,
On Mon, May 18, 2015 at 6:03 PM, Lina Iyer lina.i...@linaro.org wrote:
The lock in question is used differently than traditional locks across
processors. This lock helps synchronizes context transition from
non-secure to secure
On Sat, Jul 18 2015 at 05:31 -0600, Ohad Ben-Cohen wrote:
Hi Lina,
On Thu, Jul 2, 2015 at 11:30 PM, Lina Iyer lina.i...@linaro.org wrote:
You are right, RAW capability is not lock specific. But we dont want to
impose this on every lock in the bank either.
I'm not sure I'm following your
On Fri, Aug 14 2015 at 04:52 -0600, Ohad Ben-Cohen wrote:
On Thu, Aug 13, 2015 at 6:25 PM, Andy Gross agr...@codeaurora.org wrote:
The issue in hardwiring this into the driver itself means forfeiting
extensibility. So on one side (w/ raw support), we get the ability to deal with
the lock
On Thu, Aug 13 2015 at 00:34 -0600, Ohad Ben-Cohen wrote:
On Wed, Jul 29, 2015 at 12:51 AM, Lina Iyer lina.i...@linaro.org wrote:
Let's not make this more complicated than needed, so please add the
hwcaps member to hwspinlock_device instead of to hwspinlock struct. We
could always change
On Wed, Nov 11 2015 at 02:10 -0700, Zhaoyang Huang wrote:
On 6 October 2015 at 22:27, Marc Titinger wrote:
From: Marc Titinger
Cpuidle now handles c-states and power-states differently. c-states do not
decrement
the reference count for the
Hi Marc,
Thanks for rebasing on top of my latest series.
On Tue, Oct 06 2015 at 08:27 -0600, Marc Titinger wrote:
Devices may register an intermediate retention state into the domain upon
I may agree with the usability of dynamic adding a state to the domain,
but I dont see why a device
On Tue, Oct 06 2015 at 08:27 -0600, Marc Titinger wrote:
This patch allows cluster-level C-states to being soaked in as generic
domain power states, in order for the domain governor to chose the most
efficient power state compatible with the device constraints. Similarly,
devices can register
Hi Marc,
I am trying to apply this on top of Axel's patches on linux-next (after
fixing issues I saw with his v9), and running to issues applying your
patches. Could you rebase on top of his v10 (he said he would send to
the ML soon) ?
Thanks,
Lina
On Tue, Oct 06 2015 at 08:27 -0600, Marc
upport for multiple domains will be
added in subsequent patches.
Suggested-by: Lina Iyer <lina.i...@linaro.org>
Signed-off-by: Axel Haslam <ahaslam+rene...@baylibre.com>
---
arch/arm/mach-exynos/pm_domains.c | 2 +-
arch/arm/mach-imx/gpc.c | 2 +-
arch/arm/mach-s3c64xx/pm
On Fri, Oct 09 2015 at 03:39 -0600, Marc Titinger wrote:
On 08/10/2015 18:11, Lina Iyer wrote:
Hi Marc,
Thanks for rebasing on top of my latest series.
On Tue, Oct 06 2015 at 08:27 -0600, Marc Titinger wrote:
Devices may register an intermediate retention state into the domain upon
I may
On Thu, Jul 09 2015 at 03:28 -0600, Lorenzo Pieralisi wrote:
On Thu, Jul 09, 2015 at 09:43:04AM +0100, Jisheng Zhang wrote:
On Thu, 9 Jul 2015 16:31:24 +0800
Jisheng Zhang jszh...@marvell.com wrote:
As for the suspend member function, the to-be-suspended cpu is always
the calling cpu itself,
not be
necessary either, because we can get the node via. of_get_cpu_node().
Signed-off-by: Jisheng Zhang jszh...@marvell.com
Tested-by: Lina Iyer lina.i...@linaro.org
---
arch/arm/include/asm/cpuidle.h | 6 +++---
arch/arm/kernel/cpuidle.c | 8
drivers/soc/qcom/spm.c | 17
Enable QCOM_SCM for QCOM power management driver
Signed-off-by: Lina Iyer lina.i...@linaro.org
---
drivers/soc/qcom/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index 5eea374..e9a2c19 100644
--- a/drivers/soc/qcom/Kconfig
+++ b
On Fri, Jul 10 2015 at 14:29 -0600, Dave Gerlach wrote:
On 07/10/2015 02:36 PM, Stephen Boyd wrote:
On 07/10/2015 12:31 PM, Dave Gerlach wrote:
Hello,
I am seeing the following error when building v4.2-rc1 for arm with
multi_v7_defconfig with CONFIG_SMP=n:
LINKvmlinux
LD vmlinux.o
cpu_cluster_pm_exit() must be sent after cpu_cluster_pm_enter() has been
sent for the cluster and before any cpu_pm_exit() notifications are sent
for any CPU.
Cc: Nicolas Pitre <nicolas.pi...@linaro.org>
Acked-by: Kevin Hilman <khil...@linaro.org>
Signed-off-by: Lina Iyer <lina.
On Fri, Sep 25 2015 at 07:04 -0600, Marc Titinger wrote:
From: Marc Titinger
fake path to start testing, eventually move this out of /arch/.
incidently enable PM_GENERIC_DOMAINS for VExpress.
In fact, this could be moved out of ARM. My last series moved it to
On Fri, Dec 18 2015 at 09:15 -0700, Georgi Djakov wrote:
The SAW2 (Subsystem Power Manager and Adaptive Voltage Scaling Wrapper)
is part of the SPM subsystem. It is a hardware block found on some of the
Qualcomm chipsets, which regulates the power to the CPU cores. Add some
basic support for it,
On Wed, Feb 10 2016 at 03:13 -0700, Mark Brown wrote:
On Tue, Feb 09, 2016 at 03:21:54PM -0700, Lina Iyer wrote:
On Tue, Feb 09 2016 at 06:13 -0700, Georgi Djakov wrote:
Please delete unneeded context from mails when replying. Doing this
makes it much easier to find your reply in the message
On Tue, Feb 09 2016 at 06:13 -0700, Georgi Djakov wrote:
The SAW (Subsystem Power Manager and Adaptive Voltage Scaling Wrapper)
is part of the SPM subsystem. It is a hardware block in the Qualcomm
chipsets that regulates the power to the CPU cores on platform such as
apq8064, msm8974, apq8084
Hi Bjorn,
On Thu, Sep 01 2016 at 16:28 -0600, Bjorn Andersson wrote:
This series splits the virtio rpmsg bus driver into a rpmsg bus and a virtio
backend/wireformat.
As we discussed the Qualcomm SMD implementation a couple of years back people
suggested that I should make it "a rpmsg
On Mon, Sep 12 2016 at 10:52 -0600, Lina Iyer wrote:
Hi Bjorn,
On Thu, Sep 01 2016 at 16:28 -0600, Bjorn Andersson wrote:
This series splits the virtio rpmsg bus driver into a rpmsg bus and a virtio
backend/wireformat.
As we discussed the Qualcomm SMD implementation a couple of years back
On Tue, Oct 25 2016 at 17:51 -0600, Rafael J. Wysocki wrote:
On Tuesday, October 25, 2016 10:47:29 AM Stephen Rothwell wrote:
Hi Rafael,
Today's linux-next merge of the pm tree got a conflict in:
arch/arm/mach-imx/gpc.c
between commits:
eef0b282bb58 ("ARM: imx: gpc: Initialize all power
On Fri, May 11 2018 at 14:14 -0600, Doug Anderson wrote:
Hi,
On Fri, May 11, 2018 at 8:06 AM, Lina Iyer <il...@codeaurora.org> wrote:
As I've said I haven't reviewed RPMh in any amount of detail and so
perhaps I don't understand something.
OK, I dug a little more and coded up som
Hi Doug,
Will explain only the key points now.
On Fri, May 11 2018 at 14:19 -0600, Doug Anderson wrote:
Hi,
On Wed, May 9, 2018 at 10:01 AM, Lina Iyer <il...@codeaurora.org> wrote:
/**
@@ -77,12 +82,14 @@ struct rpmh_request {
* @cache: the list of cached requests
* @lock: synch
Hi Daniel,
On Tue, May 08 2018 at 20:04 -0600, Daniel Lezcano wrote:
On Mon, May 07, 2018 at 11:54:08AM -0600, Lina Iyer wrote:
From: Ram Chandrasekar <rkumb...@codeaurora.org>
From: Ram Chandrasekar <rkumb...@codeaurora.org>
Step wise governor increases the mitigatio
at the time of writing. The TCS are triggered by the firmware
after the last of the CPUs has executed its WFI. Since these requests
may come in different batches of requests, it is the job of this
controller driver to find and arrange the requests into the available
TCSes.
Signed-off-by: Lina Iyer
.
rpmh_write_batch() is a blocking call that can be used to send multiple
RPMH command sets. Each RPMH command set is set asynchronously and the
API blocks until all the command sets are complete and receive their
tx_done callbacks.
Signed-off-by: Lina Iyer <il...@codeaurora.org>
---
Changes
activity and may be called from the
system PM drivers when the system is entering suspend or deeper sleep
modes during cpuidle.
Also allow invalidating the cached requests, so they may be re-populated
again.
Signed-off-by: Lina Iyer <il...@codeaurora.org>
Reviewed-by: Evan Green <evgr...@chr
that the wake TCS
is being repurposed to send active request, hence the sleep and wake
TCSes be invalidated before the active request is sent.
Signed-off-by: Lina Iyer <il...@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <m...@chromium.org>
---
drivers/soc/qcom/rpmh-rsc.c | 18 ++
Hi Andy, David,
These patches have been reviewed by our peers and have recieved no
further comments in the past few weeks. Would you consider merging this
in your trees?
Thanks,
Lina
On Tue, Apr 10 2018 at 11:57 -0600, Lina Iyer wrote:
Changes since v7:
- Add reviewed-by tags
Log sent RPMH requests and interrupt responses in FTRACE.
Cc: Steven Rostedt <rost...@goodmis.org>
Signed-off-by: Lina Iyer <il...@codeaurora.org>
---
Changes in v7:
- varible name changes and white space
Changes in v6:
- struct tcs_response was removed. Fix in t
r each type of requests. Active mode TCSes (AMC) are used to
send requests immediately to the resource, while control TCS are used to
provide specific information to the controller. Sleep and Wake TCS send
sleep and wake requests, after and before the system halt respectively.
Signed-off-by: Lin
in the context of the controller's thread and frees the
allocated memory. This API allows RPMH requests from atomic contexts as
well.
Signed-off-by: Lina Iyer <il...@codeaurora.org>
---
Changes in v6:
- replace rpmh_client with device *
---
drivers/soc/qcom/rpmh.
Add device binding documentation for Qualcomm Technology Inc's RPMH RSC
driver. The driver is used for communicating resource state requests for
shared resources.
Cc: devicet...@vger.kernel.org
Signed-off-by: Lina Iyer <il...@codeaurora.org>
Reviewed-by: Rob Herring <r...@kernel.org>
Allow sleep and wake commands to be cleared from the respective TCSes,
so that they can be re-populated.
Signed-off-by: Lina Iyer <il...@codeaurora.org>
---
Changes in v7:
- Move bitmap_zero() outside the loop
Changes in v6:
- remove unnecessary locks around __tcs_inva
be used to send
active state requests.
Signed-off-by: Lina Iyer <il...@codeaurora.org>
---
Changes in v7:
- Optimization and locking fixes
Changes in v6:
- replace rpmh_client with device
- inline wait_for_tx_done()
Changes in v4:
- use const struct tcs_cmd
g/lkml/2018/3/2/801
v4: https://lkml.org/lkml/2018/3/9/979
v5: https://lkml.org/lkml/2018/4/5/480
v6: https://lkml.org/lkml/2018/4/19/914
v7: https://lkml.org/lkml/2018/5/2/779
Lina Iyer (10):
drivers: qcom: rpmh-rsc: add RPMH controller for QCOM SoCs
dt-bindings: introduce RPMH RSC bi
On Wed, Apr 25 2018 at 15:41 -0600, Matthias Kaehlcke wrote:
On Thu, Apr 19, 2018 at 04:16:30PM -0600, Lina Iyer wrote:
Sleep and wake requests are sent when the application processor
subsystem of the SoC is entering deep sleep states like in suspend.
These requests help lower the system power
On Fri, Apr 27 2018 at 12:40 -0600, Matthias Kaehlcke wrote:
On Fri, Apr 27, 2018 at 11:39:43AM -0600, Lina Iyer wrote:
On Wed, Apr 25 2018 at 15:41 -0600, Matthias Kaehlcke wrote:
> On Thu, Apr 19, 2018 at 04:16:30PM -0600, Lina Iyer wrote:
> > Sleep and wake requests are
On Wed, Apr 25 2018 at 17:41 -0600, Matthias Kaehlcke wrote:
On Thu, Apr 19, 2018 at 04:16:34PM -0600, Lina Iyer wrote:
Platform drivers need make a lot of resource state requests at the same
time, say, at the start or end of an usecase. It can be quite
inefficient to send each request
On Thu, Apr 26 2018 at 12:05 -0600, Matthias Kaehlcke wrote:
Hi Lina,
On Thu, Apr 19, 2018 at 04:16:29PM -0600, Lina Iyer wrote:
Sending RPMH requests and waiting for response from the controller
through a callback is common functionality across all platform drivers.
To simplify drivers, add
On Wed, Apr 25 2018 at 16:11 -0600, Matthias Kaehlcke wrote:
On Thu, Apr 19, 2018 at 04:16:31PM -0600, Lina Iyer wrote:
Allow sleep and wake commands to be cleared from the respective TCSes,
so that they can be re-populated.
Signed-off-by: Lina Iyer <il...@codeaurora.org>
---
Changes
On Fri, Apr 27 2018 at 14:06 -0600, Matthias Kaehlcke wrote:
On Fri, Apr 27, 2018 at 01:45:59PM -0600, Lina Iyer wrote:
On Fri, Apr 27 2018 at 12:40 -0600, Matthias Kaehlcke wrote:
> On Fri, Apr 27, 2018 at 11:39:43AM -0600, Lina Iyer wrote:
> > On Wed, Apr 25 2018 at 15:41 -0600,
On Wed, May 09 2018 at 17:25 -0600, Matthias Kaehlcke wrote:
Hi Lina,
On Wed, May 09, 2018 at 11:01:54AM -0600, Lina Iyer wrote:
Sleep and wake requests are sent when the application processor
subsystem of the SoC is entering deep sleep states like in suspend.
These requests help lower
On Wed, May 09 2018 at 16:03 -0600, Matthias Kaehlcke wrote:
On Wed, May 09, 2018 at 11:01:58AM -0600, Lina Iyer wrote:
Platform drivers need make a lot of resource state requests at the same
time, say, at the start or end of an usecase. It can be quite
inefficient to send each request
On Wed, May 09 2018 at 11:49 -0600, Steven Rostedt wrote:
On Wed, 9 May 2018 11:01:52 -0600
Lina Iyer <il...@codeaurora.org> wrote:
Log sent RPMH requests and interrupt responses in FTRACE.
Has this changed since the last time I reviewed it? If not, please add
the: Reviewed-by:
On Wed, May 09 2018 at 15:30 -0600, Doug Anderson wrote:
Lina
On Wed, May 9, 2018 at 9:42 AM, Lina Iyer <il...@codeaurora.org> wrote:
Hi Andy, David,
These patches have been reviewed by our peers and have recieved no
further comments in the past few weeks. Would you consider m
Hi Doug,
On Thu, May 10 2018 at 16:37 -0600, Doug Anderson wrote:
Hi,
On Tue, May 8, 2018 at 9:05 AM, <il...@codeaurora.org> wrote:
On 2018-05-03 14:26, Doug Anderson wrote:
Hi Doug,
Hi,
On Wed, May 2, 2018 at 12:37 PM, Lina Iyer <il...@codeaurora.org> wrote:
+static struc
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