On Thu, 26 Nov 2020 00:55:54 +0530, Vidya Sagar wrote:
> PCIe controller in Tegra194 requires the "dbi" region base address to be
> programmed in one of the application logic registers to enable CPU access
> to the "dbi" region. But, commit a0fd361db8e5 ("PCI: dwc: Move "dbi",
> "dbi2", and "addr_s
On Thu, 26 Nov 2020 00:52:34 +0530, Vidya Sagar wrote:
> commit a0fd361db8e5 ("PCI: dwc: Move "dbi", "dbi2", and "addr_space"
> resource setup into common code") moved the code that sets up dbi_base
> to DWC common code thereby creating a requirement to not access the "dbi"
> region before calling
On Thu, 1 Oct 2020 11:30:51 +0530, Srinath Mannam wrote:
> This patch series contains fixes and improvements to pcie iproc driver.
>
> This patch set is based on Linux-5.9.0-rc2.
>
> Changes from v2:
> - Addressed Bjorn's review comments
> - Corrected subject line and commit message of Pat
On Thu, Oct 01, 2020 at 11:30:51AM +0530, Srinath Mannam wrote:
> This patch series contains fixes and improvements to pcie iproc driver.
>
> This patch set is based on Linux-5.9.0-rc2.
>
> Changes from v2:
> - Addressed Bjorn's review comments
> - Corrected subject line and commit message
On Mon, Nov 09, 2020 at 10:49:35PM +0530, Vidya Sagar wrote:
> Currently the driver checks for error value of different APIs during the
> uninitialization sequence. It just returns from there if there is any error
> observed for one of those calls. Comparatively it is better to continue the
> unini
On Mon, Nov 30, 2020 at 12:17:41AM +0100, Pali Rohár wrote:
> On Sunday 11 October 2020 19:21:49 Pali Rohár wrote:
> > On Thursday 24 September 2020 17:22:32 Pali Rohár wrote:
> > > On Thursday 24 September 2020 10:11:06 Bjorn Helgaas wrote:
> > > > On Thu, Sep 24, 2020 at 10:46:18AM +0200, Pali Ro
On Thu, Nov 26, 2020 at 03:54:14PM +, David Brazdil wrote:
> Forward the following PSCI SMCs issued by host to EL3 as they do not
> require the hypervisor's intervention. This assumes that EL3 correctly
> implements the PSCI specification.
>
> Only function IDs implemented in Linux are include
On Thu, Nov 26, 2020 at 03:54:00PM +, David Brazdil wrote:
> Function IDs used by PSCI are configurable for v0.1 via DT/APCI. If the
Side note: in ACPI we don't support versions < 0.2, for commit log
accuracy.
Other than that I agree with Mark's change request.
Thanks,
Lorenzo
> host is usi
gister and invokes the interrupt
> > with PME/AER vIRQ numbers.
> >
> > These vIRQ numbers is obtained from portdrv in uniphier_add_pcie_port()
> > function.
> >
> > Cc: Marc Zyngier
> > Cc: Jingoo Han
> > Cc: Gusta
On Fri, 13 Nov 2020 18:01:34 +0100, Marek Szyprowski wrote:
> This patchset is a resurrection of the DW PCIe support for the Exynos5433
> SoCs posted long time ago here: https://lkml.org/lkml/2016/12/26/6 and
> later here: https://lkml.org/lkml/2017/12/21/296 .
>
> In meantime the support for the
On Fri, 6 Nov 2020 20:41:05 +0530, Kishon Vijay Abraham I wrote:
> Make "cdns,max-outbound-regions" optional DT property in all the
> platforms using Cadence PCIe core.
>
> Kishon Vijay Abraham I (2):
> dt-bindings: PCI: Make "cdns,max-outbound-regions" optional property
> PCI: cadence: Do not
On Mon, 2 Nov 2020 15:57:12 -0500, Jim Quinlan wrote:
> The variable 'tmp' is used multiple times in the brcm_pcie_setup()
> function. One such usage did not initialize 'tmp' to the current value of
> the target register. By luck the mistake does not currently affect
> behavior; regardless 'tmp'
On Fri, 23 Oct 2020 17:20:08 +0100, Lad Prabhakar wrote:
> Drop unused members dev and base from struct rcar_pcie_host.
Applied to pci/rcar, thanks!
[1/1] PCI: rcar: Drop unused members from struct rcar_pcie_host
https://git.kernel.org/lpieralisi/pci/c/6e8e137abe
Thanks,
Lorenzo
On Thu, Nov 19, 2020 at 06:03:47PM +, Catalin Marinas wrote:
> On Thu, Nov 19, 2020 at 06:01:20PM +0000, Lorenzo Pieralisi wrote:
> > [+Catalin - I hope it can go via arm64 tree, trivial doc fixup]
>
> Or Will if you want it in 5.10, otherwise I can pick it up for 5.11.
Tha
> description in 'iort_dma_setup'
> drivers/acpi/arm64/iort.c:1534: warning: Function parameter or member 'ops'
> not described in 'iort_add_platform_device'
>
> Signed-off-by: Shiju Jose
> ---
> drivers/acpi/arm64/iort.c | 8 +---
>
On Sun, Sep 27, 2020 at 01:42:57PM +0100, Lad Prabhakar wrote:
> Add PCIe support for the RZ/G2H (a.k.a. R8A774E1).
>
> Signed-off-by: Lad Prabhakar
> Reviewed-by: Marian-Cristian Rotariu
>
> Acked-by: Rob Herring
> Reviewed-by: Wolfram Sang
> Reviewed-by: Geert Uytterhoeven
> Reviewed-by: Y
On Tue, Sep 22, 2020 at 11:30:30AM -0600, Rob Herring wrote:
> On Mon, Sep 21, 2020 at 1:50 AM Neil Armstrong
> wrote:
> >
> > When establish link timeouts, probe fails but the error is unrelated since
> > the PCIe controller has been probed succesfully.
> >
> > Align with most of the other dw-pc
On Sun, 6 Sep 2020 20:51:27 +0100, Alex Dewar wrote:
> Currently the Keystone driver can only be compile-tested on ARM, but
> this restriction seems unnecessary. Get rid of it to increase test
> coverage.
>
> Build-tested with allyesconfig on x86, ppc, mips and riscv.
Applied to pci/keystone, tha
On Wed, Nov 18, 2020 at 10:05:29PM +0800, Chen Baozi wrote:
> Hi Lorenzo,
>
> > On Nov 18, 2020, at 5:51 PM, Lorenzo Pieralisi
> > wrote:
> >
> > On Tue, Nov 17, 2020 at 09:42:14PM +0800, Chen Baozi wrote:
> >> Some PCIe designs require software to do
On Thu, Jun 11, 2020 at 07:32:46PM +0800, Peng Fan wrote:
> We should free "test" before the return of run_test.
>
> Signed-off-by: Peng Fan
> ---
> tools/pci/pcitest.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/tools/pci/pcitest.c b/tools/pci/pcitest.c
> index 0a1344c..7c20332
On Wed, 18 Nov 2020 20:16:24 +0530, Vidya Sagar wrote:
> This patch series adds support for configuring the DesignWare IP's ATU
> region for prefetchable memory translations.
> It first starts by flagging a warning if the size of non-prefetchable
> aperture goes beyond 32-bit as PCIe spec doesn't a
On Tue, Nov 17, 2020 at 11:04:57PM +0530, Vidya Sagar wrote:
[...]
> > IIUC we should:
> >
> > (1) apply
> > https://patchwork.kernel.org/project/linux-pci/patch/20201026181652.418729-1-r...@kernel.org
> > (2) apply [1,2] from this series
> >
> > For (2), are they rebased against v5.10-rc3 wit
On Tue, Nov 17, 2020 at 09:42:14PM +0800, Chen Baozi wrote:
> Some PCIe designs require software to do extra acknowledgements for
> legacy INTx interrupts. If the driver is written only for device tree,
> things are simple. In that case, a new driver can be written under
> driver/pci/controller/ wi
On Tue, Nov 17, 2020 at 10:08:35AM +0530, Vidya Sagar wrote:
> Hi Lorenzo & Bjorn,
> Sorry to bother you.
> Could you please take a look at the patches-1 & 2 from this series?
IIUC we should:
(1) apply
https://patchwork.kernel.org/project/linux-pci/patch/20201026181652.418729-1-r...@kernel.org
(
[+Jonathan]
On Mon, Nov 09, 2020 at 08:27:09PM +0800, Baolin Wang wrote:
[...]
> I did some investigation for this issue. I am sorry I made some
> misleading description in the commit message. The issue is, when we
> want to disable the NUMA from firmware, we usually just remove the SRAT
> table
On Thu, Nov 12, 2020 at 11:20:08AM +, Marc Zyngier wrote:
> On 2020-11-11 16:28, Lorenzo Pieralisi wrote:
> > GIC v4.1 introduced changes to the GIC CPU interface; systems that
> > integrate CPUs that do not support GIC v4.1 features (as reported in
> > the
> > I
On Thu, Nov 12, 2020 at 09:36:10AM +, Marc Zyngier wrote:
> Hi Lorenzo,
>
> On 2020-11-11 16:28, Lorenzo Pieralisi wrote:
> > GIC CPU interfaces versions predating GIC v4.1 were not built to
> > accommodate vINTID within the vSGI range; as reported in the GIC
> > s
results in CONSTRAINED UNPREDICTABLE behaviour at architectural
level.
Add a cpufeature and related capability to detect GIC v4.1 CPUIF
features so that the GIC driver can probe it to detect GIC CPUIF
hardware configuration and take action accordingly.
Signed-off-by: Lorenzo Pieralisi
Cc: Will Deacon
GIC CPUIF version through the arm64 capabilities
infrastructure and disable vSGIs if a CPUIF version < 4.1 is
detected to prevent using vSGIs on systems where they may
misbehave.
Signed-off-by: Lorenzo Pieralisi
Cc: Marc Zyngier
---
drivers/irqchip/irq-gic-v3-its.c | 20 +++-
1
not changed from GIC v4.0 to GIC v4.1.
Cc: Will Deacon
Cc: Catalin Marinas
Cc: Marc Zyngier
Lorenzo Pieralisi (2):
arm64: cpufeature: Add GIC CPUIF v4.1 detection
irqchip/gic-v3-its: Disable vSGI upon (CPUIF < v4.1) detection
arch/arm64/include/asm/cpucaps.h | 3 ++-
arch/arm64/ker
c b/drivers/acpi/scan.c
> index a896e5e87c93..bc6a79e33220 100644
> --- a/drivers/acpi/scan.c
> +++ b/drivers/acpi/scan.c
Acked-by: Lorenzo Pieralisi
> @@ -1453,7 +1453,7 @@ int acpi_dma_get_range(struct device *dev, u64
> *dma_addr, u64 *offset,
> }
>
> /**
> - * acp
e_sizes_init()
>
> arch/arm64/mm/init.c | 3 ++-
> drivers/acpi/arm64/iort.c | 52 +++
> include/linux/acpi_iort.h | 4 +++
> 3 files changed, 58 insertions(+), 1 deletion(-)
Acked-by: Lorenzo Pieralisi
> diff --git a/arch/arm64/m
Jingoo, Gustavo,
please review this patch, thanks.
Lorenzo
On Wed, Oct 21, 2020 at 01:29:31AM +0530, Vidya Sagar wrote:
> DWC sub-system currently doesn't differentiate between prefetchable and
> non-prefetchable memory aperture entries in the 'ranges' property and
> provides ATU mapping only fo
On Mon, Oct 05, 2020 at 05:43:51PM +0530, Vidya Sagar wrote:
> Use ATU region-3 and region-0 to setup mapping for prefetchable and
> non-prefetchable memory regions respectively only if their respective CPU
> and bus addresses are different.
>
The commit subject and log must be rewritten. You sho
On Tue, Oct 20, 2020 at 07:03:59PM +0530, Vidya Sagar wrote:
>
>
> On 10/20/2020 6:50 PM, Lorenzo Pieralisi wrote:
> > External email: Use caution opening links or attachments
> >
> >
> > On Mon, Oct 19, 2020 at 11:21:54AM +0530, Vidya Sagar wrote:
> >
On Mon, Oct 19, 2020 at 11:21:54AM +0530, Vidya Sagar wrote:
> Hi Lorenzo, Rob, Gustavo,
> Could you please review this change?
Next cycle - we are in the middle of the merge window and I am not
queueing any more patches.
Thanks,
Lorenzo
> Thanks,
> Vidya Sagar
>
> On 10/5/2020 5:43 PM, Vidya S
On Tue, Oct 20, 2020 at 01:45:45PM +0530, Kishon Vijay Abraham I wrote:
> Hi,
>
> On 05/10/20 11:27 am, Kishon Vijay Abraham I wrote:
> > Hi Jon Mason, Allen Hubbe, Dave Jiang,
> >
> > On 30/09/20 9:05 pm, Kishon Vijay Abraham I wrote:
> >> This series is about implementing SW defined Non-Transpa
On Thu, Oct 15, 2020 at 05:47:38PM -0500, Bjorn Helgaas wrote:
> On Wed, Sep 16, 2020 at 01:41:30PM +0800, Zhiqiang Hou wrote:
> > From: Hou Zhiqiang
> >
> > On NXP Layerscape platforms, it results in SError in the
> > enumeration of the PCIe controller, which is not connecting
> > with an Endpoi
On Tue, Oct 20, 2020 at 02:13:13AM +, Z.q. Hou wrote:
[...]
> > > For NXP Layerscape platforms (the ls1028a and ls2088a are also NXP
> > Layerscape platform), as the error response to AXI/AHB was enabled, it will
> > get UR error and trigger SError on AXI bus when it accesses a non-existent
>
On Fri, Sep 18, 2020 at 09:27:40AM -0600, Rob Herring wrote:
[...]
> > > Maybe a link down just never happens once up, but if so, then we only need
> > > to check it once and fail probe.
> >
> > Many customers connect the FPGA Endpoint, which may establish PCIe link
> > after the PCIe enumeration
On Tue, Oct 20, 2020 at 02:13:13AM +, Z.q. Hou wrote:
[...]
> > > For NXP Layerscape platforms (the ls1028a and ls2088a are also NXP
> > Layerscape platform), as the error response to AXI/AHB was enabled, it will
> > get UR error and trigger SError on AXI bus when it accesses a non-existent
>
On Thu, Oct 15, 2020 at 05:47:38PM -0500, Bjorn Helgaas wrote:
> On Wed, Sep 16, 2020 at 01:41:30PM +0800, Zhiqiang Hou wrote:
> > From: Hou Zhiqiang
> >
> > On NXP Layerscape platforms, it results in SError in the
> > enumeration of the PCIe controller, which is not connecting
> > with an Endpoi
On Mon, Oct 12, 2020 at 04:41:11AM +, Z.q. Hou wrote:
[...]
> > >> Yeah, I don't see any registers in the DRA7x PCIe wrapper for
> > >> disabling error forwarding.
> > >
> > > It's a DWC port logic register AFAICT, but perhaps not present in all
> > versions.
> >
> > Okay. I see there's a re
On Thu, Oct 15, 2020 at 05:47:38PM -0500, Bjorn Helgaas wrote:
> On Wed, Sep 16, 2020 at 01:41:30PM +0800, Zhiqiang Hou wrote:
> > From: Hou Zhiqiang
> >
> > On NXP Layerscape platforms, it results in SError in the
> > enumeration of the PCIe controller, which is not connecting
> > with an Endpoi
On Wed, Oct 14, 2020 at 09:12:09PM +0200, Nicolas Saenz Julienne wrote:
[...]
> +unsigned int __init acpi_iort_get_zone_dma_size(void)
> +{
> + struct acpi_table_iort *iort;
> + struct acpi_iort_node *node, *end;
> + acpi_status status;
> + u8 limit = 32;
> + int i;
> +
> +
On Wed, Sep 16, 2020 at 01:41:30PM +0800, Zhiqiang Hou wrote:
> From: Hou Zhiqiang
>
> On NXP Layerscape platforms, it results in SError in the
> enumeration of the PCIe controller, which is not connecting
> with an Endpoint device. And it doesn't make sense to
> enumerate the Endpoints when the
On Wed, Sep 16, 2020 at 01:41:30PM +0800, Zhiqiang Hou wrote:
> From: Hou Zhiqiang
>
> On NXP Layerscape platforms, it results in SError in the
> enumeration of the PCIe controller, which is not connecting
> with an Endpoint device. And it doesn't make sense to
> enumerate the Endpoints when the
On Fri, Oct 09, 2020 at 11:13:59AM +0200, Ard Biesheuvel wrote:
> On Fri, 9 Oct 2020 at 10:36, Nicolas Saenz Julienne
> wrote:
> >
> > On Fri, 2020-10-09 at 09:37 +0200, Ard Biesheuvel wrote:
> > > On Fri, 9 Oct 2020 at 09:11, Christoph Hellwig wrote:
> > > > On Thu, Oct 08, 2020 at 12:05:25PM +0
On Fri, Oct 09, 2020 at 03:53:11PM +0800, Jisheng Zhang wrote:
> Fix two MSI issues. One to skip PCIE_MSI_INTR0* programming if MSI is
> disabled, another to use an address in the driver data for MSI address,
> to fix the MSI page leakage during suspend/resume.
>
> Since v6:
> - Keep the IS_ENAB
On Thu, Oct 01, 2020 at 07:02:04PM +0530, Kishon Vijay Abraham I wrote:
[...]
> >> Yeah, I don't see any registers in the DRA7x PCIe wrapper for disabling
> >> error forwarding.
> >
> > It's a DWC port logic register AFAICT, but perhaps not present in all
> > versions.
>
> Okay. I see there's
On Wed, Sep 30, 2020 at 09:12:05AM +0800, Jisheng Zhang wrote:
> Fix two MSI issues. One to skip PCIE_MSI_INTR0* programming if MSI is
> disabled, another to use an address in the driver data for MSI address,
> to fix the MSI page leakage during suspend/resume.
>
> Since v4:
> - fix pci-dra7xx.c
On Wed, Sep 30, 2020 at 02:36:03PM +0900, Kunihiko Hayashi wrote:
> This moves iATU register mapping in the Keystone driver to common
> framework. And this adds "iatu" property description to the dt-bindings
> for UniPhier PCIe host and endpoint controller.
>
> This series is split from the previo
On Fri, Oct 02, 2020 at 11:53:27AM -0700, Kevin Hilman wrote:
> Hi Lorenzo,
>
> Lorenzo Pieralisi writes:
>
> > On Fri, Sep 18, 2020 at 11:12:51AM -0700, Kevin Hilman wrote:
> >> Enable pci-meson to build as a module whenever ARCH_MESON is enabled.
> >>
&
[+Christoph]
On Tue, Sep 29, 2020 at 12:18:49PM -0600, Alex Williamson wrote:
> On Tue, 29 Sep 2020 09:18:22 +0200
> Auger Eric wrote:
>
> > Hi all,
> >
> > [also correcting some outdated email addresses + adding Lorenzo in cc]
> >
> > On 9/29/20 12:42 AM, Alex Williamson wrote:
> > > On Mon,
On Fri, Oct 02, 2020 at 05:07:01PM +0200, Pali Rohár wrote:
[...]
> > I will apply the stable tag and dependency, it should be fine.
>
> Ok! I thought that according to stable-kernel-rules.html that dependent
> commit could be added after stable email address separated with # char.
> At least th
On Fri, Oct 02, 2020 at 04:52:37PM +0200, Pali Rohár wrote:
> On Friday 02 October 2020 15:38:51 Lorenzo Pieralisi wrote:
> > On Fri, Oct 02, 2020 at 04:26:16PM +0200, Pali Rohár wrote:
> > > On Friday 02 October 2020 14:37:13 Lorenzo Pieralisi wrote:
> > > > On W
On Tue, Sep 15, 2020 at 01:11:21PM -0700, David Miller wrote:
> From: Lorenzo Pieralisi
> Date: Tue, 15 Sep 2020 10:32:02 +0100
>
> > Move the ioremap/iounmap declaration before asm-generic/io.h is
> > included so that it is visible within it.
> >
> >
On Fri, Oct 02, 2020 at 04:26:16PM +0200, Pali Rohár wrote:
> On Friday 02 October 2020 14:37:13 Lorenzo Pieralisi wrote:
> > On Wed, Sep 02, 2020 at 04:43:42PM +0200, Pali Rohár wrote:
> > > This patch series fixes regression introduced in commit 366697018c9a
> > &g
On Wed, Sep 02, 2020 at 04:43:42PM +0200, Pali Rohár wrote:
> This patch series fixes regression introduced in commit 366697018c9a
> ("PCI: aardvark: Add PHY support") which caused aardvark driver
> initialization failure on EspressoBin board with factory version of
> Arm Trusted Firmware provided
On Mon, Sep 21, 2020 at 09:10:54PM +0800, Qinglang Miao wrote:
> Simplify the return expression.
>
> Signed-off-by: Qinglang Miao
> ---
> drivers/pci/controller/pci-loongson.c | 7 +--
> 1 file changed, 1 insertion(+), 6 deletions(-)
Applied to pci/loongson, thanks.
Lorenzo
> diff --git a
On Mon, Sep 21, 2020 at 09:10:53PM +0800, Qinglang Miao wrote:
> Simplify the return expression.
>
> Signed-off-by: Qinglang Miao
> ---
> drivers/pci/controller/cadence/pcie-cadence-host.c | 8 ++--
> 1 file changed, 2 insertions(+), 6 deletions(-)
Applied to pci/cadence, thanks.
Lorenzo
On Fri, Sep 18, 2020 at 11:08:29AM +0800, Liu Shixin wrote:
> module_bcma_driver() makes the code simpler by eliminating
> boilerplate code.
>
> Signed-off-by: Liu Shixin
> ---
> drivers/pci/controller/pcie-iproc-bcma.c | 13 +
> 1 file changed, 1 insertion(+), 12 deletions(-)
Appli
On Fri, Sep 18, 2020 at 11:08:29AM +0800, Liu Shixin wrote:
> module_bcma_driver() makes the code simpler by eliminating
> boilerplate code.
>
> Signed-off-by: Liu Shixin
> ---
> drivers/pci/controller/pcie-iproc-bcma.c | 13 +
> 1 file changed, 1 insertion(+), 12 deletions(-)
Appli
On Fri, Oct 02, 2020 at 01:51:58AM -0700, Dexuan Cui wrote:
> pci_restore_msi_state() directly writes the MSI/MSI-X related registers
> via MMIO. On a physical machine, this works perfectly; for a Linux VM
> running on a hypervisor, which typically enables IOMMU interrupt remapping,
> the hyperviso
On Thu, Oct 01, 2020 at 09:42:43AM +0200, Thomas Petazzoni wrote:
> Fixes the following build warning when CONFIG_OF is disabled:
>
> drivers/pci/controller/dwc/pcie-armada8k.c:344:34: warning:
> ‘armada8k_pcie_of_match’ defined but not used [-Wunused-const-variable=]
> 344 | static const struc
On Wed, Sep 30, 2020 at 12:38:04AM +, Dexuan Cui wrote:
> > From: Lorenzo Pieralisi
> > Sent: Monday, September 28, 2020 3:43 AM
> >
> > [+MarcZ - this patch needs IRQ maintainers vetting]
>
> Sure. Hi MarkZ, please also review the patch. Thanks!
>
>
On Tue, Sep 29, 2020 at 11:41:29PM +0800, Baolin Wang wrote:
> Hi,
>
> 锟斤拷 2020/9/28 23:23, Lorenzo Pieralisi 写锟斤拷:
> > On Mon, Sep 28, 2020 at 10:49:57PM +0800, Baolin Wang wrote:
> > > On Mon, Sep 28, 2020 at 03:00:55PM +0100, Will Deacon wrote:
> > > > [+ L
On Sat, Sep 26, 2020 at 09:49:56AM +0200, Bean Huo wrote:
> seems the Hisilicon PCI driver maintainers are absent, however, we are
> still using their old platform based on Kirin.
>
> hi, Lorenzo
> is it possible to take this patch without Hisilicon maintainter's ACK?
I applied it to pci/kirin, t
On Fri, Sep 18, 2020 at 11:12:51AM -0700, Kevin Hilman wrote:
> Enable pci-meson to build as a module whenever ARCH_MESON is enabled.
>
> Cc: Yue Wang
> Signed-off-by: Kevin Hilman
> ---
> Tested on Khadas VIM3 and Khadas VIM3 using NVMe SSD devices.
>
> drivers/pci/controller/dwc/Kconfig
On Mon, Sep 28, 2020 at 10:49:57PM +0800, Baolin Wang wrote:
> On Mon, Sep 28, 2020 at 03:00:55PM +0100, Will Deacon wrote:
> > [+ Lorenzo]
> >
> > On Tue, Sep 22, 2020 at 06:33:24PM +0800, Baolin Wang wrote:
> > > If the BIOS disabled the NUMA configuration, but did not change the
> > > proximity
On Wed, Sep 16, 2020 at 10:50:25AM +0800, Liu Shixin wrote:
> Use DEFINE_SEQ_ATTRIBUTE macro to simplify the code.
>
> Signed-off-by: Liu Shixin
> ---
> drivers/pci/controller/pci-tegra.c | 28 +++-
> 1 file changed, 3 insertions(+), 25 deletions(-)
Applied to pci/tegra,
[+MarcZ - this patch needs IRQ maintainers vetting]
On Tue, Sep 08, 2020 at 04:17:59PM -0700, Dexuan Cui wrote:
> Hyper-V doesn't trap and emulate the accesses to the MSI/MSI-X registers,
> and we must use hv_compose_msi_msg() to ask Hyper-V to create the IOMMU
> Interrupt Remapping Table Entries.
On Thu, Sep 24, 2020 at 04:24:47AM +, Z.q. Hou wrote:
> Hi Rob,
>
> Thanks a lot for your comments!
>
> > -Original Message-
> > From: Rob Herring
> > Sent: 2020年9月18日 23:28
> > To: Z.q. Hou
> > Cc: linux-kernel@vger.kernel.org; P
On Fri, Sep 18, 2020 at 09:58:51PM +0200, Arnd Bergmann wrote:
> On Fri, Sep 18, 2020 at 1:45 PM Lorenzo Pieralisi
> wrote:
> > >
> > > Lorenzo Pieralisi (3):
> > > sparc32: Remove useless io_32.h __KERNEL__ preprocessor guard
> > > sparc32: Move iore
On Fri, Sep 18, 2020 at 04:00:22PM +0800, Zhiqiang Hou wrote:
> From: Xiaowei Bao
>
> Add PCIe EP node for ls1088a to support EP mode.
>
> Signed-off-by: Xiaowei Bao
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Andrew Murray
> ---
> V8:
> - s/pcie_ep/pcie-ep.
>
> .../arm64/boot/dts/freesca
On Mon, Sep 21, 2020 at 10:16:24PM +0100, Alex Dewar wrote:
> brcm_pcie_resume() contains a return statement that was presumably
> intended to have an "if (ret)" in front of it, otherwise the function
> returns prematurely. Fix this.
>
> Additionally, redisable the clock on the error path.
>
> I
On Fri, Sep 18, 2020 at 02:38:00PM +0200, Bean Huo wrote:
> From: Bean Huo
>
> PCI driver might be probed before the gpiochip, so, of_get_named_gpio()
> can return -EPROBE_DEFER. And let kirin_pcie_probe() directly return
> -ENODEV, which will result in the PCIe probe failure and the PCIe
> will
On Fri, Sep 18, 2020 at 04:00:12PM +0800, Zhiqiang Hou wrote:
> From: Hou Zhiqiang
>
> Add the PCIe EP multiple PF support for DWC and Layerscape, and use
> a list to manage the PFs of each PCIe controller; add the doorbell
> MSIX function for DWC; and refactor the Layerscape EP driver due to
> s
On Wed, Sep 16, 2020 at 12:06:55PM +0100, Lorenzo Pieralisi wrote:
> v2 of a previous posting.
>
> v1->v2:
> - Added additional patch to remove sparc32 useless __KERNEL__
> guard
>
> v1:
> https://lore.kernel.org/lkml/20200915093203.16934-1-lorenzo.pier
I
> devices.
>
> Cc: Benjamin Herrenschmidt
> Cc: Bjorn Helgaas
> Cc: Catalin Marinas
> Cc: Jason Gunthorpe
> Cc: Lorenzo Pieralisi
> Cc: Will Deacon
> Signed-off-by: Clint Sbisa
> ---
> Changes in v2:
> - Rewrote the commit message.
>
> arc
On Tue, Aug 11, 2020 at 05:54:29PM +0800, Zhiqiang Hou wrote:
> From: Hou Zhiqiang
>
> Add the PCIe EP multiple PF support for DWC and Layerscape, and use
> a list to manage the PFs of each PCIe controller; add the doorbell
> MSIX function for DWC; and refactor the Layerscape EP driver due to
> s
On Fri, Sep 11, 2020 at 01:52:20PM -0400, Jim Quinlan wrote:
[...]
> Jim Quinlan (10):
> PCI: brcmstb: PCIE_BRCMSTB depends on ARCH_BRCMSTB
> dt-bindings: PCI: Add bindings for more Brcmstb chips
> PCI: brcmstb: Add bcm7278 register info
> PCI: brcmstb: Add suspend and resume pm_ops
> P
On Wed, Sep 16, 2020 at 03:51:11PM +0100, Catalin Marinas wrote:
> On Wed, Sep 16, 2020 at 12:06:58PM +0100, Lorenzo Pieralisi wrote:
> > For arches that do not select CONFIG_GENERIC_IOMAP, the current
> > pci_iounmap() function does nothing causing obvious memory leaks
> > fo
The __KERNEL_ preprocessor guard is useless in non-uapi headers.
Remove it.
Signed-off-by: Lorenzo Pieralisi
Cc: David S. Miller
---
arch/sparc/include/asm/io_32.h | 4
1 file changed, 4 deletions(-)
diff --git a/arch/sparc/include/asm/io_32.h b/arch/sparc/include/asm/io_32.h
index
com
https://lore.kernel.org/lkml/20200824132046.3114383-1-george.cher...@marvell.com
Cc: Bjorn Helgaas
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Arnd Bergmann
Cc: "David S. Miller"
Cc: George Cherian
Cc: Yang Yingliang
Lorenzo Pieralisi (3):
sparc32: Remove useless io_32
.74701-1-yangyingli...@huawei.com
Link:
https://lore.kernel.org/lkml/20200824132046.3114383-1-george.cher...@marvell.com
Signed-off-by: Lorenzo Pieralisi
Cc: Arnd Bergmann
Cc: George Cherian
Cc: Will Deacon
Cc: Bjorn Helgaas
Cc: Catalin Marinas
Cc: Yang Yingliang
---
include/asm-generic/i
Move the ioremap/iounmap declaration before asm-generic/io.h is
included so that it is visible within it.
Signed-off-by: Lorenzo Pieralisi
Cc: "David S. Miller"
---
arch/sparc/include/asm/io_32.h | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/
On Thu, Sep 03, 2020 at 01:34:54PM +0100, Shiju Jose wrote:
> CPER records describing a firmware-first error are identified by GUID.
> The ghes driver currently logs, but ignores any unknown CPER records.
> This prevents describing errors that can't be represented by a standard
> entry, that would
On Tue, Sep 15, 2020 at 03:14:52PM +0100, Christoph Hellwig wrote:
> > diff --git a/arch/sparc/include/asm/io_32.h b/arch/sparc/include/asm/io_32.h
> > index 9a52d9506f80..042201c79ad1 100644
> > --- a/arch/sparc/include/asm/io_32.h
> > +++ b/arch/sparc/include/asm/io_32.h
> > @@ -11,6 +11,16 @@
>
On Tue, Sep 15, 2020 at 01:47:21PM +1000, Stephen Rothwell wrote:
> Hi all,
>
> On Wed, 9 Sep 2020 10:06:20 -0600 Rob Herring wrote:
> >
> > On Tue, Sep 8, 2020 at 8:37 PM Stephen Rothwell
> > wrote:
> > >
> > > After merging the pci tree, today's linux-next build (arm
> > > multi_v7_defconfig)
Move the ioremap/iounmap declaration before asm-generic/io.h is
included so that it is visible within it.
Signed-off-by: Lorenzo Pieralisi
Cc: "David S. Miller"
---
arch/sparc/include/asm/io_32.h | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/
.74701-1-yangyingli...@huawei.com
Link:
https://lore.kernel.org/lkml/20200824132046.3114383-1-george.cher...@marvell.com
Signed-off-by: Lorenzo Pieralisi
Cc: Arnd Bergmann
Cc: George Cherian
Cc: Will Deacon
Cc: Bjorn Helgaas
Cc: Catalin Marinas
Cc: Yang Yingliang
---
include/asm-generic/i
://lore.kernel.org/lkml/20200905024811.74701-1-yangyingli...@huawei.com
https://lore.kernel.org/lkml/20200824132046.3114383-1-george.cher...@marvell.com
Cc: Bjorn Helgaas
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Arnd Bergmann
Cc: "David S. Miller"
Cc: George Cherian
Cc: Yang Yingliang
On Wed, Sep 09, 2020 at 02:54:01PM +0100, Catalin Marinas wrote:
> On Wed, Sep 09, 2020 at 12:36:13PM +0100, Lorenzo Pieralisi wrote:
> > On Mon, Sep 07, 2020 at 12:21:19PM +0100, Catalin Marinas wrote:
> > > On Mon, Sep 07, 2020 at 10:51:21AM +, George Cherian wrote:
>
On Wed, Sep 09, 2020 at 02:54:01PM +0100, Catalin Marinas wrote:
> On Wed, Sep 09, 2020 at 12:36:13PM +0100, Lorenzo Pieralisi wrote:
> > On Mon, Sep 07, 2020 at 12:21:19PM +0100, Catalin Marinas wrote:
> > > On Mon, Sep 07, 2020 at 10:51:21AM +, George Cherian wrote:
>
On Mon, Sep 07, 2020 at 12:21:19PM +0100, Catalin Marinas wrote:
> + Lorenzo
>
> On Mon, Sep 07, 2020 at 10:51:21AM +, George Cherian wrote:
> > Catalin Marinas wrote:
> > > On Sat, Sep 05, 2020 at 10:48:11AM +0800, Yang Yingliang wrote:
> > > > diff --git a/arch/arm64/kernel/pci.c b/arch/arm
On Mon, Aug 24, 2020 at 03:30:19PM -0400, Jim Quinlan wrote:
> From: Jim Quinlan
>
> Some STB chips have a special purpose reset controller named RESCAL (reset
> calibration). The PCIe HW can now control RESCAL to start and stop its
> operation. On probe(), the RESCAL is deasserted and the driv
On Mon, Sep 07, 2020 at 11:29:06AM -0700, Florian Fainelli wrote:
>
>
> On 9/7/2020 10:43 AM, Jim Quinlan wrote:
> > On Mon, Sep 7, 2020 at 5:16 AM Lorenzo Pieralisi
> > wrote:
> > >
> > > On Thu, Aug 27, 2020 at 09:29:59AM -0400, Jim Quinlan wrote:
On Mon, Sep 07, 2020 at 01:10:33PM +0200, Pali Rohár wrote:
> Hi,
>
> we have some more improvements for PCIe aardvark controller (Armada 3720
> SOC - EspressoBIN and Turris MOX).
>
> The main improvement is that with these patches the driver can be compiled
> as a module, and can be reloaded at
On Mon, Jul 06, 2020 at 10:05:06AM +0530, Vidya Sagar wrote:
>
>
> On 18-Jun-20 12:26 AM, Vidya Sagar wrote:
> >
> >
> > On 02-Jun-20 10:37 PM, Gustavo Pimentel wrote:
> > > External email: Use caution opening links or attachments
> > >
> > >
> > > On Tue, Jun 2, 2020 at 11:9:38, Vidya Sagar
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