On Mon, May 18, 2020 at 12:30:04PM +0200, Pali Rohár wrote:
> On Sunday 17 May 2020 17:57:02 Gregory CLEMENT wrote:
> > Hello,
> >
> > > Hello,
> > >
> > > On Thu, 30 Apr 2020 10:06:13 +0200
> > > Pali Rohár wrote:
> > >
> > >> Marek Behún (5):
> > >> PCI: aardvark: Improve link training
> >
Address Hanjun and Robin's comments.
>
> drivers/acpi/arm64/iort.c | 5 +
> 1 file changed, 5 insertions(+)
Acked-by: Lorenzo Pieralisi
> diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
> index ed3d2d1..12bb70e 100644
> --- a/drivers/acpi/arm64/i
On Tue, May 05, 2020 at 06:13:13PM +0200, Nicolas Saenz Julienne wrote:
> On the Raspberry Pi 4, after a PCI reset, VL805's firmware may either be
> loaded directly from an EEPROM or, if not present, by the SoC's
> co-processor, VideoCore. This series adds support for the later.
>
> Note that
On Wed, May 13, 2020 at 01:16:51PM +0200, Pali Rohár wrote:
> On Thursday 30 April 2020 10:06:13 Pali Rohár wrote:
> > Hello,
> >
> > this is the fourth version of the patch series for Armada 3720 PCIe
> > controller (aardvark). It's main purpose is to fix some bugs regarding
> > buggy ath10k
On Tue, May 05, 2020 at 06:13:13PM +0200, Nicolas Saenz Julienne wrote:
> On the Raspberry Pi 4, after a PCI reset, VL805's firmware may either be
> loaded directly from an EEPROM or, if not present, by the SoC's
> co-processor, VideoCore. This series adds support for the later.
>
> Note that
On Wed, Apr 01, 2020 at 04:58:13PM -0700, Alan Mikhak wrote:
> From: Alan Mikhak
>
> Function dw_pcie_prog_outbound_atu_unroll() does not program the upper
> 32-bit ATU limit register. Since ATU programming functions limit the
> size of the translated region to 4GB by using a u32 size parameter,
On Mon, May 11, 2020 at 01:22:56PM -0700, Tuan Phan wrote:
> PMCG node can have zero ID mapping if its overflow interrupt
> is wire based. The code to parse PMCG node can not assume it will
> have a single ID mapping.
>
> Signed-off-by: Tuan Phan
> ---
> drivers/acpi/arm64/iort.c | 4 +++-
> 1
On Tue, May 05, 2020 at 06:13:17PM +0200, Nicolas Saenz Julienne wrote:
> On the Raspberry Pi 4, after a PCI reset, VL805's firmware may either be
> loaded directly from an EEPROM or, if not present, by the SoC's
> VideoCore. Inform VideoCore that VL805 was just reset.
>
> Also, as this creates a
On Wed, May 06, 2020 at 07:21:30AM +0200, Lukas Bulwahn wrote:
> Commit 3edeb49525bb ("dt-bindings: PCI: Add NXP Layerscape SoCs PCIe Gen4
> controller") includes a new entry in MAINTAINERS, but slipped in a typo in
> one of the file entries.
>
> Hence, since then, ./scripts/get_maintainer.pl
ated. Thanks Lorenzo Pieralisi for the review and
> suggestions, as well as Michael Kelley's contribution to the commit
> log.
>
> Thanks,
> Wei
>
>
> Wei Hu (2):
> PCI: hv: Fix the PCI HyperV probe failure path to release resource
> properly
> PCI: hv:
On Thu, May 07, 2020 at 01:03:00PM +0800, Wei Hu wrote:
> In the case of kdump, the PCI device was not cleanly shut down
> before the kdump kernel starts. This causes the initial
> attempt of entering D0 state in the kdump kernel to fail with
> invalid device state returned from Hyper-V host.
>
On Thu, May 07, 2020 at 04:15:39PM -0400, Jim Quinlan wrote:
> v3 -- A change was submitted to [1] to make 'aspm-no-l0s' a general
> property for PCIe devices. As such, the STB PCIe YAML file
> merely notes that it may be used.
>
> v2 -- Dropped commit concerning CRS.
>--
On Thu, May 07, 2020 at 07:20:20PM +0200, Nicolas Saenz Julienne wrote:
> While preparing the driver for upstream this detail was missed.
>
> If not asserted during the initialization process, devices connected on
> the bus will not be made aware of the internal reset happening. This,
>
On Thu, May 07, 2020 at 01:33:11PM +0100, Lad Prabhakar wrote:
> Hi All,
>
> This patch series adds support for endpoint driver for R-Car PCIe controller
> on
> R-Car/RZ-G2x SoC's, this also extends the epf framework to handle multiple
> windows
> supported by the controller for mapping PCI
On Wed, Apr 29, 2020 at 05:42:30PM +0100, Marc Zyngier wrote:
> My vim3l board stubbornly refuses to play ball with a bog
> standard PCIe switch (ASM1184e), spitting all kind of errors
> ranging from link never coming up to crazy things like downstream
> ports falling off the face of the planet.
>
On Tue, Apr 14, 2020 at 12:25:12PM +0200, Pali Rohár wrote:
> Error code is stored in rp->reset_gpio and not in err variable.
>
> Signed-off-by: Pali Rohár
> ---
> drivers/pci/controller/pci-tegra.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Applied to pci/tegra, thanks.
On Wed, May 06, 2020 at 02:55:17PM +, Michael Kelley wrote:
[...]
> > Hv_pci_bus_exit() calls hv_send_resources_released() to release all child
> > resources.
> > These child resources were allocated in hv_send_resources_allocated().
> > Hv_send_resources_allocated() could fail in the
On Wed, May 06, 2020 at 05:36:46AM +, Wei Hu wrote:
> Hi Lorenzo,
>
> Thanks for your review. Please see my comments inline.
>
> > -Original Message-
> > From: Lorenzo Pieralisi
> > Sent: Tuesday, May 5, 2020 11:03 PM
> > To: Wei Hu
&
On Fri, May 01, 2020 at 01:37:28PM +0800, Wei Hu wrote:
> In the case of kdump, the PCI device was not cleanly shut down
> before the kdump kernel starts. This causes the initial
> attempt of entering D0 state in the kdump kernel to fail with
> invalid device state returned from Hyper-V host.
>
On Fri, May 01, 2020 at 01:36:17PM +0800, Wei Hu wrote:
> Some error cases in hv_pci_probe() were not handled. Fix these error
> paths to release the resourses and clean up the state properly.
This patch does more than that. It adds a variable to store the
number of slots actually allocated - I
On Fri, May 01, 2020 at 12:39:21PM +0100, Marc Zyngier wrote:
> On a system that uses the internal DWC MSI widget, I get this
> warning from debugfs when CONFIG_GENERIC_IRQ_DEBUGFS is selected:
>
> debugfs: File ':soc:pcie@fc00' in directory 'domains' already present!
>
> This is due to
On Fri, Mar 27, 2020 at 01:45:56PM +, Colin King wrote:
> From: Colin Ian King
>
> A return statment is indented incorrectly, remove extraneous space.
>
> Signed-off-by: Colin Ian King
> ---
> drivers/pci/controller/pcie-altera.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
On Wed, Apr 22, 2020 at 04:24:47PM +0900, Kunihiko Hayashi wrote:
> When unbinding pci_epf_test, pci_epf_test_clean_dma_chan() is called in
> pci_epf_test_unbind() even though epf_test->dma_supported is false.
> As a result, dma_release_channel() will occur null pointer access because
> dma_chan
On Sat, Apr 18, 2020 at 10:16:37AM +0200, Christophe JAILLET wrote:
> IF we fails somewhere in 'v3_pci_probe()', we need to free 'host'.
> Use the managed version of 'pci_alloc_host_bridge()' to do that easily.
> The use of managed resources is already widely used in this driver.
>
> Fixes:
On Wed, Apr 15, 2020 at 04:49:53PM +0800, Jason Yan wrote:
> Fix the following sparse warning:
>
> drivers/pci/controller/dwc/pcie-intel-gw.c:456:5: warning: symbol
> 'intel_pcie_cpu_addr' was not declared. Should it be static?
>
> Reported-by: Hulk Robot
> Signed-off-by: Jason Yan
> ---
>
On Wed, Apr 01, 2020 at 04:58:13PM -0700, Alan Mikhak wrote:
> From: Alan Mikhak
>
> Function dw_pcie_prog_outbound_atu_unroll() does not program the upper
> 32-bit ATU limit register. Since ATU programming functions limit the
> size of the translated region to 4GB by using a u32 size parameter,
On Thu, Apr 23, 2020 at 11:18:03AM +0800, Zou Wei wrote:
> Fix the following sparse warning:
>
> drivers/pci/controller/dwc/pcie-hisi.c:365:21: warning:
> symbol 'hisi_pcie_platform_ops' was not declared. Should it be static?
>
> Reported-by: Hulk Robot
> Signed-off-by: Zou Wei
> ---
>
ded
> addr is (void *) already.
>
> objdump -d shows no difference after this patch.
>
> Signed-off-by: Jiri Slaby
> Cc: Kishon Vijay Abraham I
> Cc: Lorenzo Pieralisi
> ---
> drivers/pci/controller/dwc/pcie-designware-ep.c | 6 +-
> 1 file changed, 1 inserti
On Thu, Apr 30, 2020 at 09:43:20AM +0100, Lad, Prabhakar wrote:
> Hi Kishon,
>
> On Thu, Apr 23, 2020 at 7:23 PM Lad Prabhakar
> wrote:
> >
> > Hi All,
> >
> > This patch series adds support for endpoint driver for R-Car PCIe
> > controller on
> > R-Car/RZ-G2x SoC's, this also extends the epf
On Mon, May 04, 2020 at 02:22:30PM +0530, Kishon Vijay Abraham I wrote:
> Hi Lorenzo,
>
> On 5/1/2020 8:41 PM, Lorenzo Pieralisi wrote:
> > On Fri, Apr 17, 2020 at 05:13:22PM +0530, Kishon Vijay Abraham I wrote:
> >> The PCI Bus Binding specification (IEEE Std 1
On Fri, Apr 17, 2020 at 05:13:22PM +0530, Kishon Vijay Abraham I wrote:
> The PCI Bus Binding specification (IEEE Std 1275-1994 Revision 2.1 [1])
> defines both Vendor ID and Device ID to be 32-bits. Fix
> pcie-cadence-host.c driver to read 32-bit Vendor ID and Device ID
> properties from device
[+Robin - to check on dma-ranges intepretation]
I would need RobH and Robin to review this.
Also, An ACK from Tom is required - for the whole series.
On Fri, Apr 17, 2020 at 05:13:20PM +0530, Kishon Vijay Abraham I wrote:
> Cadence PCIe core driver (host mode) uses "cdns,no-bar-match-nbits"
>
On Thu, Oct 17, 2019 at 07:57:56PM +0530, Abhishek Shah wrote:
> Hi Lorenzo,
>
> Please see my comments inline:
>
> On Tue, Oct 15, 2019 at 10:13 PM Lorenzo Pieralisi
> wrote:
> >
> > On Fri, Sep 06, 2019 at 09:28:13AM +0530, Abhishek Shah wrote:
> > > I
On Sat, Oct 05, 2019 at 10:12:11PM +0530, Vidya Sagar wrote:
> Corrects the programming to provide REFCLK to the downstream device
> when there is no CLKREQ sideband signal routing present from root port
> to the endpont.
>
> Signed-off-by: Vidya Sagar
> ---
>
On Wed, Oct 16, 2019 at 02:02:49PM +0200, Simon Horman wrote:
> At the end of the v5.3 upstream development cycle I stepped down
> from my role at Renesas.
>
> Pass maintainership of the R-Car PCIE to Marek and Shimoda-san.
>
> Signed-off-by: Simon Horman
> ---
> MAINTAINERS | 3 ++-
> 1 file
On Wed, Oct 16, 2019 at 02:02:49PM +0200, Simon Horman wrote:
> At the end of the v5.3 upstream development cycle I stepped down
> from my role at Renesas.
>
> Pass maintainership of the R-Car PCIE to Marek and Shimoda-san.
>
> Signed-off-by: Simon Horman
> ---
> MAINTAINERS | 3 ++-
> 1 file
n
> expression (different address spaces)
> drivers/pci/controller/pci-mvebu.c:716:31:expected void [noderef]
> *
> drivers/pci/controller/pci-mvebu.c:716:31:got void *
>
> Signed-off-by: Ben Dooks
> ---
> Cc: Thomas Petazzoni
> Cc: Jason Cooper
> Cc:
ci_bridge_emul_ops' was not declared. Should it be static?
>
> Signed-off-by: Ben Dooks
> ---
> Cc: Thomas Petazzoni
> Cc: Jason Cooper
> Cc: Lorenzo Pieralisi
> Cc: Andrew Murray
> Cc: Bjorn Helgaas
> Cc: linux-...@vger.kernel.org
> Cc: linux-arm-ker...@lists.
n
> argument 1 (different address spaces)
> drivers/pci/controller/pcie-iproc-msi.c:301:17:expected void const
> volatile [noderef] *addr
> drivers/pci/controller/pcie-iproc-msi.c:301:17:got unsigned int
> [usertype] *[assigned] msg
>
> Signed-off-by: Ben Dooks
On Wed, Aug 28, 2019 at 02:24:43PM +0530, Srinath Mannam wrote:
> From: Ray Jui
>
> Update the iProc PCIe binding document for better modeling of the legacy
> interrupt (INTx) support
>
> Signed-off-by: Ray Jui
> Signed-off-by: Srinath Mannam
> ---
>
On Tue, Oct 15, 2019 at 10:28:24AM -0700, Florian Fainelli wrote:
> On 9/4/19 10:16 AM, Florian Fainelli wrote:
> > On 8/28/19 1:54 AM, Srinath Mannam wrote:
> >> This patch series adds PCIe legacy interrupt (INTx) support to the iProc
> >> PCIe driver by modeling it with its own IRQ domain. All 4
On Fri, Sep 06, 2019 at 08:50:07PM +0200, Markus Elfring wrote:
> From: Markus Elfring
> Date: Fri, 6 Sep 2019 20:40:06 +0200
>
> Simplify these function implementations by using a known function.
>
> Generated by: scripts/coccinelle/api/ptr_ret.cocci
>
> Signed-off-by: Markus Elfring
> ---
>
On Fri, Sep 06, 2019 at 09:28:13AM +0530, Abhishek Shah wrote:
> Invalidate PAXB inbound/outbound address mapping each time before
> programming it. This is helpful for the cases where we need to
> reprogram inbound/outbound address mapping without resetting PAXB.
> kexec kernel is one such
On Wed, Sep 04, 2019 at 06:03:38PM +0200, Niklas Cassel wrote:
> find_next_bit() takes a parameter of size long, and performs arithmetic
> that assumes that the argument is of size long.
>
> Therefore we cannot pass a u32, since this will cause find_next_bit()
> to read outside the stack buffer
t;csr_write"
> passed 4 arguments, but takes just 2
> static void csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off, size_t
> size)
>
> Cc: Hou Zhiqiang
> Cc: Lorenzo Pieralisi
> Cc: Minghuan Lian
> Cc: Subrahmanya Lingappa
> Cc: Andrew Murray
&
On Wed, Oct 09, 2019 at 10:06:56AM -0700, Alan Mikhak wrote:
> From: Alan Mikhak
>
> Modify pci_epc_mem_alloc_addr() to cast the variable 'pageno'
> from type 'int' to 'phys_addr_t' before shifting left. This
> cast is needed to avoid treating bit 31 of 'pageno' as the
> sign bit which would
On Mon, Sep 16, 2019 at 02:50:16PM +0200, Neil Armstrong wrote:
> This patchset :
> - updates the Amlogic PCI bindings for G12A
> - reworks the Amlogic PCIe driver to make use of the
> G12a USB3+PCIe Combo PHY instead of directly writing in
> the PHY register
> - adds the necessary operations to
On Fri, Sep 27, 2019 at 10:55:02AM +0200, Remi Pommarel wrote:
> advk_pcie_wait_pio() can be called while holding a spinlock (from
> pci_bus_read_config_dword()), then depends on jiffies in order to
> timeout while polling on PIO state registers. In the case the PIO
> transaction failed, the
On Fri, Jun 14, 2019 at 12:10:59PM +0200, Remi Pommarel wrote:
> PCI_EXP_RTCTL is used to activate PME interrupt only, so writing into it
> should not modify other interrupts' mask. The ISR mask polarity was also
> inverted, when PCI_EXP_RTCTL_PMEIE is set PCIE_MSG_PM_PME_MASK mask bit
> should
On Wed, May 22, 2019 at 11:33:50PM +0200, Remi Pommarel wrote:
> When configuring pcie reset pin from gpio (e.g. initially set by
> u-boot) to pcie function this pin goes low for a brief moment
> asserting the PERST# signal. Thus connected device enters fundamental
> reset process and link
On Wed, May 22, 2019 at 11:33:51PM +0200, Remi Pommarel wrote:
> Aardvark's PCI_EXP_LNKSTA_LT flag in its link status register is not
> implemented and does not reflect the actual link training state (the
> flag is always set to 0). In order to support link re-training feature
> this flag has to
On Tue, Aug 06, 2019 at 08:49:46PM +0200, Remi Pommarel wrote:
> On Wed, May 22, 2019 at 11:33:50PM +0200, Remi Pommarel wrote:
> > When configuring pcie reset pin from gpio (e.g. initially set by
> > u-boot) to pcie function this pin goes low for a brief moment
> > asserting the PERST# signal.
On Mon, Oct 14, 2019 at 12:48:29PM +0530, Pankaj Dubey wrote:
> From: Anvesh Salveru
>
> In some platforms, PCIe PHY may have issues which will prevent linkup
> to happen in GEN3 or higher speed. In case equalization fails, link will
> fallback to GEN1.
>
> DesignWare controller gives
On Sun, Oct 13, 2019 at 11:34:15AM +0100, Marc Zyngier wrote:
> On Tue, 1 Oct 2019 09:05:46 +0100
> Andrew Murray wrote:
>
> Hi Lorenzo,
>
> > On Mon, Sep 30, 2019 at 06:52:30PM +0200, Remi Pommarel wrote:
> > > On Mon, Sep 30, 2019 at 04:40:18PM +0100, Andrew Murray wrote:
> > > > On Wed,
On Wed, Sep 11, 2019 at 11:38:20PM +, Dexuan Cui wrote:
> Implement the suspend/resume callbacks for hibernation.
>
> hv_pci_suspend() needs to prevent any new work from being queued: a later
> patch will address this issue.
I don't see why you have two separate patches, the second one
On Wed, Sep 11, 2019 at 11:38:23PM +, Dexuan Cui wrote:
> A VM can have multiple hbus. It looks incorrect for the second hbus's
> hv_pci_protocol_negotiation() to set the global variable
> 'pci_protocol_version' (which was set by the first hbus), even if the
> same value is written.
>
>
jj/pci-epf-uaf.txt
>
> ...
>
> From: Hillf Danton
>
> To: Bjorn Helgaas
>
> Cc: linux-pci ,
>
> LKML ,
>
> Randy Dunlap ,
>
> Al Viro ,
>
> Dan Carpenter ,
>
> Lorenzo Pieralisi ,
>
>
On Tue, Sep 17, 2019 at 11:10:37AM +0530, Kishon Vijay Abraham I wrote:
>
> On 16/09/19 4:52 PM, Lorenzo Pieralisi wrote:
> > On Mon, Sep 16, 2019 at 10:06:30AM +0800, Hillf Danton wrote:
> >>
> >> On Sun, 15 Sep 2019 09:34:37 -0700
> >>>
> >>
On Fri, Sep 20, 2019 at 04:07:14PM +0100, Andrew Murray wrote:
> On Fri, Sep 20, 2019 at 04:55:05PM +0200, Arnd Bergmann wrote:
> > Without this, we can run into a build failure:
> >
> > drivers/pci/controller/dwc/pcie-tegra194.c:1394:8: error: implicit
> > declaration of function
On Fri, Sep 20, 2019 at 06:39:25PM +0800, YueHaibing wrote:
> Fix build error without CONFIG_PINCTRL
>
> drivers/pci/controller/dwc/pcie-tegra194.c: In function tegra_pcie_config_rp:
> drivers/pci/controller/dwc/pcie-tegra194.c:1394:8: error: implicit
> declaration of function
On Mon, Sep 16, 2019 at 07:54:33AM -0600, Jon Derrick wrote:
> Hi Lorenzo, Bjorn, Keith,
>
> Please consider the following patches for 5.4 inclusion.
>
> These will apply to 5.2 stable. 4.19 has a few feature deps so I will instead
> follow-up with a backport.
>
> Jon Derrick (2):
> PCI: vmd:
On Tue, Sep 17, 2019 at 03:51:39PM +, Derrick, Jonathan wrote:
[...]
> Sorry for the confusion.
>
> These changes only affect systems with VMD devices with 8086:28C0
> device IDs, but these won't be production hardware for some time.
>
> Systems with VMD devices exist in the wild with
On Tue, Sep 17, 2019 at 02:45:03PM +, Derrick, Jonathan wrote:
> On Tue, 2019-09-17 at 15:05 +0100, Lorenzo Pieralisi wrote:
> > On Tue, Sep 17, 2019 at 01:55:59PM +, Derrick, Jonathan wrote:
> > > On Tue, 2019-09-17 at 11:41 +0100, Lorenzo Pieralisi wrote:
> >
On Tue, Sep 17, 2019 at 01:55:59PM +, Derrick, Jonathan wrote:
> On Tue, 2019-09-17 at 11:41 +0100, Lorenzo Pieralisi wrote:
> > On Mon, Sep 16, 2019 at 07:54:35AM -0600, Jon Derrick wrote:
> > > The shadow offset scratchpad was moved to 0x2000-0x2010. Update the
>
On Mon, Sep 16, 2019 at 07:54:35AM -0600, Jon Derrick wrote:
> The shadow offset scratchpad was moved to 0x2000-0x2010. Update the
> location to get the correct shadow offset.
Hi Jon,
what does "was moved" mean ? Would this code still work on previous HW ?
We must make sure that the address
On Mon, Sep 16, 2019 at 10:06:30AM +0800, Hillf Danton wrote:
>
> On Sun, 15 Sep 2019 09:34:37 -0700
> >
> > Kernel is 5.3-rc8 on x86_64.
> >
> > Loading and removing the pci-epf-test module causes a BUG.
> >
> >
> > [40928.435755] calling pci_epf_test_init+0x0/0x1000 [pci_epf_test] @ 12132
Add Andrew Murray as designated reviewer for PCI native host
and endpoint controller drivers.
Signed-off-by: Lorenzo Pieralisi
Cc: Andrew Murray
Cc: Bjorn Helgaas
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 783569e3c4b4..08d97988034d
On Thu, Sep 12, 2019 at 04:00:42PM +0300, Jonathan Chocron wrote:
> The Root Port (identified by [1c36:0031]) doesn't support MSI-X. On some
> platforms it is configured to not advertise the capability at all, while
> on others it (mistakenly) does. This causes a panic during
> initialization by
On Sat, Sep 07, 2019 at 11:55:42AM -0500, Bjorn Helgaas wrote:
> s/Add quirk to disable/Disable/ in subject
>
> On Thu, Sep 05, 2019 at 05:00:18PM +0300, Jonathan Chocron wrote:
> > The Root Port (identified by [1c36:0031]) doesn't support MSI-X. On some
> > platforms it is configured to not
On Mon, Sep 09, 2019 at 11:10:06PM +, Haiyang Zhang wrote:
>
>
> > -Original Message-
> > From: Lorenzo Pieralisi
> > Sent: Wednesday, August 21, 2019 5:03 AM
> > To: Stephen Rothwell
> > Cc: Bjorn Helgaas ; Linux Next Mailing List > n...
On Thu, Sep 05, 2019 at 05:00:14PM +0300, Jonathan Chocron wrote:
> This series adds support for Amazon's Annapurna Labs DT-based PCIe host
> controller driver.
> Additionally, it adds 3 quirks (ACS, VPD and MSI-X) and 2 generic DWC patches.
>
> Changes since v4:
> - Moved the HEADER_TYPE
On Thu, Sep 05, 2019 at 04:15:47PM +0530, Vidya Sagar wrote:
> This patch series enables Tegra194's C5 controller which owns x16 slot in
> p2972- platform. C5 controller's PERST# and CLKREQ# are not configured as
> output and bi-directional signals by default and hence they need to be
>
On Thu, Sep 05, 2019 at 01:44:46PM +0530, Vidya Sagar wrote:
> Hi Lorenzo / Bjorn,
> Can you please review this series?
> I have Reviewed-by and Acked-by from Rob, Thierry and Andrew already.
Rebase it on top of my pci/tegra branch (it does not apply),
resend it and I will merge it.
Thanks,
an ; Haiyang Zhang
> > ; Stephen Hemminger
> > ; Sasha Levin ; Lorenzo
> > Pieralisi ; linux-...@vger.kernel.org; linux-
> > ker...@vger.kernel.org; linux-hyp...@vger.kernel.org
> > Subject: [PATCH v3] PCI: hv: Make functions static
> >
> > Functions
On Sun, Sep 01, 2019 at 04:23:03PM +0200, Remi Pommarel wrote:
> advk_pcie_wait_pio() can be called while holding a spinlock (from
> pci_bus_read_config_dword()), then depends on jiffies in order to
> timeout while polling on PIO state registers. In the case the PIO
> transaction failed, the
On Wed, Aug 21, 2019 at 06:35:40PM +0300, Jonathan Chocron wrote:
> This series adds support for Amazon's Annapurna Labs DT-based PCIe host
> controller driver.
> Additionally, it adds 3 quirks (ACS, VPD and MSI-X) and 2 generic DWC patches.
>
> Changes since v3:
> - Removed PATCH 8/8 since the
On Sat, Aug 31, 2019 at 09:51:05AM +0530, Vidya Sagar wrote:
> On 8/30/2019 6:00 PM, Bjorn Helgaas wrote:
> > [+cc Krzysztof]
> >
> > On Thu, Aug 29, 2019 at 10:23 PM Stephen Rothwell
> > wrote:
> > >
> > > Hi all,
> > >
> > > After merging the pci tree, today's linux-next build (x86_64
On Wed, Aug 28, 2019 at 08:00:56AM -0500, Bjorn Helgaas wrote:
> On Thu, Aug 01, 2019 at 04:25:29PM -0500, Bjorn Helgaas wrote:
> > Hi,
> >
> > I got the following dmesg log from Fawad [1]:
> >
> > imx6q-pcie 1ffc000.pcie: host bridge /soc/pcie@1ffc000 ranges:
> > imx6q-pcie 1ffc000.pcie:
On Fri, Aug 23, 2019 at 08:48:32PM +0530, Vidya Sagar wrote:
> APIs like devm_regulator_get() and devm_phy_get() have the potential to
> return -EPROBE_DEFER when the respective sub-systems are not ready yet.
> So avoid printing an error message as .probe() will be tried out again
> at a later
On Fri, Aug 23, 2019 at 08:46:18PM +0530, Vidya Sagar wrote:
> When a platform has an open PCIe slot, not having a device connected to
> it doesn't have to result in a dev_err() print saying that the link is
> not up but a dev_info() would suffice.
>
> Signed-off-by: Vidya Sagar
> ---
>
On Fri, Aug 23, 2019 at 04:26:41PM +0800, Xiaowei Bao wrote:
> Add the PCIe compatible string for LS1028A
>
> Signed-off-by: Xiaowei Bao
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Rob Herring
> ---
> v2:
> - No change.
> v3:
> - No change.
> v4:
> - No change.
>
>
On Tue, Aug 20, 2019 at 07:28:37AM +, Z.q. Hou wrote:
> From: Hou Zhiqiang
>
> On FSL Layerscape SoCs, the number of lanes assigned to PCIe
> controller is not fixed, it is determined by the selected
> SerDes protocol. The current num-lanes indicates the max lanes
> PCIe controller can
On Fri, Aug 23, 2019 at 10:44:25AM +0100, Andrew Murray wrote:
> On Thu, Aug 22, 2019 at 05:48:15PM +0100, Lorenzo Pieralisi wrote:
> > On Tue, Aug 20, 2019 at 07:28:37AM +, Z.q. Hou wrote:
> > > From: Hou Zhiqiang
> > >
> > > On FSL Layerscape SoCs,
On Tue, Aug 20, 2019 at 07:28:43AM +, Z.q. Hou wrote:
> From: Hou Zhiqiang
>
> The num-lanes is not a mandatory property, e.g. on FSL
> Layerscape SoCs, the PCIe link training is completed
> automatically base on the selected SerDes protocol, it
> doesn't need the num-lanes to set-up the
On Tue, Aug 20, 2019 at 07:28:37AM +, Z.q. Hou wrote:
> From: Hou Zhiqiang
>
> On FSL Layerscape SoCs, the number of lanes assigned to PCIe
> controller is not fixed, it is determined by the selected
> SerDes protocol. The current num-lanes indicates the max lanes
> PCIe controller can
On Sat, Jul 13, 2019 at 10:11:29PM +0800, Hou Zhiqiang wrote:
> The current code erroneously sets-up the CPU base address with
> parameter 'pci_addr', which is passed to initialize the PCI
> base address of the inbound window, and the upper 32-bit of the
> CPU base address of the inbound window is
On Wed, Aug 21, 2019 at 01:01:23PM +0100, Colin King wrote:
> From: Colin Ian King
>
> The check for pcie->phy_count < 0 is always false because phy_count
> is an unsigned int and can never be less than zero. Fix this by
> assigning ret to the return from of_property_count_strings and
> checking
On Wed, Aug 21, 2019 at 07:19:39AM +1000, Stephen Rothwell wrote:
> Hi all,
>
> Commit
>
> c4a29fbba415 ("PCI: hv: Use bytes 4 and 5 from instance ID as the PCI
> domain numbers")
>
> is missing a Signed-off-by from its committer.
>
> Also, all the tags should be kept together, please.
On Thu, Aug 15, 2019 at 05:01:37PM +, Haiyang Zhang wrote:
> Currently in Azure cloud, for passthrough devices, the host sets the device
> instance ID's bytes 8 - 15 to a value derived from the host HWID, which is
> the same on all devices in a VM. So, the device instance ID's bytes 8 and 9
>
On Thu, Aug 15, 2019 at 05:01:37PM +, Haiyang Zhang wrote:
> Currently in Azure cloud, for passthrough devices, the host sets the device
> instance ID's bytes 8 - 15 to a value derived from the host HWID, which is
> the same on all devices in a VM. So, the device instance ID's bytes 8 and 9
>
On Wed, Aug 14, 2019 at 03:52:15PM +, Haiyang Zhang wrote:
> Currently in Azure cloud, for passthrough devices, the host sets the device
> instance ID's bytes 8 - 15 to a value derived from the host HWID, which is
> the same on all devices in a VM. So, the device instance ID's bytes 8 and 9
>
On Fri, Jul 26, 2019 at 04:40:07PM +0200, Stefan Agner wrote:
> Define the length of the DBI registers and limit config space to its
> length. This makes sure that the kernel does not access registers
> beyond that point, avoiding the following abort on a i.MX 6Quad:
> # cat
On Fri, Jul 12, 2019 at 08:53:19AM -0700, Randy Dunlap wrote:
> From: Randy Dunlap
>
> Fix build errors when building almost-allmodconfig but with SYSFS
> not set (not enabled). Fixes these build errors:
>
> ERROR: "pci_destroy_slot" [drivers/pci/controller/pci-hyperv.ko] undefined!
> ERROR:
On Tue, Jul 23, 2019 at 04:21:07PM -0500, Bjorn Helgaas wrote:
> On Sat, Jul 13, 2019 at 11:03:53AM -0400, Sasha Levin wrote:
[...]
> > > > v3: corrected Fixes: tag [Dexuan Cui ]
> > > > This is the Microsoft-preferred version of the patch.
> > > >
> > > > drivers/pci/Kconfig |2 +-
> >
On Wed, Aug 14, 2019 at 09:48:00AM +, Xiaowei Bao wrote:
>
>
> > -Original Message-
> > From: Lorenzo Pieralisi
> > Sent: 2019年8月14日 17:30
> > To: Xiaowei Bao
> > Cc: M.h. Lian ; Mingkai Hu
> > ; Roy Zang ;
> > bhelg...@goog
I asked you to remove the period at the end of the patch $SUBJECT and
you did not, either you do not read what I write or explain me what's
going on.
On Wed, Aug 14, 2019 at 10:03:29AM +0800, Xiaowei Bao wrote:
> The PCIe controller of layerscape just have 4 BARs, BAR0 and BAR1
> is 32bit, BAR2
On Tue, Aug 13, 2019 at 05:06:14PM +0530, Vidya Sagar wrote:
> Tegra194 has six PCIe controllers based on Synopsys DesignWare core.
> There are two Universal PHY (UPHY) blocks with each supporting 12(HSIO:
> Hisg Speed IO) and 8(NVHS: NVIDIA High Speed) lanes respectively.
> Controllers:0~4 use
On Tue, Aug 13, 2019 at 12:55:59PM +, Haiyang Zhang wrote:
>
>
> > -Original Message-
> > From: Lorenzo Pieralisi
> > Sent: Tuesday, August 13, 2019 6:14 AM
> > To: Haiyang Zhang
> > Cc: sas...@kernel.org; bhelg...@google.com; linu
Some style comments - we have time to fix them.
On Fri, Aug 09, 2019 at 10:16:09AM +0530, Vidya Sagar wrote:
[...]
I do not know why up to here the line spacing is OK and here
you started cramming code all together :)
Just a matter of consistency, thanks for fixing them up.
> +static void
On Sat, Jun 15, 2019 at 02:48:24PM +0800, Yuehaibing wrote:
> +cc Lorenzo Pieralisi
Can we drop this patch and merge:
https://patchwork.ozlabs.org/patch/1131444/
instead ?
Thanks,
Lorenzo
>
> On 2019/6/15 14:18, Yuehaibing wrote:
> >
> > On 2019/6/2 6:59, Michael Ke
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