On Fri, Mar 08, 2019 at 02:07:51PM +0100, Ulf Hansson wrote:
> On Fri, 8 Mar 2019 at 12:49, Lorenzo Pieralisi
> wrote:
> >
> > On Fri, Mar 08, 2019 at 11:36:49AM +0100, Ulf Hansson wrote:
> >
> > [...]
> >
> > > Instead, my suggestion is according to
On Fri, Mar 08, 2019 at 11:36:49AM +0100, Ulf Hansson wrote:
[...]
> Instead, my suggestion is according to what I propose in patch 4 and
> $subject patch, which means minor adjustments to be able to pass the
> struct cpuidle_driver * to the init functions. This, I need it for
> next steps, but
On Mon, Mar 04, 2019 at 11:14:18AM +0100, Ulf Hansson wrote:
> On Fri, 1 Mar 2019 at 18:28, Mark Rutland wrote:
> >
> > On Thu, Feb 28, 2019 at 02:59:17PM +0100, Ulf Hansson wrote:
> > > Instead of iterating through all the state nodes in DT, to find out how
> > > many states that needs to be
On Fri, Mar 01, 2019 at 08:50:48AM +0800, Ley Foon Tan wrote:
> On Thu, 2019-02-28 at 10:56 +0000, Lorenzo Pieralisi wrote:
> > On Thu, Feb 28, 2019 at 06:52:50PM +0800, Ley Foon Tan wrote:
> >
> > [...]
> >
> > >
> > > +static int s10_tlp_read_pack
On Fri, Mar 01, 2019 at 06:54:45AM +, Maya Nakamura wrote:
> This patchset removes a duplicate definition of VP set (hv_vp_set) and
> uses the common definition (hv_vpset) that is used in other places. It
> changes the order of the members in struct hv_pcibus_device due to
> flexible array in
On Fri, Mar 01, 2019 at 12:55:59AM -0800, Andrey Smirnov wrote:
> The clock in question is not present on i.MX7, so move the code
> requesting it into i.MX8MQ-only path.
>
> Fixes: eeb61c4e8530 ("PCI: imx6: Add code to request/control
> "pcie_aux" clock for i.MX8MQ")
> Reported-by: Trent Piepho
On Fri, Feb 01, 2019 at 01:36:05PM +0800, honghui.zh...@mediatek.com wrote:
> From: Honghui Zhang
>
> Two patches:
> patch 1 enable whole MMIO range which also fix the complain of
> scripts/coccinelle/api/resource_size.cocci
> patch 2 enlarge the PCIe2AHB window size to support fully access of
On Fri, Feb 01, 2019 at 01:36:07PM +0800, honghui.zh...@mediatek.com wrote:
> From: Honghui Zhang
>
> The PCIE_AXI_WINDOW0 defines the translate window size for the request
> from EP side. Request outside of this window will be treated as
> unsupported request.
>
> Enlarge this window size from
On Wed, Feb 20, 2019 at 10:03:55PM +0530, Srinath Mannam wrote:
> In the present driver outbound window configuration is done to map above
> 32-bit address I/O regions with corresponding PCI memory range given in
> ranges DT property.
>
> This patch add outbound window configuration to map below
On Thu, Feb 28, 2019 at 06:52:50PM +0800, Ley Foon Tan wrote:
[...]
> +static int s10_tlp_read_packet(struct altera_pcie *pcie, u32 *value)
> +{
> + int i;
> + u32 ctrl;
> + u32 comp_status;
> + u32 dw[4];
> + u32 count;
> +
> + for (i = 0; i < TLP_LOOP; i++) {
> +
On Thu, Feb 28, 2019 at 02:35:06AM +, Maya Nakamura wrote:
> Remove a duplicate definition of VP set (hv_vp_set) and use the common
> definition (hv_vpset) that is used in other places.
>
> Change the order of the members in struct hv_pcibus_device so that the
> declaration of
On Wed, Feb 27, 2019 at 05:51:46PM -0600, Bjorn Helgaas wrote:
> On Wed, Feb 27, 2019 at 3:01 PM Stephen Rothwell
> wrote:
> >
> > Hi Bjorn,
> >
> > Commit
> >
> > a048671aa0c8 ("PCI: qcom: Don't deassert reset GPIO during probe")
> >
> > is missing a Signed-off-by from its committer.
>
>
On Tue, Feb 26, 2019 at 05:15:46PM +0800, Ley Foon Tan wrote:
> Add PCIe Root Port support for Stratix 10 device.
>
> Main differences compare with PCIe Root Port IP on Cyclone V
> and Arria 10 devices:
>
> - HIP interface to access Root Port configuration register.
> - TLP programming flow:
>
On Wed, Feb 27, 2019 at 04:53:37PM +0100, Vitaly Kuznetsov wrote:
> Maya Nakamura writes:
>
> > Remove a duplicate definition of VP set (hv_vp_set) and use the common
> > definition (hv_vpset) that is used in other places.
> >
> > Change the order of the members in struct hv_pcibus_device so
On Wed, Feb 27, 2019 at 01:34:44PM +0100, Vitaly Kuznetsov wrote:
> Maya Nakamura writes:
>
> > Remove the duplicate implementation of cpumask_to_vpset() and use the
> > shared implementation. Export hv_max_vp_index, which is required by
> > cpumask_to_vpset().
> >
> > Apply changes to
On Thu, Feb 21, 2019 at 03:45:12PM +0530, Kishon Vijay Abraham I wrote:
> K2G provides separate IRQ lines for each of the four legacy interrupts.
> Model this using hierarchy domain instead of linear domain with chained
> IRQ handler.
>
> Signed-off-by: Kishon Vijay Abraham I
> ---
>
On Tue, Feb 19, 2019 at 12:02:37PM -0800, Andrey Smirnov wrote:
> Everyone:
>
> This is the series is a spin-off from [imx6-dwc] containing only small
> improvements that I made while reading the code and researching commit
> history of pcie-designware*.c. All changes are optional, so
> commits
On Wed, Feb 20, 2019 at 03:09:01AM +, Xiaowei Bao wrote:
>
>
> -Original Message-
> From: Lorenzo Pieralisi
> Sent: 2019年2月19日 19:27
> To: Xiaowei Bao
> Cc: bhelg...@google.com; robh...@kernel.org; mark.rutl...@arm.com;
> shawn...@kernel.org
Replace Alan Douglas with Tom Joseph as the current PCI
Cadence host/endpoint controller maintainer.
Signed-off-by: Lorenzo Pieralisi
Cc: Bjorn Helgaas
Cc: Tom Joseph
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index
Hi Tom,
the $SUBJECT should be reformatted, please read:
https://www.kernel.org/doc/html/latest/process/submitting-patches.html
Also, while using get_maintainer.pl to derive a sane CC list is good,
it has to be used with some common sense, it is not really needed for
this patch.
There is no
On Thu, Feb 14, 2019 at 11:20:36PM +0800, Ley Foon Tan wrote:
> Add PCIe Root Port support for Stratix 10 device.
>
> Main differences:
Main differences with what ? We need to rewrite this commit log.
> - HIP interface to access Root Port configuration register.
> - TLP programming flow:
> -
On Tue, Feb 19, 2019 at 03:01:39PM +0800, Jianjun Wang wrote:
> On Wed, 2019-01-23 at 15:40 +0000, Lorenzo Pieralisi wrote:
> > On Mon, Dec 24, 2018 at 07:40:28PM +0800, Jianjun Wang wrote:
> > > On Thu, 2018-12-20 at 12:20 -0600, Bjorn Helgaas wrote:
> > > > On T
On Mon, Feb 11, 2019 at 05:51:06PM -0800, Andrey Smirnov wrote:
> Lorenzo:
>
> This small series adds code to control "pcie_aux" clock. This is an
> oversight from original submission [pcie-imx8mq-v7], which was only
> discovered once I submitted an RFC for corresponding DT changes going
> via
On Thu, Feb 14, 2019 at 04:59:04PM -0800, Andrey Smirnov wrote:
[...]
> Lorenzo, can you apply the dwc specific patches that are already
> reviewed by Gustavo Pimentel from this series, to keep things moving
> while we are waiting on Lucas? I can also spin them out into a
> separate series if
On Tue, Jan 22, 2019 at 02:33:27PM +0800, Xiaowei Bao wrote:
> Add the PCIe EP mode support for layerscape platform.
>
> Signed-off-by: Xiaowei Bao
> Reviewed-by: Minghuan Lian
> Reviewed-by: Zhiqiang Hou
> Reviewed-by: Kishon Vijay Abraham I
> ---
> depends on:
On Mon, Feb 18, 2019 at 09:16:03PM -0800, Bjorn Andersson wrote:
> On Wed 13 Feb 07:23 PST 2019, Lorenzo Pieralisi wrote:
>
> > On Fri, Jan 25, 2019 at 03:26:16PM -0800, Bjorn Andersson wrote:
> > > Acquiring the reset GPIO low means that reset is being deasserted, this
>
On Mon, Feb 04, 2019 at 12:13:21PM +, Shameer Kolothum wrote:
> From: Neil Leeder
>
> Add support for the SMMU Performance Monitor Counter Group
> information from ACPI. This is in preparation for its use
> in the SMMUv3 PMU driver.
Also, in case I do not get a chance to update it, please
p; ops->dev_is_coherent(node) ?
> - DEV_DMA_COHERENT : DEV_DMA_NON_COHERENT;
> -
> - /* Configure DMA for the page table walker */
> - acpi_dma_configure(>dev, attr);
> + if (ops->dev_dma_configure)
> + ops->dev_dma_configu
On Mon, Jan 28, 2019 at 11:15:37PM -0800, Maya Nakamura wrote:
> This patchset removes a duplicate definition of VP set (hv_vp_set) and
> uses the common definition (hv_vpset) that is used in other places. It
> changes the order of the members in struct hv_pcibus_device due to
> flexible array in
On Mon, Jan 28, 2019 at 09:49:32PM -0800, Maya Nakamura wrote:
> On Sun, Jan 27, 2019 at 05:11:48AM +, Michael Kelley wrote:
> > From: Maya Nakamura Sent: Saturday, January
> > 26, 2019 12:52 AM
> > >
> > > Remove a duplicate definition of VP set (hv_vp_set) and use the common
> > >
On Thu, Feb 14, 2019 at 04:59:04PM -0800, Andrey Smirnov wrote:
[...]
> > @Lucas: May I ask you to consider please which patches you deem
> > worth for inclusion ? I will have a look too but I would be grateful
> > if the driver maintainers can chime in to help.
> >
>
> Lorenzo, can you apply
On Mon, Jan 14, 2019 at 04:44:58PM +0530, Kishon Vijay Abraham I wrote:
> Hi Lorenzo,
>
> The Endpoint controller driver uses features member in 'struct pci_epc'
> to advertise the list of supported features to the endpoint function
> driver.
>
> There are a few shortcomings with this approach.
On Fri, Feb 15, 2019 at 11:49:12AM +0530, Kishon Vijay Abraham I wrote:
> Hi Lorenzo,
>
> On 14/02/19 9:59 PM, Lorenzo Pieralisi wrote:
> > On Wed, Feb 13, 2019 at 07:17:14PM +0530, Kishon Vijay Abraham I wrote:
> >> Hi Lorenzo,
> >>
> >> On
On Wed, Feb 13, 2019 at 07:17:14PM +0530, Kishon Vijay Abraham I wrote:
> Hi Lorenzo,
>
> On 11/02/19 11:07 PM, Lorenzo Pieralisi wrote:
> > On Mon, Jan 14, 2019 at 04:45:06PM +0530, Kishon Vijay Abraham I wrote:
> >> pci_epf_alloc_space() sets the MEM TYPE flags to ind
[CC'ed MarcZ]
On Thu, Feb 14, 2019 at 10:27:19AM +0530, Kishon Vijay Abraham I wrote:
> Hi Lorenzo,
>
> On 13/02/19 10:27 PM, Lorenzo Pieralisi wrote:
> > On Wed, Feb 13, 2019 at 06:56:23PM +0530, Kishon Vijay Abraham I wrote:
> >> ks_pcie_legacy_irq_handler() uses 'vir
On Wed, Feb 13, 2019 at 06:56:23PM +0530, Kishon Vijay Abraham I wrote:
> ks_pcie_legacy_irq_handler() uses 'virq' to get the IRQ number offset.
> This offset is used to get the correct IRQ_STATUS register
> corresponding to the IRQ line that raised the interrupt.
> There is no guarantee that
On Wed, Feb 13, 2019 at 07:55:39PM +0530, Bharat Kumar Gogada wrote:
> The current Multi MSI data programming fails if a
> end point is connected with switch.
>
> Fix Multi MSI data, by programming data with required alignment.
I have no idea what this means. If you are fixing a bug describe
it
On Fri, Jan 25, 2019 at 03:26:16PM -0800, Bjorn Andersson wrote:
> Acquiring the reset GPIO low means that reset is being deasserted, this
> is followed almost immediately with qcom_pcie_host_init() asserting it,
> initializing it and then finally deasserting it again, for the link to
> come up.
>
On Mon, Jan 28, 2019 at 11:15:37PM -0800, Maya Nakamura wrote:
> This patchset removes a duplicate definition of VP set (hv_vp_set) and
> uses the common definition (hv_vpset) that is used in other places. It
> changes the order of the members in struct hv_pcibus_device due to
> flexible array in
On Wed, Feb 13, 2019 at 07:08:18PM +0530, Kishon Vijay Abraham I wrote:
> Hi Lorenzo,
>
> On 12/02/19 8:37 PM, Lorenzo Pieralisi wrote:
> > On Mon, Jan 07, 2019 at 12:11:44PM +0530, Kishon Vijay Abraham I wrote:
> >
> > [...]
> >
> >> static
On Wed, Feb 13, 2019 at 02:20:29AM +, Michael Kelley wrote:
> From: Lorenzo Pieralisi Sent: Tuesday, February
> 12, 2019 8:35 AM
> >
> > On Mon, Jan 28, 2019 at 09:49:32PM -0800, Maya Nakamura wrote:
> > > On Sun, Jan 27, 2019 at 05:11:48AM +, Michael Kelle
On Wed, Feb 13, 2019 at 10:03:09AM +1100, Stephen Rothwell wrote:
> Hi all,
>
> In commit
>
> 593425276b94 ("PCI: endpoint: functions: Use memcpy_fromio()/memcpy_toio()")
>
> Fixes tag
>
> Fixes: 349e7a85b25f ("PCI: endpoint: functions: Add an EP function to
>
> has these problem(s):
>
>
On Tue, Feb 05, 2019 at 10:27:01AM +0530, Srinath Mannam wrote:
> Add configuration to support IPROC PCIe host controller outbound memory
> window mapping with SOC address range inside 4GB boundary, which is 32 bit
> AXI address.
I do not understand what this means, explain it to me and rewrite
On Tue, Feb 05, 2019 at 10:27:00AM +0530, Srinath Mannam wrote:
> In the current implementation, config read output data 0x0001 is
> assumed as CRS completion. But sometimes 0x0001 can be a valid data.
>
> IPROC PCIe host controller has a register to show config read request
> status
On Mon, Jan 28, 2019 at 09:49:32PM -0800, Maya Nakamura wrote:
> On Sun, Jan 27, 2019 at 05:11:48AM +, Michael Kelley wrote:
> > From: Maya Nakamura Sent: Saturday, January
> > 26, 2019 12:52 AM
> > >
> > > Remove a duplicate definition of VP set (hv_vp_set) and use the common
> > >
On Mon, Jan 07, 2019 at 12:11:44PM +0530, Kishon Vijay Abraham I wrote:
[...]
> static int pci_epf_test_bind(struct pci_epf *epf)
> {
> int ret;
> struct pci_epf_test *epf_test = epf_get_drvdata(epf);
> struct pci_epf_header *header = epf->header;
> + const struct
On Thu, Feb 07, 2019 at 08:36:32PM +, Dexuan Cui wrote:
>
> When we unload pci-hyperv, the host doesn't send us a PCI_EJECT message.
> In this case we also need to make sure the sysfs pci slot directory
> is removed, otherwise "cat /sys/bus/pci/slots/2/address" will trigger
> "BUG: unable to
On Tue, Feb 12, 2019 at 09:54:54AM +0100, Lucas Stach wrote:
> Hi Bjorn,
>
> Am Montag, den 11.02.2019, 15:39 -0600 schrieb Bjorn Helgaas:
> > On Wed, Feb 06, 2019 at 10:57:32AM +0100, Stefan Agner wrote:
> > > Define the length of the DBI registers. This makes sure that
> > > the kernel does not
On Mon, Jan 14, 2019 at 04:45:06PM +0530, Kishon Vijay Abraham I wrote:
> pci_epf_alloc_space() sets the MEM TYPE flags to indicate a 32-bit
> Base Address Register irrespective of the size. Fix it here to indicate
> 64-bit BAR if the size is > 2GB.
>
> Signed-off-by: Kishon Vijay Abraham I
>
On Mon, Feb 11, 2019 at 05:04:00PM +0800, Wen Yang wrote:
> Use the IO memcpy() functions when copying from/to IO memory.
> These locations were found via sparse.
>
> Signed-off-by: Wen Yang
> Suggested-by: Kishon Vijay Abraham I
> CC: Lorenzo Pieralisi
> CC: Bjorn H
Apologies, I have dropped the ball on this one.
On Wed, Jan 02, 2019 at 02:16:48PM +0800, Ley Foon Tan wrote:
> Add PCIe Root Port support for Stratix 10 device.
>
> Main differences:
> - HIP interface to access Root Port configuration register.
> - TLP programming flow:
> - One REG0 register
> CC: Kishon Vijay Abraham I
> CC: Lorenzo Pieralisi
> CC: Bjorn Helgaas
> CC: Gustavo Pimentel
> CC: Niklas Cassel
> CC: Greg Kroah-Hartman
> CC: Cyrille Pitchen
> CC: linux-...@vger.kernel.org (open list:PCI ENDPOINT SUBSYSTEM)
> CC: linux-kernel@vger.kernel.org (open
On Tue, Dec 04, 2018 at 02:27:32PM +0100, Stefan Agner wrote:
> The custom fault handler is currently only meant to handle kernel
> mode bus faults. Exit in case the abort happened in user mode.
>
> Signed-off-by: Stefan Agner
> ---
> drivers/pci/controller/dwc/pci-imx6.c | 10 --
> 1
On Wed, Feb 06, 2019 at 10:57:31AM +0100, Stefan Agner wrote:
> Add length to the struct dw_pcie and check that the accessors
> dw_pcie_(rd|wr)_conf() do not read/write beyond that point.
>
> Suggested-by: Trent Piepho
> Signed-off-by: Stefan Agner
> ---
> Changes in v4:
> - Move length check
On Fri, Feb 08, 2019 at 10:16:59AM +0530, Kishon Vijay Abraham I wrote:
> Hi Lorenzo,
>
> On 07/02/19 10:18 PM, Lorenzo Pieralisi wrote:
> > On Thu, Feb 07, 2019 at 04:39:21PM +0530, Kishon Vijay Abraham I wrote:
> >> Platforms using Designware IP uses dw
On Thu, Feb 07, 2019 at 04:39:21PM +0530, Kishon Vijay Abraham I wrote:
> Platforms using Designware IP uses dw_pci_msi_bottom_irq_chip for
> configuring the MSI controller logic within the Designware IP. However
> certain platforms like Keystone (K2G) which uses Desingware IP has
> it's own MSI
On Thu, Feb 07, 2019 at 04:39:17PM +0530, Kishon Vijay Abraham I wrote:
> The legacy interrupt handler directly checks the IRQ_STATUS register
> corresponding to a interrupt line inorder to invoke generic_handle_irq.
>
> While this is okay for K2G platform which has separate interrupt line for
>
On Thu, Feb 07, 2019 at 04:39:18PM +0530, Kishon Vijay Abraham I wrote:
> ks_pcie_get_irq_controller_info() was used to configure both MSI and
> legacy interrupt. This will prevent MSI or legacy interrupt specific
> intializations. Add separate functions to configure MSI and legacy
> interrupts.
>
On Wed, Feb 06, 2019 at 10:57:31AM +0100, Stefan Agner wrote:
> Add length to the struct dw_pcie and check that the accessors
> dw_pcie_(rd|wr)_conf() do not read/write beyond that point.
>
> Suggested-by: Trent Piepho
> Signed-off-by: Stefan Agner
> ---
> Changes in v4:
> - Move length check
On Tue, Jan 22, 2019 at 02:33:25PM +0800, Xiaowei Bao wrote:
> Add the documentation for the Device Tree binding for the layerscape PCIe
> controller with EP mode.
>
> Signed-off-by: Xiaowei Bao
> Reviewed-by: Minghuan Lian
> Reviewed-by: Zhiqiang Hou
> Reviewed-by: Rob Herring
> ---
> v2:
>
On Tue, Feb 05, 2019 at 11:09:19AM +0530, Subrahmanya Lingappa wrote:
> Reviewed-by: Subrahmanya Lingappa
I have a feeling you do not read what I write. Please never top-post.
Read this, especially the email etiquette section:
https://kernelnewbies.org/PatchCulture
>
>
>
> On Tue, Jan 29,
On Tue, Dec 18, 2018 at 12:02:42PM +, Fabrizio Castro wrote:
> Add PCIe support for the RZ/G2E (a.k.a. R8A774C0).
>
> Signed-off-by: Fabrizio Castro
> Reviewed-by: Geert Uytterhoeven
> ---
> v1->v2:
> * Dropped change to the description of "phys" optional property according
> to Geert's
On Mon, Jan 14, 2019 at 06:54:00PM +0530, Kishon Vijay Abraham I wrote:
> Add PCIe RC support for TI's AM654 SoC. The PCIe controller in AM654
> uses Synopsys core revision 4.90a and uses the same TI wrapper as used
> in keystone2 with certain modification. Hence AM654 will use the same
> pci
lic lists will
reject your emails otherwise) and top-post.
You are supposed to maintain this code, if you can't it is fine but I
should know because there are developers who are waiting for your
review, please understand.
Thanks,
Lorenzo
>Thanks,
>~subbu
>On Tue, Jan 29, 2019
On Thu, Jan 31, 2019 at 10:08:11AM +0100, Stefan Agner wrote:
> On 30.01.2019 18:54, Lorenzo Pieralisi wrote:
> > On Tue, Dec 04, 2018 at 05:55:26PM +0100, Stefan Agner wrote:
> >> Add length to the struct dw_pcie and check that the accessors
> >> dw_pcie_(rd|wr)_conf
On Fri, Feb 01, 2019 at 04:15:19PM -0800, Andrey Smirnov wrote:
> Everyone:
>
> This series contains changes I made in order to enable support of PCIE
> IP block on i.MX8MQ SoCs.
>
> Changes since [v6]:
>
> - Patches rebased on Lorenzo's pci/dwc branch
>
> - Reworded commit message of "PCI:
On Tue, Dec 18, 2018 at 12:02:42PM +, Fabrizio Castro wrote:
> Add PCIe support for the RZ/G2E (a.k.a. R8A774C0).
>
> Signed-off-by: Fabrizio Castro
> Reviewed-by: Geert Uytterhoeven
> ---
> v1->v2:
> * Dropped change to the description of "phys" optional property according
> to Geert's
On Thu, Jan 31, 2019 at 10:08:11AM +0100, Stefan Agner wrote:
> On 30.01.2019 18:54, Lorenzo Pieralisi wrote:
> > On Tue, Dec 04, 2018 at 05:55:26PM +0100, Stefan Agner wrote:
> >> Add length to the struct dw_pcie and check that the accessors
> >> dw_pcie_(rd|wr)_conf
On Thu, Jan 24, 2019 at 12:15:18PM -0800, Andrey Smirnov wrote:
> Everyone:
>
> This series contains changes I made in order to enable support of PCIE
> IP block on i.MX8MQ SoCs.
>
> Changes since [v5]:
>
> - Reformatted commit messages to adhere to
>
>
On Thu, Jan 24, 2019 at 12:15:20PM -0800, Andrey Smirnov wrote:
> PCIE PHY IP block on i.MX7D differs from the one used on i.MX6 family,
> so none of the code in current implementation of imx6_setup_phy_mpll()
> is applicable.
So :) ? Add a conclusive statement to the commit log.
Lorenzo
>
On Fri, Jan 04, 2019 at 09:49:05AM -0800, Andrey Smirnov wrote:
> Everyone:
>
> This is the series containing various small improvements that I made
> while reading the code and researching commit history of pci-imx6.c
> and pcie-designware*.c files. All changes are optional, so commits
> that
On Thu, Jan 24, 2019 at 04:15:37PM +0530, Kishon Vijay Abraham I wrote:
> Certain PHYs used with PCIe controller can also be used with other
> controllers such as USB or SATA. In order to configure the PHY
> to work with PCIe controller, invoke phy_set_mode API with mode
> set to PHY_MODE_PCIE.
>
On Thu, Jan 24, 2019 at 01:59:54PM +0530, Kishon Vijay Abraham I wrote:
> Previous version of the patch series can be found here [1]
>
> Patch series adds support to enable x2 lane mode in dra74/dra76 and
> dra72 based boards in pci-dra7xx driver. It introduces new compatible
> strings in order
On Tue, Dec 04, 2018 at 05:55:26PM +0100, Stefan Agner wrote:
> Add length to the struct dw_pcie and check that the accessors
> dw_pcie_(rd|wr)_conf() do not read/write beyond that point.
>
> Suggested-by: Trent Piepho
> Signed-off-by: Stefan Agner
> ---
> Changes in v4:
> - Move length check
On Wed, Jan 30, 2019 at 09:58:53AM -0600, Bjorn Helgaas wrote:
> On Wed, Jan 30, 2019 at 12:33:47PM +0000, Lorenzo Pieralisi wrote:
> > On Wed, Jan 02, 2019 at 02:03:53PM +0800, honghui.zh...@mediatek.com wrote:
> > > From: Honghui Zhang
> > >
> > > drivers/pc
On Wed, Jan 02, 2019 at 02:03:53PM +0800, honghui.zh...@mediatek.com wrote:
> From: Honghui Zhang
>
> drivers/pci/pcie-mediatek.c:720:13-16: WARNING: Suspicious code.
> resource_size is maybe missing with mem
>
> Generated by: scripts/coccinelle/api/resource_size.cocci
>
> Signed-off-by:
Rob,
Is it OK for you if I pull this series into the pci tree ?
Please let me know, thanks.
Lorenzo
On Mon, Jan 21, 2019 at 05:44:57PM +0800, Xiaowei Bao wrote:
> Add the documentation for the Device Tree binding for the layerscape PCIe
> controller with EP mode.
>
> Signed-off-by: Xiaowei
On Tue, Jan 29, 2019 at 08:08:28AM +, Z.q. Hou wrote:
> From: Hou Zhiqiang
>
> This patch set is aim to refactor the Mobiveil driver and add
> PCIe support for NXP Layerscape series SoCs integrated Mobiveil's
> PCIe Gen4 controller.
>
> Hou Zhiqiang (27):
> PCI: mobiveil: uniform the
On Fri, Jan 25, 2019 at 01:57:57PM +0100, Miquel Raynal wrote:
> Hi Lorenzo,
>
> Lorenzo Pieralisi wrote on Fri, 25 Jan 2019
> 12:40:11 +:
>
> > On Fri, Jan 25, 2019 at 11:05:30AM +0100, Miquel Raynal wrote:
> > > Hi Lorenzo,
> > >
> > &
On Fri, Jan 25, 2019 at 11:05:30AM +0100, Miquel Raynal wrote:
> Hi Lorenzo,
>
> Lorenzo Pieralisi wrote on Wed, 23 Jan 2019
> 17:05:09 +:
>
> > On Tue, Jan 08, 2019 at 05:24:25PM +0100, Miquel Raynal wrote:
> > > Hello,
> > >
> > > As p
On Mon, Jan 07, 2019 at 12:11:33PM +0530, Kishon Vijay Abraham I wrote:
> Hi Lorenzo,
>
> The Endpoint controller driver uses features member in 'struct pci_epc'
> to advertise the list of supported features to the endpoint function
> driver.
>
> There are a few shortcomings with this approach.
On Wed, Dec 19, 2018 at 06:11:59PM +0530, Kishon Vijay Abraham I wrote:
> Instead of creating a new irqchip with empty callback functions, use
> dummy_irq_chip. Since there is nothing to do in the irqchip callback
> functions, use handle_simple_irq instead of handle_level_irq.
>
> Signed-off-by:
On Sat, Jan 12, 2019 at 01:55:57PM -0800, Andrey Smirnov wrote:
> Everyone:
>
> This series contains changes I made in order to enable support of PCIE
> IP block on i.MX8MQ SoCs.
>
> Changes since [v4]:
>
> - Collected Reviewed-by from Lucas
>
> - Replaced ((ARM || ARM64) && COMPILE_TEST)
On Tue, Jan 08, 2019 at 05:24:25PM +0100, Miquel Raynal wrote:
> Hello,
>
> As part of an effort to bring suspend to RAM support to Armada 3700
> SoCs (main target: ESPRESSObin), this series handles the work around
> the PCIe IP.
>
> First, more configuration is done in the 'setup' helper as
On Mon, Dec 24, 2018 at 07:40:28PM +0800, Jianjun Wang wrote:
> On Thu, 2018-12-20 at 12:20 -0600, Bjorn Helgaas wrote:
> > On Tue, Dec 18, 2018 at 05:19:24PM +0800, Jianjun Wang wrote:
> > > On Mon, 2018-12-17 at 15:46 +, Lorenzo Pieralisi wrote:
> > > > On M
On Tue, Dec 25, 2018 at 10:44:38AM +0800, Hanjun Guo wrote:
> Hi Qian,
>
> Good catch, minor comments below.
>
> On 2018/12/25 1:20, Qian Cai wrote:
> > rivers/acpi/arm64/iort.c:880:1: error: expected identifier or '(' before
> > '{' token
> ^^
> drivers
>
> > { return NULL; }
> > ^
> >
On Fri, Jan 04, 2019 at 11:36:26AM +0100, LABBE Corentin wrote:
> On Fri, Jan 04, 2019 at 10:30:25AM +0000, Lorenzo Pieralisi wrote:
> > On Fri, Jan 04, 2019 at 09:08:37AM +, Corentin Labbe wrote:
> > > When building on x86, I got the following build failure:
> >
&g
On Fri, Jan 04, 2019 at 09:08:37AM +, Corentin Labbe wrote:
> When building on x86, I got the following build failure:
Hi,
what tree are you testing on and which config ?
Thanks,
Lorenzo
> drivers/pci/controller/dwc/pci-meson.c: In function ‘meson_pcie_assert_reset’:
>
return 0;
> }
Hi Richard,
the patch is OK with me (even though I have to take for granted how the
IMX MSI logic works), the commit log isn't. So please update it with
Bjorn's version:
https://lore.kernel.org/linux-pci/20181219141241.gb12...@google.com/
*inclusive* of the Fixes: tag.
With the commit log updated as per the link above:
Acked-by: Lorenzo Pieralisi
On Fri, Dec 07, 2018 at 09:53:10AM +0900, Kunihiko Hayashi wrote:
> This series adds PCIe host controller driver for Socionext UniPhier SoCs.
> This controller is based on the DesignWare PCIe core. This driver
> supports LD20 and PXs3 SoCs.
>
> v4:
On Wed, Dec 19, 2018 at 07:13:47PM +0800, Hanjie Lin wrote:
>
>
> On 2018/12/19 6:47, Bjorn Helgaas wrote:
> > On Tue, Dec 18, 2018 at 04:04:46PM +0800, Hanjie Lin wrote:
> >> From: Yue Wang
> >>
> >> The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
> >> PCI core. This
On Thu, Nov 29, 2018 at 06:46:57PM +0100, Ulf Hansson wrote:
> When the hierarchical CPU topology is used and when a CPU has been put
> offline (hotplug), that same CPU prevents its PM domain and thus also
> potential master PM domains, from being powered off. This is because genpd
> observes the
On Tue, Dec 18, 2018 at 05:19:24PM +0800, Jianjun Wang wrote:
> On Mon, 2018-12-17 at 15:46 +0000, Lorenzo Pieralisi wrote:
> > On Mon, Dec 17, 2018 at 08:32:47AM -0600, Bjorn Helgaas wrote:
> > > On Mon, Dec 17, 2018 at 04:19:39PM +0800, Jianjun Wang wrote:
> > > &g
On Fri, Dec 14, 2018 at 09:25:38AM +0800, honghui.zh...@mediatek.com wrote:
> From: Honghui Zhang
>
> The "num-lanes" property in MediaTek's PCIe device node is not used by
> its driver or anyone else, cleanup those related code.
>
> Honghui Zhang (4):
> PCI: mediatek: Remove un-used variant
(parent->type == ACPI_IORT_NODE_SMMU_V3)) {
> pci_request_acs();
> - return true;
> + acs_enabled = true;
> + return;
> }
> }
> }
> -
> - r
On Mon, Dec 17, 2018 at 08:32:47AM -0600, Bjorn Helgaas wrote:
> On Mon, Dec 17, 2018 at 04:19:39PM +0800, Jianjun Wang wrote:
> > On Thu, 2018-12-13 at 08:55 -0600, Bjorn Helgaas wrote:
> > > On Thu, Dec 06, 2018 at 09:09:13AM +0800, Jianjun Wang wrote:
> > > > The read value of BAR0 is
On Sat, Dec 15, 2018 at 01:02:47AM +, Sinan Kaya wrote:
> Remove PCI dependent code out of iort.c when CONFIG_PCI is not defined.
>
> Signed-off-by: Sinan Kaya
> ---
> drivers/acpi/arm64/iort.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/acpi/arm64/iort.c
On Fri, Dec 14, 2018 at 02:38:29PM -0600, Bjorn Helgaas wrote:
> [+cc Trent]
>
> On Thu, Dec 06, 2018 at 12:15:50PM +, Lorenzo Pieralisi wrote:
> > On Wed, Dec 05, 2018 at 11:35:42PM -0800, Andrey Smirnov wrote:
> > > Everyone:
> > >
> > > Th
On Sun, Dec 16, 2018 at 03:09:13PM -0800, Andrey Smirnov wrote:
> Lorenzo:
>
> These are patches fixing things pointed out by Bjorn in [1] and [2] as
> well as something I noticed while giving pci/next branch a try (#endif
> placement). Hopefully this is at least somewhat helpful.
>
> Thanks,
>
On Mon, Dec 17, 2018 at 11:12:58AM +0100, Lucas Stach wrote:
> Am Freitag, den 14.12.2018, 21:25 -0800 schrieb Andrey Smirnov:
> > > On Fri, Dec 14, 2018 at 12:38 PM Bjorn Helgaas wrote:
> > >
> > > [+cc Trent]
> > >
> > > On Thu, Dec 06, 2
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