-1123,7 +1183,7 @@ static int cqspi_setup_flash(struct cqspi_st *cqspi,
> struct device_node *np)
> goto err;
> }
>
> - ret = spi_nor_scan(nor, NULL, SPI_NOR_QUAD);
> + ret = spi_nor_scan(nor, NULL, mode);
> if (ret)
> goto err;
>
> @@ -1277,13 +1337,6 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {
> #define CQSPI_DEV_PM_OPS NULL
> #endif
>
> -static struct of_device_id const cqspi_dt_ids[] = {
> - {.compatible = "cdns,qspi-nor",},
> - { /* end of table */ }
> -};
> -
> -MODULE_DEVICE_TABLE(of, cqspi_dt_ids);
> -
> static struct platform_driver cqspi_platform_driver = {
> .probe = cqspi_probe,
> .remove = cqspi_remove,
>
--
Best regards,
Marek Vasut
On 03/10/2017 01:00 PM, Artur Jedrysek wrote:
>
> From: Marek Vasut [mailto:marek.va...@gmail.com]
> Sent: 10 March 2017 04:37
>> On 03/08/2017 09:02 AM, Artur Jedrysek wrote:
>>> Recent versions of Cadence QSPI controller support Octal SPI transfers
>>> as
ust block size (512) at some other calling side.
>
> (Sorry for previous same content email, just found out it's html
> format and rejected by mail list)
>
> On Mon, Feb 27, 2017 at 1:31 AM, Marek Vasut <marek.va...@gmail.com> wrote:
>> On 02/22/2017 03:15 AM, Lepto
On 03/10/2017 01:03 PM, Artur Jedrysek wrote:
>
>> From: Marek Vasut [mailto:marek.va...@gmail.com]
>> Sent: 10 March 2017 04:39
>> On 03/08/2017 09:05 AM, Artur Jedrysek wrote:
>>> This patch updates Cadence QSPI Device Tree documentation to include
>>>
>
> Quad-SPI controller can always support single, dual and quad. There was
> no option to configure max mode. Octal-SPI controller can be configured
> to support either octal or quad mode. No controller could be configured
> (during hardware compilation/synthesis) to support only single/dual
> SPI mode. To put it shortly: single, dual and quad is always supported.
So basically the whole check you need to perform here is
mode = quad;
if (controller->flags & CAN_DO_OCTAL) {
if (readl(ID_REGISTER) & IS_CONFIGURED_AS_OCTAL)
mode = octal;
}
--
Best regards,
Marek Vasut
err = spi_nor_select_pp(nor, params, shared_mask);
> + if (err) {
> + dev_err(nor->dev, "invalid page program\n");
> + return err;
> + }
> +
> + /* Select the Sector Erase command. */
> + err = spi_nor_select_erase(nor, info);
> + if (err) {
> + dev_err(nor->dev, "invalid sector/block erase\n");
> + return err;
> + }
> +
> + /* Enable Quad I/O if needed. */
> + enable_quad_io = (spi_nor_get_protocol_width(nor->read_proto) == 4 ||
> + spi_nor_get_protocol_width(nor->write_proto) == 4);
What if read_proto != write_proto ? Also, this is awful code ... fix it.
> + if (enable_quad_io && params->quad_enable)
> + nor->flash_quad_enable = params->quad_enable;
> + else
> + nor->flash_quad_enable = NULL;
> +
> + return 0;
> +}
> +
> +int spi_nor_scan(struct spi_nor *nor, const char *name,
> + const struct spi_nor_hwcaps *hwcaps)
> +{
> + struct spi_nor_flash_parameter params;
> const struct flash_info *info = NULL;
> struct device *dev = nor->dev;
> struct mtd_info *mtd = >mtd;
> @@ -1548,6 +1824,11 @@ int spi_nor_scan(struct spi_nor *nor, const char
> *name, enum read_mode mode)
> if (ret)
> return ret;
>
> + /* Reset SPI protocol for all commands */
> + nor->reg_proto = SNOR_PROTO_1_1_1;
> + nor->read_proto = SNOR_PROTO_1_1_1;
> + nor->write_proto = SNOR_PROTO_1_1_1;
> +
> if (name)
> info = spi_nor_match_id(name);
> /* Try to auto-detect if chip name wasn't specified or not found */
[...]
--
Best regards,
Marek Vasut
e *spi)
> spi_set_drvdata(spi, flash);
> flash->spi = spi;
>
> - if (spi->mode & SPI_RX_QUAD)
> + if (spi->mode & SPI_RX_QUAD) {
> hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
> - else if (spi->mode & SPI_RX_DUAL)
> +
> + if (spi->mode & SPI_TX_QUAD)
> + hwcaps.mask |= (SNOR_HWCAPS_READ_1_4_4 |
> + SNOR_HWCAPS_PP_1_1_4 |
> + SNOR_HWCAPS_PP_1_4_4);
> + } else if (spi->mode & SPI_RX_DUAL) {
> hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
>
> + if (spi->mode & SPI_TX_DUAL)
> + hwcaps.mask |= SNOR_HWCAPS_READ_1_2_2;
> + }
> +
> if (data && data->name)
> nor->mtd.name = data->name;
>
>
--
Best regards,
Marek Vasut
25 the smallest value ? Use a macro for this ...
> + flash->fsize = 25;
> +
> + ret = spi_nor_scan(>nor, NULL, flash_read);
> + if (ret) {
> + dev_err(qspi->dev, "device scan failed\n");
> + return ret;
> + }
> +
> + /* number of bytes in Flash memory = 2^[FSIZE+1] */
> + flash->fsize = __fls(mtd->size) - 1;
> +
> + writel_relaxed(DCR_CSHT(1), qspi->io_base + QUADSPI_DCR);
> +
> + ret = mtd_device_register(mtd, NULL, 0);
> + if (ret) {
> + dev_err(qspi->dev, "mtd device parse failed\n");
> + return ret;
> + }
> +
> + dev_dbg(qspi->dev, "read mm:%s cs:%d bus:%d\n",
> + qspi->read_mode == CCR_FMODE_MM ? "yes" : "no", cs_num, width);
> +
> + return 0;
> +}
[...]
--
Best regards,
Marek Vasut
cphe...@gmail.com
> Cc: David Woodhouse <dw...@infradead.org>
> Cc: Brian Norris <computersforpe...@gmail.com>
> Cc: Boris Brezillon <boris.brezil...@free-electrons.com>
> Cc: Marek Vasut <marek.va...@gmail.com>
> Cc: Richard Weinberger <rich...@nod.at>
On 04/18/2017 04:21 PM, Andrey Smirnov wrote:
> Replace C99 type with their kernel counterparts as per request from
> Marek Vasut.
>
> No functional change intended.
>
> Cc: cphe...@gmail.com
> Cc: David Woodhouse <dw...@infradead.org>
> Cc: Brian Norris <compute
On 04/18/2017 04:21 PM, Andrey Smirnov wrote:
> As per request from Marek Vasut, change the following:
Does that really have to be in the commit message ? ^_^'
>- Replace indentation between type and name of local variable from
> tabs to spaces
>
>- Replace ma
On 04/18/2017 07:57 PM, Mark Brown wrote:
> On Sun, Apr 16, 2017 at 08:08:01PM +0200, Marek Vasut wrote:
>
> This looks good, a couple of minor things though:
>
>> +static int bd9571mwv_regulator_is_enabled(struct regulator_dev *reg)
>> +{
>> +/* Alway
On 04/19/2017 12:36 AM, Joe Perches wrote:
> On Tue, 2017-04-18 at 20:25 +0200, Marek Vasut wrote:
>> On 04/18/2017 04:21 PM, Andrey Smirnov wrote:
>>> As per request from Marek Vasut, change the following:
>>
>> Does that really have to be in the commit mess
can't say I'm a big fan on this re-numeration when you add a new
entry. But unless you have a better idea, we'll have to live with this ...
--
Best regards,
Marek Vasut
ather introduce the Octo SPI protocols now so it's done as it
> should be.
>
> Signed-off-by: Cyrille Pitchen <cyrille.pitc...@atmel.com>
Reviewed-by: Marek Vasut <marek.va...@gmail.com>
--
Best regards,
Marek Vasut
gt; + return ((u32)(proto & SNOR_PROTO_DATA_MASK)) >> SNOR_PROTO_DATA_SHIFT;
> +}
> +
> +static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
> +{
> + return spi_nor_get_protocol_data_nbits(proto);
> +}
[...]
Looks good otherwise.
--
Best regards,
Marek Vasut
On 04/19/2017 04:58 AM, Andrey Smirnov wrote:
> On Tue, Apr 18, 2017 at 11:31 AM, Marek Vasut <marek.va...@gmail.com> wrote:
>> On 04/18/2017 04:21 PM, Andrey Smirnov wrote:
>>> In anticipation of supporting chips that need it, extend the size of
>>> struct flas
= MODE_IO_X1;
> + aspi->xfer_mode_addr = MODE_IO_X1;
> + aspi->xfer_mode_data = MODE_IO_X1;
> + break;
> + case SPI_NOR_FAST:
> + aspi->num_hi_z_clocks = nor->read_dummy;
> + aspi->xfer_mode_cmd = MODE_IO_X1;
> + aspi->xfer_mode_addr = MODE_IO_X1;
> + aspi->xfer_mode_data = MODE_IO_X1;
> + break;
> + case SPI_NOR_DUAL:
> + aspi->num_hi_z_clocks = nor->read_dummy;
> + aspi->xfer_mode_cmd = MODE_IO_X1;
> + aspi->xfer_mode_addr = MODE_IO_X1;
> + aspi->xfer_mode_data = MODE_IO_X2;
> + break;
> + case SPI_NOR_QUAD:
> + aspi->num_hi_z_clocks = nor->read_dummy;
> + aspi->xfer_mode_cmd = MODE_IO_X1;
> + aspi->xfer_mode_addr = MODE_IO_X1;
> + aspi->xfer_mode_data = MODE_IO_X4;
> + break;
> + }
> +
> + aspi_setup_xip_read_chain(aspi, nor);
> +
> + mtd_device_register(>nor.mtd, NULL, 0);
> +
> + return 0;
> +}
> +
> +static int anarion_qspi_drv_remove(struct platform_device *pdev)
> +{
> + struct anarion_qspi *aspi = platform_get_drvdata(pdev);
> +
> + mtd_device_unregister(>nor.mtd);
> + return 0;
> +}
> +
> +static const struct of_device_id anarion_qspi_of_match[] = {
> + { .compatible = "adaptrum,anarion-qspi" },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, anarion_qspi_of_match);
> +
> +static struct platform_driver anarion_qspi_driver = {
> + .driver = {
> + .name = "anarion-qspi",
> + .of_match_table = anarion_qspi_of_match,
> + },
> + .probe = anarion_qspi_drv_probe,
> + .remove = anarion_qspi_drv_remove,
> +};
> +module_platform_driver(anarion_qspi_driver);
> +
> +MODULE_DESCRIPTION("Adaptrum Anarion Quad SPI Controller Driver");
> +MODULE_AUTHOR("Alexandru Gagniuc <mr.nuke...@gmail.com>");
> +MODULE_LICENSE("GPL v2");
>
--
Best regards,
Marek Vasut
On 07/18/2017 11:23 AM, Lee Jones wrote:
> On Mon, 17 Jul 2017, Marek Vasut wrote:
>
>> Add the MFD part of the ROHM BD9571MWV-M PMIC driver and MAINTAINERS
>> entry. The MFD part only specifies the regmap bits for the PMIC and
>> binds the subdevs together.
>>
On 07/10/2017 05:33 PM, Geert Uytterhoeven wrote:
> Hi Marek,
>
> On Tue, May 2, 2017 at 2:18 PM, Marek Vasut <marek.va...@gmail.com> wrote:
>> Add the MFD part of the ROHM BD9571MWV-M PMIC driver and MAINTAINERS
>> entry. The MFD part only specifies the regmap bit
Add the MFD part of the ROHM BD9571MWV-M PMIC driver and MAINTAINERS
entry. The MFD part only specifies the regmap bits for the PMIC and
binds the subdevs together.
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: linux-kernel@vger.kernel.org
Cc: Geert Uytterhoeven <g
ot happen,
> because this is DT-only driver, and without a valid match in
> vf610_nfc_dt_ids the dev wouldn't have been probed in the first place.
>
> I'll let Stefan decide whether he wants it or not, but I see no real
> reason for this extra check.
So how did you trigger the issue in the first place ?
--
Best regards,
Marek Vasut
(four universal clock outputs and one reference clock output at
> OUT0_SELB_I2C).
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov+rene...@cogentembedded.com>
Reviewed-by: Marek Vasut <marek.va...@gmail.com>
> ---
> drivers/clk/clk-versaclock5.c | 11 +
- 5p49v5923: (required) either or both of "xin", "clkin".
> + - 5p49v5923 and
> + - 5p49v5925: (required) either or both of "xin", "clkin".
> - 5p49v5933 and
> - 5p49v5935: (optional) property not present or "clkin".
>
> @@ -37,6 +39,7 @@ clock specifier, the following mapping applies:
> 1 -- OUT1
> 2 -- OUT4
>
> +5P49V5925 and
> 5P49V5935:
> 0 -- OUT0_SEL_I2CB
> 1 -- OUT1
>
--
Best regards,
Marek Vasut
On 07/09/2017 07:38 PM, Vladimir Barinov wrote:
> On 09.07.2017 16:31, Marek Vasut wrote:
>> On 07/07/2017 03:57 AM, Vladimir Barinov wrote:
>>> From: Vladimir Barinov <vladimir.barinov+rene...@cogentembedded.com>
>>>
>>> IDT VersaClock 5 5P49V5925 has 4
Signed-off-by: Vladimir Barinov <vladimir.barinov+rene...@cogentembedded.com>
Reviewed-by: Marek Vasut <marek.va...@gmail.com>
> ---
> Changes in version 2:
> - fixed typo in patch header: VC5 has 5 clock outputs
> - rebased against patch:
> [V3,7/8] clk: vc5: Add bindin
On 06/29/2017 05:03 PM, matthew.gerl...@linux.intel.com wrote:
>
>
> On Thu, 29 Jun 2017, Marek Vasut wrote:
>
>> On 06/29/2017 01:09 AM, Rob Herring wrote:
>>> On Tue, Jun 27, 2017 at 08:57:14AM -0700,
>>> matthew.gerl...@linux.intel.com wrote:
>>>
On 07/03/2017 01:55 PM, Lee Jones wrote:
> On Tue, 27 Jun 2017, Marek Vasut wrote:
>
>> On 05/02/2017 02:18 PM, Marek Vasut wrote:
>>> Add the MFD part of the ROHM BD9571MWV-M PMIC driver and MAINTAINERS
>>> entry. The MFD part only specifies the regmap bits for the
On 07/03/2017 03:48 PM, Lee Jones wrote:
> On Mon, 03 Jul 2017, Marek Vasut wrote:
>
>> On 07/03/2017 01:55 PM, Lee Jones wrote:
>>> On Tue, 27 Jun 2017, Marek Vasut wrote:
>>>
>>>> On 05/02/2017 02:18 PM, Marek Vasut wrote:
>>>>
On 06/27/2017 09:48 PM, Cyrille Pitchen wrote:
> Le 27/06/2017 à 18:11, Marek Vasut a écrit :
>> On 06/27/2017 05:34 PM, Arnd Bergmann wrote:
>>> The variable was already marked 'const' before the previous
>>> patch, but the qualifier was in an unusual place, and now t
ANDC_ECC_MODES (ECC_RS_4BIT | ECC_BCH_8BIT)
>
> +static const struct qcom_nand_driver_data ebi2_nandc_data = {
> + .ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
> + .dma_bam_enabled = false,
> +};
> +
> +static const struct qcom_nand_driver_data qpic_nandc_v1_4_0_data = {
> + .ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
> + .dma_bam_enabled = true,
> +};
> /*
> * data will hold a struct pointer containing more differences once we
> support
> * more controller variants
> */
> static const struct of_device_id qcom_nandc_of_match[] = {
> { .compatible = "qcom,ipq806x-nand",
> - .data = (void *)EBI2_NANDC_ECC_MODES,
> + .data = (void *)_nandc_data,
> + },
> + { .compatible = "qcom,qpic-nandc-v1.4.0",
> + .data = (void *)_nandc_v1_4_0_data,
> },
> {}
> };
>
--
Best regards,
Marek Vasut
On 06/29/2017 01:09 AM, Rob Herring wrote:
> On Tue, Jun 27, 2017 at 08:57:14AM -0700, matthew.gerl...@linux.intel.com
> wrote:
>>
>>
>> On Tue, 27 Jun 2017, Marek Vasut wrote:
>>
>>> On 06/27/2017 04:32 PM, matthew.gerl...@linux.intel.com wrote:
>>
abled << ECC_CFG_ECC_DISABLE
> + host->ecc_bch_cfg = !host->bch_enabled << ECC_CFG_ECC_DISABLE
> | 0 << ECC_SW_RESET
> | host->cw_data << ECC_NUM_DATA_BYTES
> | 1 << ECC_FORCE_CLK_OPEN
>
--
Best regards,
Marek Vasut
uf, oob_size2);
> + write_data_dma(nandc, reg_off, oob_buf, oob_size2, 0);
> oob_buf += oob_size2;
>
> config_cw_write_post(nandc);
> @@ -1685,7 +1700,7 @@ static int qcom_nandc_write_oob(struct mtd_info *mtd,
> struct nand_chip *chip,
>
> config_cw_write_pre(nandc);
> write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
> -data_size + oob_size);
> +data_size + oob_size, 0);
> config_cw_write_post(nandc);
>
> ret = submit_descs(nandc);
> @@ -1769,7 +1784,8 @@ static int qcom_nandc_block_markbad(struct mtd_info
> *mtd, loff_t ofs)
> update_rw_regs(host, 1, false);
>
> config_cw_write_pre(nandc);
> - write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, host->cw_size);
> + write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
> +host->cw_size, 0);
> config_cw_write_post(nandc);
>
> ret = submit_descs(nandc);
>
--
Best regards,
Marek Vasut
return -ENOMEM;
> + }
> }
>
> INIT_LIST_HEAD(>desc_list);
> @@ -2153,6 +2258,17 @@ static int qcom_probe_nand_devices(struct
> qcom_nand_controller *nandc)
> if (list_empty(>host_list))
> return -ENODEV;
>
> + if (nandc->dma_bam_enabled) {
> + free_bam_transaction(nandc);
> + nandc->bam_txn = alloc_bam_transaction(nandc,
> +nandc->max_cwperpage);
> + if (!nandc->bam_txn) {
> + dev_err(nandc->dev,
> + "failed to allocate bam transaction\n");
> + return -ENOMEM;
> + }
> + }
> +
> list_for_each_entry_safe(host, tmp, >host_list, node) {
> ret = qcom_nand_mtd_register(nandc, host, child);
> if (ret) {
>
--
Best regards,
Marek Vasut
> + ret = of_property_read_u32(np, "qcom,cmd-crci",
> +>cmd_crci);
> + if (ret) {
> + dev_err(nandc->dev, "command CRCI unspecified\n");
> + return ret;
> + }
>
> - ret = of_property_read_u32(np, "qcom,data-crci", >data_crci);
> - if (ret) {
> - dev_err(nandc->dev, "data CRCI unspecified\n");
> - return ret;
> + ret = of_property_read_u32(np, "qcom,data-crci",
> +>data_crci);
> + if (ret) {
> + dev_err(nandc->dev, "data CRCI unspecified\n");
> + return ret;
> + }
> }
>
> return 0;
> @@ -2128,7 +2188,7 @@ static int qcom_nandc_probe(struct platform_device
> *pdev)
>
> ret = qcom_nandc_alloc(nandc);
> if (ret)
> - return ret;
> + goto err_core_clk;
>
> ret = clk_prepare_enable(nandc->core_clk);
> if (ret)
>
Can you please fix your mailer to stop adding "QUALCOMM INDIA, on behalf
of Qualcomm Innovation Center"... stuff at the bottom of the patches ?
--
Best regards,
Marek Vasut
On 06/27/2017 10:21 PM, Cyrille Pitchen wrote:
> Le 27/06/2017 à 21:51, Marek Vasut a écrit :
>> On 06/27/2017 09:48 PM, Cyrille Pitchen wrote:
>>> Le 27/06/2017 à 18:11, Marek Vasut a écrit :
>>>> On 06/27/2017 05:34 PM, Arnd Bergmann wrote:
>>>>> T
oks at the data
>>>>> from one
>>>>> perspective on power up, and a processor trying to update the flash
>>>>> has
>>>>> a different perspective.
>>>>
>>>> Another thing I'd ask here is, is that bit-reverse a hardware property
>>>> or is that some software configuration thing ?
>>>
>>> I would say the bit reversal is a property of the FPGA that is reading
>>> the flash at power up.
>>
>> So it's not a property of the block, but rather of the bus somewhere ?
>
> You are correct, it is not a property of the Altera Quadspi component, but
> a property of the fpga and external hardware that access the flash on
> power up.
So yes, it's a property of that small thing which loads the bitstream
from the EPCS/EPCQ and programs the cells in the FPGA. This shouldn't be
in this driver nor it's bindings, see above.
--
Best regards,
Marek Vasut
On 04/26/2017 12:31 AM, Mark Brown wrote:
> On Tue, Apr 25, 2017 at 08:32:10PM +0200, Marek Vasut wrote:
>> Add driver for the regulator block in the ROHM BD9571MWV-W MFD PMIC.
>> This block supports three voltage monitors, VD18, VD25, VD33 for the
>> 1V8, 2V5, 3V3 volta
it
> will result in the minimum voltage on VDD_ARM_SOC_IN rather than a fix
> 1375mv. I tested Marek's patch and it works fine on my rev B board
> (which otherwise fails to boot upstream).
Oh that's nice , thanks ! I don't have SDB and I hacked it up after a
brief discussion with Fabio without even compile-testing it, thus RFC.
Glad to hear it works and thanks for testing it ! Can you add a formal
Tested-by please ?
--
Best regards,
Marek Vasut
Add the MFD part of the ROHM BD9571MWV-M PMIC driver and MAINTAINERS
entry. The MFD part only specifies the regmap bits for the PMIC and
binds the subdevs together.
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: linux-kernel@vger.kernel.org
Cc: Geert Uytterhoeven <g
Add driver for the regulator block in the ROHM BD9571MWV-W MFD PMIC.
This block supports three voltage monitors, VD18, VD25, VD33 for the
1V8, 2V5, 3V3 voltage rails and a single voltage regulator for the
DVFS rail.
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: linux-
s supported by both the (Q)SPI memory and
> controller hence selecting the relevant settings for (Fast) Read and Page
> Program operations.
>
> Signed-off-by: Cyrille Pitchen <cyrille.pitc...@atmel.com>
Reviewed-by: Marek Vasut <marek.va...@gmail.com>
[...]
--
Best regards,
Marek Vasut
atever the number of I/O lines
> used during instruction (x) and address/mode/dummy (y) clock cycles, DTR
> is used only during data (z) clock cycles of SPI x-y-z protocols.
>
> Signed-off-by: Cyrille Pitchen <cyrille.pitc...@atmel.com>
Reviewed-by: Marek Vasut <marek.va...@gmail.com>
--
Best regards,
Marek Vasut
On 04/24/2017 01:38 PM, Lee Jones wrote:
> On Sun, 16 Apr 2017, Marek Vasut wrote:
[...]
>> +static int bd9571mwv_identify(struct bd9571mwv *bd)
>> +{
>> +struct device *dev = bd->dev;
>> +unsigned int value;
>> +int ret;
>&
Add the MFD part of the ROHM BD9571MWV-M PMIC driver and MAINTAINERS
entry. The MFD part only specifies the regmap bits for the PMIC and
binds the subdevs together.
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: linux-kernel@vger.kernel.org
Cc: Geert Uytterhoeven <g
Add driver for the regulator block in the ROHM BD9571MWV-W MFD PMIC.
This block supports three voltage monitors, VD18, VD25, VD33 for the
1V8, 2V5, 3V3 voltage rails and a single voltage regulator for the
DVFS rail.
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: linux-
mode_cmd = MODE_IO_X1;
>>> +aspi->xfer_mode_addr = MODE_IO_X1;
>>> +aspi->xfer_mode_data = MODE_IO_X1;
>>> +break;
>>> +case SPI_NOR_FAST:
>>> +aspi->num_hi_z_clocks = nor->read_dummy;
>>> +aspi->xfer_mode_cmd = MODE_IO_X1;
>>> +aspi->xfer_mode_addr = MODE_IO_X1;
>>> +aspi->xfer_mode_data = MODE_IO_X1;
>>> +break;
>>> +case SPI_NOR_DUAL:
>>> +aspi->num_hi_z_clocks = nor->read_dummy;
>>> +aspi->xfer_mode_cmd = MODE_IO_X1;
>>> +aspi->xfer_mode_addr = MODE_IO_X1;
>>> +aspi->xfer_mode_data = MODE_IO_X2;
>>> +break;
>>> +case SPI_NOR_QUAD:
>>> +aspi->num_hi_z_clocks = nor->read_dummy;
>>> +aspi->xfer_mode_cmd = MODE_IO_X1;
>>> +aspi->xfer_mode_addr = MODE_IO_X1;
>>> +aspi->xfer_mode_data = MODE_IO_X4;
>>> +break;
>>> +}
>>> +
>>> +aspi_setup_xip_read_chain(aspi, nor);
>>> +
>>> +mtd_device_register(>nor.mtd, NULL, 0);
>>> +
>>> +return 0;
>>> +}
>
> [snip]
--
Best regards,
Marek Vasut
On 07/31/2017 10:54 PM, Alexandru Gagniuc wrote:
> Hi Marek,
>
> Me again!
>
> On 07/29/2017 02:34 AM, Marek Vasut wrote:
>> On 07/29/2017 12:07 AM, Alexandru Gagniuc wrote:
>>> +static void aspi_drain_fifo(struct anarion_qspi *aspi, uint8_t *buf,
>>> si
On 08/01/2017 12:20 AM, Alexandru Gagniuc wrote:
> On 07/31/2017 02:33 PM, Marek Vasut wrote:
>> On 07/31/2017 07:17 PM, Alexandru Gagniuc wrote:
>
> Hi Marek,
>
> Thank you again for your feedback. I've applied a majority of your
> suggestions, and I am very happy with t
%d\n", irq);
"Cannot obtain IRQ, ret=%i\n" please . It's inobvious what the value
means otherwise.
> + return irq;
> }
>
> ret = clk_prepare_enable(cqspi->clk);
>
--
Best regards,
Marek Vasut
}
> + }
> +
> + return 0;
> +error:
> + altera_asmip2_remove_banks(dev);
> + return -EIO;
> +}
> +
> +static int altera_asmip2_remove(struct platform_device *pdev)
> +{
> + if (!pdev) {
> + dev_err(>dev, "%s NULL\n", __func__);
> + return -EINVAL;
Can this really happen ?
> + } else {
> + return altera_asmip2_remove_banks(>dev);
> + }
> +}
> +
> +static const struct of_device_id altera_asmip2_id_table[] = {
> +
> + { .compatible = "altr,asmi_parallel2",},
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, altera_asmip2_id_table);
> +
> +static struct platform_driver altera_asmip2_driver = {
> + .driver = {
> + .name = ALTERA_ASMIP2_DRV_NAME,
> + .of_match_table = altera_asmip2_id_table,
> + },
> + .probe = altera_asmip2_probe,
> + .remove = altera_asmip2_remove,
> +};
> +module_platform_driver(altera_asmip2_driver);
> +
> +MODULE_AUTHOR("Matthew Gerlach <matthew.gerl...@linux.intel.com>");
> +MODULE_DESCRIPTION("Altera ASMI Parallel II");
> +MODULE_LICENSE("GPL v2");
> +MODULE_ALIAS("platform:" ALTERA_ASMIP2_DRV_NAME);
> diff --git a/include/linux/mtd/altera-asmip2.h
> b/include/linux/mtd/altera-asmip2.h
> new file mode 100644
> index 000..580c43c
> --- /dev/null
> +++ b/include/linux/mtd/altera-asmip2.h
> @@ -0,0 +1,24 @@
> +/*
> + *
> + * Copyright 2017 Intel Corporation, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +#ifndef __ALTERA_QUADSPI_H
> +#define __ALTERA_QUADSPI_H
> +
> +#include
> +
> +#define ALTERA_ASMIP2_DRV_NAME "altr-asmip2"
> +#define ALTERA_ASMIP2_MAX_NUM_FLASH_CHIP 3
> +#define ALTERA_ASMIP2_RESOURCE_SIZE 0x10
> +
> +struct altera_asmip2_plat_data {
> + void __iomem *csr_base;
> + u32 num_chip_sel;
> +};
> +
> +#endif
>
--
Best regards,
Marek Vasut
On 05/03/2017 04:58 PM, Leonard Crestez wrote:
> On Wed, 2017-05-03 at 16:26 +0200, Marek Vasut wrote:
>
>> On 05/03/2017 03:57 PM, Shawn Guo wrote:
>>>
>>> On Tue, Apr 25, 2017 at 07:28:06PM +0200, Marek Vasut wrote:
>>>>
>>>> On 04/25/20
On 05/03/2017 04:41 PM, Shawn Guo wrote:
> On Wed, May 03, 2017 at 04:32:06PM +0200, Marek Vasut wrote:
>> On 05/03/2017 04:26 PM, Marek Vasut wrote:
>>> On 05/03/2017 03:57 PM, Shawn Guo wrote:
>>>> On Tue, Apr 25, 2017 at 07:28:06PM +0200, Marek Vasut wrote:
>>
On 05/03/2017 04:26 PM, Marek Vasut wrote:
> On 05/03/2017 03:57 PM, Shawn Guo wrote:
>> On Tue, Apr 25, 2017 at 07:28:06PM +0200, Marek Vasut wrote:
>>> On 04/25/2017 07:23 PM, Leonard Crestez wrote:
>>>> Anyway, that version also sets the supply for reg_arm and reg
On 05/03/2017 03:57 PM, Shawn Guo wrote:
> On Tue, Apr 25, 2017 at 07:28:06PM +0200, Marek Vasut wrote:
>> On 04/25/2017 07:23 PM, Leonard Crestez wrote:
>>> Anyway, that version also sets the supply for reg_arm and reg_soc. It
>>> is not necessary for fixing the c
On 05/03/2017 07:58 PM, Leonard Crestez wrote:
> On Wed, 2017-05-03 at 17:59 +0200, Marek Vasut wrote:
>> On 05/03/2017 04:58 PM, Leonard Crestez wrote:
>>> On Wed, 2017-05-03 at 16:26 +0200, Marek Vasut wrote:
>>>> 2) It actually fixes a problem with the vo
t of_device_id const cqspi_dt_ids[] = {
> +static const struct of_device_id cqspi_dt_ids[] = {
> {.compatible = "cdns,qspi-nor",},
> { /* end of table */ }
> };
>
--
Best regards,
Marek Vasut
On 06/27/2017 04:32 PM, matthew.gerl...@linux.intel.com wrote:
>
>
> On Tue, 27 Jun 2017, Marek Vasut wrote:
>
> Hi Marek,
>
> Thanks for the feedback. See my comments below.
>
> Matthew Gerlach
>
>> On 06/26/2017 06:13 PM, matthew.gerl...@linux.intel.
e, void __iomem *window_reg,
>>> + size_t window_size, u32 flags);
>>> +
>>> +int altera_qspi_add_bank(struct device *dev,
>>> + u32 bank, struct device_node *np);
>>> +
>>> +int altera_quadspi_remove_banks(struct device *dev);
>>
>> Why is this header needed at all ?
>
> This header is needed because of the very different ways
> FPGAs can be used with a processor running Linux. In the case of a
> soft processor in the FPGA or an ARM connected to a FPGA, this header
> is not necessary because device trees are used to probe the driver.
> However, if the FPGA is on a PCIe card connected to an x86, device trees
> are not generally used, and the pcie driver must enumerate the
> "sub-driver".
But we don't support that later part, do we ?
--
Best regards,
Marek Vasut
On 06/27/2017 05:57 PM, matthew.gerl...@linux.intel.com wrote:
>
>
> On Tue, 27 Jun 2017, Marek Vasut wrote:
>
>> On 06/27/2017 04:32 PM, matthew.gerl...@linux.intel.com wrote:
>>>
>>>
>>> On Tue, 27 Jun 2017, Marek Vasut wrote:
>>>
On 06/27/2017 05:15 PM, matthew.gerl...@linux.intel.com wrote:
>
>
> On Tue, 27 Jun 2017, Marek Vasut wrote:
>
>> On 06/26/2017 06:13 PM, matthew.gerl...@linux.intel.com wrote:
>>> From: Matthew Gerlach <matthew.gerl...@linux.intel.com>
>>
>> Just
On 06/27/2017 07:18 PM, matthew.gerl...@linux.intel.com wrote:
>
>
> On Tue, 27 Jun 2017, Marek Vasut wrote:
>
>> On 06/27/2017 05:57 PM, matthew.gerl...@linux.intel.com wrote:
>>>
>>>
>>> On Tue, 27 Jun 2017, Marek Vasut wrote:
>>>
>&g
of the Altera Quadspi
> controller.
It'd be real nice to mention that in the cover letter with a link to
that patchset , otherwise it's real hard to understand why you did this.
> This technique of separating core driver code from platform/device tree
> code has been reviewed and accepted for the Altera Partial
> Reconfiguration IP, Altera Freeze Bridge, and the fpga region.
--
Best regards,
Marek Vasut
On 05/28/2017 08:02 AM, Axel Lin wrote:
> These functions are only used by this driver, make them static.
>
> Signed-off-by: Axel Lin <axel@ingics.com>
Obviously correct,
Acked-by: Marek Vasut <marek.va...@gmail.com>
> ---
> drivers/regulator/bd9571mwv-regulat
On 06/13/2017 09:46 PM, Cyrille Pitchen wrote:
> SPI NOR branches are now hosted on MTD repos, spi-nor/next is on l2-mtd
> and spi-nor/fixes is on linux-mtd.
>
> Signed-off-by: Cyrille Pitchen <cyrille.pitc...@wedev4u.fr>
Excellent.
Acked-by: Marek Vasut <
sfdp(nor, _params)) {
> + nor->addr_width = 0;
> + nor->mtd.erasesize = 0;
> + } else {
> + memcpy(params, _params, sizeof(*params));
> + }
> + }
> +
> return 0;
> }
>
> @@ -1757,6 +2337,10 @@ static int spi_nor_select_erase(struct spi_nor *nor,
> {
> struct mtd_info *mtd = >mtd;
>
> + /* Do nothing if already configured from SFDP. */
> + if (mtd->erasesize)
> + return 0;
> +
> #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
> /* prefer "small sector" erase if possible */
> if (info->flags & SECT_4K) {
> @@ -1989,9 +2573,11 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
> if (ret)
> return ret;
>
> - if (info->addr_width)
> + if (nor->addr_width) {
> + /* already configured by spi_nor_setup() */
> + } else if (info->addr_width) {
> nor->addr_width = info->addr_width;
> - else if (mtd->size > 0x100) {
> + } else if (mtd->size > 0x100) {
> /* enable 4-byte addressing if the device exceeds 16MiB */
> nor->addr_width = 4;
> if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
> diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
> index 55faa2f07cca..0df3638ff0b8 100644
> --- a/include/linux/mtd/spi-nor.h
> +++ b/include/linux/mtd/spi-nor.h
> @@ -41,6 +41,8 @@
> #define SPINOR_OP_WREN 0x06/* Write enable */
> #define SPINOR_OP_RDSR 0x05/* Read status register */
> #define SPINOR_OP_WRSR 0x01/* Write status register 1 byte
> */
> +#define SPINOR_OP_RDSR2 0x3f/* Read status register 2 */
> +#define SPINOR_OP_WRSR2 0x3e/* Write status register 2 */
> #define SPINOR_OP_READ 0x03/* Read data bytes (low
> frequency) */
> #define SPINOR_OP_READ_FAST 0x0b/* Read data bytes (high frequency) */
> #define SPINOR_OP_READ_1_1_2 0x3b/* Read data bytes (Dual Output SPI) */
> @@ -56,6 +58,7 @@
> #define SPINOR_OP_CHIP_ERASE 0xc7/* Erase whole flash chip */
> #define SPINOR_OP_SE 0xd8/* Sector erase (usually 64KiB) */
> #define SPINOR_OP_RDID 0x9f/* Read JEDEC ID */
> +#define SPINOR_OP_RDSFDP 0x5a/* Read SFDP */
> #define SPINOR_OP_RDCR 0x35/* Read configuration register
> */
> #define SPINOR_OP_RDFSR 0x70/* Read flag status register */
>
> @@ -128,6 +131,9 @@
> /* Configuration Register bits. */
> #define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
>
> +/* Status Register 2 bits. */
> +#define SR2_QUAD_EN_BIT7 BIT(7)
> +
> /* Supported SPI protocols */
> #define SNOR_PROTO_INST_MASK GENMASK(23, 16)
> #define SNOR_PROTO_INST_SHIFT16
>
--
Best regards,
Marek Vasut
@gmail.com>
Works for me
Reviewed-by: Marek Vasut <marek.va...@gmail.com>
> ---
> drivers/mtd/spi-nor/cadence-quadspi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c
> b/drivers/mtd/spi-nor/cade
On 05/04/2017 11:42 AM, Leonard Crestez wrote:
> On Wed, 2017-05-03 at 21:33 +0200, Marek Vasut wrote:
>> On 05/03/2017 07:58 PM, Leonard Crestez wrote:
>>> On Wed, 2017-05-03 at 17:59 +0200, Marek Vasut wrote:
>>>> On 05/03/2017 04:58 PM, Leonard Crestez wrote:
>
n buggy bindings, they need to get them
through Rob :) IMO for MX7, this should be "imx7-gpmi-nand" , unless
there's some incentive to discern the solo/dual chips and/or there
is a future imx7 coming up with different GPMI NAND block version.
>> Hi Guys,
>>
>> Yes, there should be a i.MX7 Solo version with one core fused out. IMO, can
>> we use QUIRK to distinguish them rather than SoC name. I know I also sent
>> some patch set with SoC Name but I prefer to use QUIRK now.
>
> Not sure what this means. Are you okay with Stefan's v2?
IMO the GPMI controller in solo and dual should be the same, so there's
no need to have quirks for it.
--
Best regards,
Marek Vasut
Add the MFD part of the ROHM BD9571MWV-M PMIC driver and MAINTAINERS
entry. The MFD part only specifies the regmap bits for the PMIC and
binds the subdevs together.
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: linux-kernel@vger.kernel.org
Cc: Geert Uytterhoeven <g
On 05/04/2017 02:44 PM, Shawn Guo wrote:
> On Thu, May 04, 2017 at 12:06:11PM +0200, Marek Vasut wrote:
>> On 05/04/2017 11:42 AM, Leonard Crestez wrote:
>>> I think there is a further misunderstanding here. I have a problem
>>> where imx6sx-sdb rev C boards
On 05/04/2017 03:41 PM, Shawn Guo wrote:
> On Thu, May 04, 2017 at 03:08:41PM +0200, Marek Vasut wrote:
>> On 05/04/2017 02:44 PM, Shawn Guo wrote:
>>> On Thu, May 04, 2017 at 12:06:11PM +0200, Marek Vasut wrote:
>
>
>
>>>> Mind you, my patch i
w_base;
> + q->window_size = window_size;
> +
> + q->flags = flags;
> +
> + dev_set_drvdata(dev, q);
> +
> + dev_dbg(dev, "%s SR=0x%x FSR=0x%x\n", __func__,
> + alt_qspi_readl(q->csr_base, QUADSPI_SR_REG),
> + alt_qspi_readl(q->csr_base, QUADSPI_FLAG_STATUS_REG));
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(altera_quadspi_create);
> +
> +int altera_qspi_add_bank(struct device *dev,
> + u32 bank, struct device_node *np)
> +{
> + struct altera_quadspi *q = dev_get_drvdata(dev);
> +
> + if (q->num_flashes >= ALTERA_QUADSPI_MAX_NUM_FLASH_CHIP)
> + return -ENOMEM;
> +
> + q->num_flashes++;
> +
> + return altera_quadspi_setup_banks(dev, bank, np);
> +}
> +EXPORT_SYMBOL_GPL(altera_qspi_add_bank);
> +
> +int altera_quadspi_remove_banks(struct device *dev)
> +{
> + struct altera_quadspi *q = dev_get_drvdata(dev);
> + struct altera_quadspi_flash *flash;
> + int i;
> + int ret = 0;
> +
> + /* clean up for all nor flash */
> + for (i = 0; i < q->num_flashes; i++) {
> + flash = q->flash[i];
> + if (!flash)
> + continue;
> +
> + /* clean up mtd stuff */
> + ret = mtd_device_unregister(>nor.mtd);
> + if (ret) {
> + dev_err(dev, "error removing mtd\n");
> + return ret;
> + }
> + }
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(altera_quadspi_remove_banks);
> +
> +MODULE_AUTHOR("Viet Nga Dao <vn...@altera.com>");
> +MODULE_AUTHOR("Yong Sern Lau <lau.yong.s...@intel.com>");
> +MODULE_AUTHOR("Matthew Gerlach <matthew.gerl...@linux.intel.com>");
> +MODULE_DESCRIPTION("Altera QuadSPI Version 2 Driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/include/linux/mtd/altera-quadspi.h
> b/include/linux/mtd/altera-quadspi.h
> new file mode 100644
> index 000..58f31ee
> --- /dev/null
> +++ b/include/linux/mtd/altera-quadspi.h
> @@ -0,0 +1,28 @@
> +/*
> + *
> + * Copyright 2017 Intel Corporation, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +#ifndef __ALTERA_QUADSPI_H
> +#define __ALTERA_QUADSPI_H
> +
> +#include
> +
> +#define ALTERA_QUADSPI_FL_BITREV_READ BIT(0)
> +#define ALTERA_QUADSPI_FL_BITREV_WRITE BIT(1)
> +
> +#define ALTERA_QUADSPI_MAX_NUM_FLASH_CHIP 3
> +
> +int altera_quadspi_create(struct device *dev, void __iomem *csr_base,
> + void __iomem *data_base, void __iomem *window_reg,
> + size_t window_size, u32 flags);
> +
> +int altera_qspi_add_bank(struct device *dev,
> + u32 bank, struct device_node *np);
> +
> +int altera_quadspi_remove_banks(struct device *dev);
Why is this header needed at all ?
> +#endif
>
--
Best regards,
Marek Vasut
efers to the 3Eh and 3Fh instruction op codes to write/read
> the Status Register 2 on some SPI NOR flash memories, the 35h op code
> still being used to read the Configuration Register/Status Register 2 on
> other memories.
>
> Signed-off-by: Cyrille Pitchen <cyrille.pitc.
so, they're altera specific, so altr, prefix should be added.
> +Example:
> +
> +qspi: spi@a0001000 {
> + compatible = "altr,quadspi-v2";
> + reg = <0xa0001000 0x40>, <0xb000 0x400>;
> + reg-names = "avl_csr", "avl_mem";
> +
> + flash@0 {
> + reg = <0>;
> + label = "FPGA Image";
> + };
> +};
>
--
Best regards,
Marek Vasut
On 05/02/2017 02:18 PM, Marek Vasut wrote:
> Add the MFD part of the ROHM BD9571MWV-M PMIC driver and MAINTAINERS
> entry. The MFD part only specifies the regmap bits for the PMIC and
> binds the subdevs together.
>
> Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com&g
gt;dev);
> +}
> +
> +static const struct of_device_id altera_quadspi_id_table[] = {
> +
> + { .compatible = "altr,quadspi-v2",},
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, altera_quadspi_id_table);
> +
> +static struct platform_driver altera_quadspi_driver = {
> + .driver = {
> + .name = "altera_quadspi_platform",
> + .of_match_table = altera_quadspi_id_table,
> + },
> + .probe = altera_quadspi_probe,
> + .remove = altera_quadspi_remove,
> +};
> +module_platform_driver(altera_quadspi_driver);
> +
> +MODULE_AUTHOR("Viet Nga Dao <vn...@altera.com>");
> +MODULE_AUTHOR("Yong Sern Lau <lau.yong.s...@intel.com>");
> +MODULE_AUTHOR("Matthew Gerlach <matthew.gerl...@linux.intel.com>");
> +MODULE_DESCRIPTION("Altera QuadSPI Version 2 Platform Driver");
> +MODULE_LICENSE("GPL v2");
>
--
Best regards,
Marek Vasut
angelog is missing. And for such a huge patch, the description is
really tiny.
> ---
> drivers/mtd/spi-nor/spi-nor.c | 775
> +-
> include/linux/mtd/spi-nor.h | 6 +
> 2 files changed, 768 insertions(+), 13 deletions(-)
Otherwise,
Reviewed-by: M
.
> + /* Kernel-only stuff starts here. */
> const char *name;
> int index;
>
>
--
Best regards,
Marek Vasut
as a dependency.
>>
>> Signed-off-by: Thor Thayer <thor.tha...@linux.intel.com>
Reviewed-by: Marek Vasut <marek.va...@gmail.com>
I presume it was tested on Stratix 10 ?
>> ---
>> drivers/mtd/spi-nor/Kconfig | 2 +-
>> 1 file changed, 1 insertion(+)
't assume 4 byte addressing (Cryille Pichecn and Marek Vasut).
> Fixed #define indenting as suggested by Marek Vasut.
> Added units to timer values as suggested by Marek Vasut.
> Use io(read|write)8_rep() as suggested by Marek Vasut.
> Renamed function prefixed with
binding to enable loop-back
>> circuit
>> mtd: spi-nor: cadence-quadspi: Add support to enable loop-back clock
>> circuit
>> mtd: spi-nor: cadence-quadspi: Fix error path in probe
>> mtd: spi-nor: cadence-quadspi: Add runtime PM support
>>
>> .../dev
d 'disable-over-current' binding to allow of the
> option of disabling the over-current condition.
>
> Signed-off-by: Dinh Nguyen <dingu...@kernel.org>
Reviewed-by: Marek Vasut <ma...@denx.de>
Similar patch was in U-Boot for two years now and it does the trick indeed.
&g
On 10/17/2017 12:29 AM, Cyrille Pitchen wrote:
> Hi all,
>
> Le 16/10/2017 à 11:28, Marek Vasut a écrit :
>> On 10/16/2017 08:15 AM, Vignesh R wrote:
>>>
>>>
>>> On Tuesday 03 October 2017 10:49 AM, Vignesh R wrote:
>>>>
>>>>
On 09/26/2017 12:41 AM, matthew.gerl...@linux.intel.com wrote:
>
>
> On Sun, 24 Sep 2017, Marek Vasut wrote:
>
>> On 09/24/2017 03:27 PM, Vignesh R wrote:
>>>
>>>
>>> On 9/24/2017 6:42 PM, Marek Vasut wrote:
>>>> On 09/24/2017 03:08 PM
pdev->name, cqspi);
> @@ -1284,7 +1302,14 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {
> #endif
>
> static const struct of_device_id cqspi_dt_ids[] = {
> - {.compatible = "cdns,qspi-nor",},
> + {
> + .compatible = "cdns,qspi-nor",
> + .data = (void *)0,
> + },
> + {
> + .compatible = "ti,k2g-qspi",
> + .data = (void *)CQSPI_NEEDS_WR_DELAY,
> + },
> { /* end of table */ }
> };
>
>
--
Best regards,
Marek Vasut
>clk);
> if (ret) {
> dev_err(dev, "Cannot enable QSPI clock.\n");
> @@ -1275,6 +1283,9 @@ static int cqspi_remove(struct platform_device *pdev)
>
> clk_disable_unprepare(cqspi->clk);
>
> + pm_runtime_put_sync(>dev);
> + pm_runtime_disable(>dev);
> +
> return 0;
> }
>
>
--
Best regards,
Marek Vasut
On 09/24/2017 03:08 PM, Vignesh R wrote:
>
>
> On 9/24/2017 5:31 PM, Marek Vasut wrote:
>> On 09/24/2017 12:59 PM, Vignesh R wrote:
>>> Add pm_runtime* calls to cadence-quadspi driver. This is required to
>>> switch on QSPI power domain on TI 66AK2G SoC
On 09/24/2017 02:33 PM, Vignesh R wrote:
>
>
> On 9/24/2017 5:29 PM, Marek Vasut wrote:
>> On 09/24/2017 12:59 PM, Vignesh R wrote:
>>> As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access
>>> Controller programming sequence, a delay equal to cou
On 09/24/2017 03:27 PM, Vignesh R wrote:
>
>
> On 9/24/2017 6:42 PM, Marek Vasut wrote:
>> On 09/24/2017 03:08 PM, Vignesh R wrote:
>>>
>>>
>>> On 9/24/2017 5:31 PM, Marek Vasut wrote:
>>>> On 09/24/2017 12:59 PM, Vignesh R wrote:
* SPI NOR memory during boot. Limit accessible
> + * size to 16MiB.
> + */
> + nor->addr_width = 3;
> + mtd->size = 0x100;
> + dev_info(dev, "Force 3B addressing mode\n");
> + } else
> set_4byte(nor, info, 1);
> } else {
> nor->addr_width = 3;
>
--
Best regards,
Marek Vasut
t; ispi->sregs = ispi->base + BXT_SSFSTS_CTL;
> ispi->pregs = ispi->base + BXT_PR;
> ispi->nregions = BXT_FREG_NUM;
> + ispi->pr_num = BXT_PR_NUM;
> ispi->erase_64k = true;
> break;
>
> @@ -652,7 +658,7 @@ static bool intel_spi_is_protected(const struct intel_spi
> *ispi,
> {
> int i;
>
> - for (i = 0; i < PR_NUM; i++) {
> + for (i = 0; i < ispi->pr_num; i++) {
> u32 pr_base, pr_limit, pr_value;
>
> pr_value = readl(ispi->pregs + PR(i));
>
--
Best regards,
Marek Vasut
On 10/11/2017 07:00 PM, matthew.gerl...@linux.intel.com wrote:
>
>
> On Tue, 10 Oct 2017, Marek Vasut wrote:
>
>> On 09/20/2017 08:28 PM, matthew.gerl...@linux.intel.com wrote:
>>> From: Matthew Gerlach <matthew.gerl...@linux.intel.com>
>>>
>>&
...@vger.kernel.org
> Signed-off-by: Arnd Bergmann <a...@arndb.de>
Don't you lose type-checking with this conversion to macros ?
--
Best regards,
Marek Vasut
n a
>> perfect world.
>
> Right. To clarify, this is a potential security issue, as it might be used to
> construct a stack overflow to cause privilege escalation when combined
> with some other vulnerabilities. I'd definitely want this backported to
> stable kernels as a precaution, and I'm preparing a patch to warn
> about this kind of problem again in 'allmodconfig' kernels that
> currently disable the warning on arm64 and x86.
Wouldn't it make more sense to fix the compiler instead ?
This still feels like we're fixing a bug at the wrong place ...
--
Best regards,
Marek Vasut
On 12/18/2017 11:29 AM, Arnd Bergmann wrote:
> On Mon, Dec 18, 2017 at 10:18 AM, Marek Vasut <marek.va...@gmail.com> wrote:
>> On 12/18/2017 10:16 AM, Arnd Bergmann wrote:
>>> On Sun, Dec 17, 2017 at 9:34 PM, Richard Weinberger <rich...@nod.at> wrote:
>>>&g
On 12/17/2017 09:43 AM, Boris Brezillon wrote:
> Hi Marek,
>
> On Wed, 11 Oct 2017 23:34:33 +0200
> Marek Vasut <marek.va...@gmail.com> wrote:
>
>> On 10/11/2017 03:54 PM, Arnd Bergmann wrote:
>>> The map_word_() functions, dating back to linux-2.6.8, t
ee/bindings/mtd/jedec,spi-nor.txt
>> +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
>> @@ -31,6 +31,7 @@ Required properties:
>> s25sl12801
>> s25fl008k
>> s25fl064k
>> + sst25vf016b
>> sst25vf040b
>> sst25wf040b
>> m25p40
>>
>
--
Best regards,
Marek Vasut
>>> +
>>> + if (acpi_has_method(als->device->handle, "\\_SB.PCI0.LPCB.EC0.ALSC"))
>>> {
>> So this is poking something on
>> PCI bus 0
>> LPC bus B
>> Somethingbus 0
>> Ambient light controller.
>>
>> I assume there is a better way of establishing this needs to be set?
>>
>>> + status = acpi_evaluate_integer(als->device->handle,
>>> +"\\_SB.PCI0.LPCB.EC0.ALSC",
>>> +_list,
>>> +_val);
>>> + }
>>> +
>>> return devm_iio_device_register(>dev, indio_dev);
>>> }
>>>
>>
--
Best regards,
Marek Vasut
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