[PATCH v8 1/2] dt-bindings: serial: Add rx-tx-swap to stm32-usart

[Martin Devera]

Add new rx-tx-swap property to allow for RX & TX pin swapping.

Signed-off-by: Martin Devera 
Acked-by: Fabrice Gasnier 
Reviewed-by: Rob Herring 
---
v8:
  - rebase to the latest tty-next
v7:
  - fix yaml linter warning
v6:
  - add version changelog
v5:
  - yaml fixes based on Rob Herring comments
- add serial.yaml reference
- move compatible from 'then' to 'if'
v3:
  - don't allow rx-tx-swap for st,stm32-uart (suggested
by Fabrice Gasnier)
v2:
  - change st,swap to rx-tx-swap (suggested by Rob Herring)
---
 .../devicetree/bindings/serial/st,stm32-uart.yaml  | 29 ++
 1 file changed, 19 insertions(+), 10 deletions(-)
---
 .../devicetree/bindings/serial/st,stm32-uart.yaml  | 29 ++
 1 file changed, 19 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml 
b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
index 8631678283f9..126e07566965 100644
--- a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
@@ -9,9 +9,6 @@ maintainers:
 
 title: STMicroelectronics STM32 USART bindings
 
-allOf:
-  - $ref: rs485.yaml
-
 properties:
   compatible:
 enum:
@@ -40,6 +37,8 @@ properties:
 
   uart-has-rtscts: true
 
+  rx-tx-swap: true
+
   dmas:
 minItems: 1
 maxItems: 2
@@ -66,13 +65,23 @@ properties:
   linux,rs485-enabled-at-boot-time: true
   rs485-rx-during-tx: true
 
-if:
-  required:
-- st,hw-flow-ctrl
-then:
-  properties:
-cts-gpios: false
-rts-gpios: false
+allOf:
+  - $ref: rs485.yaml#
+  - $ref: serial.yaml#
+  - if:
+  required:
+- st,hw-flow-ctrl
+then:
+  properties:
+cts-gpios: false
+rts-gpios: false
+  - if:
+  properties:
+compatible:
+  const: st,stm32-uart
+then:
+  properties:
+rx-tx-swap: false
 
 required:
   - compatible
-- 
2.11.0

[PATCH v8 2/2] tty/serial: Add rx-tx-swap OF option to stm32-usart

[Martin Devera]

STM32 F7/H7 usarts supports RX & TX pin swapping.
Add option to turn it on.
Tested on STM32MP157.

Signed-off-by: Martin Devera 
Acked-by: Fabrice Gasnier 
---
v8:
  - rebase to the latest tty-next
v6:
  - add version changelog
v4:
  - delete superfluous has_swap=false
v3:
  - add has_swap to stm32_usart_info (because F4 line
doesn't support swapping)
  - move swap variable init from stm32_usart_of_get_port
to stm32_usart_init_port because info struct is not
initialized in stm32_usart_of_get_port yet
  - set USART_CR2_SWAP in stm32_usart_startup too
v2:
  - change st,swap to rx-tx-swap (pointed out by Rob Herring)
  - rebase patches as suggested by Greg Kroah-Hartman
---
 drivers/tty/serial/stm32-usart.c | 11 ++-
 drivers/tty/serial/stm32-usart.h |  4 
 2 files changed, 14 insertions(+), 1 deletion(-)
---
 drivers/tty/serial/stm32-usart.c | 11 ++-
 drivers/tty/serial/stm32-usart.h |  4 
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/stm32-usart.c b/drivers/tty/serial/stm32-usart.c
index cba4f4ddf164..4d277804c63e 100644
--- a/drivers/tty/serial/stm32-usart.c
+++ b/drivers/tty/serial/stm32-usart.c
@@ -671,6 +671,12 @@ static int stm32_usart_startup(struct uart_port *port)
if (ret)
return ret;
 
+   if (stm32_port->swap) {
+   val = readl_relaxed(port->membase + ofs->cr2);
+   val |= USART_CR2_SWAP;
+   writel_relaxed(val, port->membase + ofs->cr2);
+   }
+
/* RX FIFO Flush */
if (ofs->rqr != UNDEF_REG)
writel_relaxed(USART_RQR_RXFRQ, port->membase + ofs->rqr);
@@ -789,7 +795,7 @@ static void stm32_usart_set_termios(struct uart_port *port,
cr1 = USART_CR1_TE | USART_CR1_RE;
if (stm32_port->fifoen)
cr1 |= USART_CR1_FIFOEN;
-   cr2 = 0;
+   cr2 = stm32_port->swap ? USART_CR2_SWAP : 0;
 
/* Tx and RX FIFO configuration */
cr3 = readl_relaxed(port->membase + ofs->cr3);
@@ -1047,6 +1053,9 @@ static int stm32_usart_init_port(struct stm32_port 
*stm32port,
stm32port->wakeup_src = stm32port->info->cfg.has_wakeup &&
of_property_read_bool(pdev->dev.of_node, "wakeup-source");
 
+   stm32port->swap = stm32port->info->cfg.has_swap &&
+   of_property_read_bool(pdev->dev.of_node, "rx-tx-swap");
+
stm32port->fifoen = stm32port->info->cfg.has_fifo;
 
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
diff --git a/drivers/tty/serial/stm32-usart.h b/drivers/tty/serial/stm32-usart.h
index a86773f1a4c4..77d1ac082e89 100644
--- a/drivers/tty/serial/stm32-usart.h
+++ b/drivers/tty/serial/stm32-usart.h
@@ -25,6 +25,7 @@ struct stm32_usart_offsets {
 struct stm32_usart_config {
u8 uart_enable_bit; /* USART_CR1_UE */
bool has_7bits_data;
+   bool has_swap;
bool has_wakeup;
bool has_fifo;
int fifosize;
@@ -76,6 +77,7 @@ struct stm32_usart_info stm32f7_info = {
.cfg = {
.uart_enable_bit = 0,
.has_7bits_data = true,
+   .has_swap = true,
.fifosize = 1,
}
 };
@@ -97,6 +99,7 @@ struct stm32_usart_info stm32h7_info = {
.cfg = {
.uart_enable_bit = 0,
.has_7bits_data = true,
+   .has_swap = true,
.has_wakeup = true,
.has_fifo = true,
.fifosize = 16,
@@ -268,6 +271,7 @@ struct stm32_port {
int last_res;
bool tx_dma_busy;/* dma tx busy   */
bool hw_flow_control;
+   bool swap;   /* swap RX & TX pins */
bool fifoen;
bool wakeup_src;
int rdr_mask;   /* receive data register mask */
-- 
2.11.0

[PATCH v7 2/2] tty/serial: Add rx-tx-swap OF option to stm32-usart

[Martin Devera]

STM32 F7/H7 usarts supports RX & TX pin swapping.
Add option to turn it on.
Tested on STM32MP157.

Signed-off-by: Martin Devera 
Acked-by: Fabrice Gasnier 
---
v6: 
  - add version changelog
v4:
  - delete superfluous has_swap=false
v3:
  - add has_swap to stm32_usart_info (because F4 line
doesn't support swapping)
  - move swap variable init from stm32_usart_of_get_port
to stm32_usart_init_port because info struct is not
initialized in stm32_usart_of_get_port yet
  - set USART_CR2_SWAP in stm32_usart_startup too
v2:
  - change st,swap to rx-tx-swap (pointed out by Rob Herring)
  - rebase patches as suggested by Greg Kroah-Hartman
---
 drivers/tty/serial/stm32-usart.c | 11 ++-
 drivers/tty/serial/stm32-usart.h |  4 
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/stm32-usart.c b/drivers/tty/serial/stm32-usart.c
index b3675cf25a69..d390f7da1441 100644
--- a/drivers/tty/serial/stm32-usart.c
+++ b/drivers/tty/serial/stm32-usart.c
@@ -644,6 +644,12 @@ static int stm32_usart_startup(struct uart_port *port)
if (ret)
return ret;
 
+   if (stm32_port->swap) {
+   val = readl_relaxed(port->membase + ofs->cr2);
+   val |= USART_CR2_SWAP;
+   writel_relaxed(val, port->membase + ofs->cr2);
+   }
+
/* RX FIFO Flush */
if (ofs->rqr != UNDEF_REG)
stm32_usart_set_bits(port, ofs->rqr, USART_RQR_RXFRQ);
@@ -758,7 +764,7 @@ static void stm32_usart_set_termios(struct uart_port *port,
cr1 = USART_CR1_TE | USART_CR1_RE;
if (stm32_port->fifoen)
cr1 |= USART_CR1_FIFOEN;
-   cr2 = 0;
+   cr2 = stm32_port->swap ? USART_CR2_SWAP : 0;
cr3 = readl_relaxed(port->membase + ofs->cr3);
cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTCFG_MASK | USART_CR3_RXFTIE
| USART_CR3_TXFTCFG_MASK;
@@ -1006,6 +1012,9 @@ static int stm32_usart_init_port(struct stm32_port 
*stm32port,
return stm32port->wakeirq ? : -ENODEV;
}
 
+   stm32port->swap = stm32port->info->cfg.has_swap &&
+   of_property_read_bool(pdev->dev.of_node, "rx-tx-swap");
+
stm32port->fifoen = stm32port->info->cfg.has_fifo;
 
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
diff --git a/drivers/tty/serial/stm32-usart.h b/drivers/tty/serial/stm32-usart.h
index cb4f327c46db..a85391e71e8e 100644
--- a/drivers/tty/serial/stm32-usart.h
+++ b/drivers/tty/serial/stm32-usart.h
@@ -25,6 +25,7 @@ struct stm32_usart_offsets {
 struct stm32_usart_config {
u8 uart_enable_bit; /* USART_CR1_UE */
bool has_7bits_data;
+   bool has_swap;
bool has_wakeup;
bool has_fifo;
int fifosize;
@@ -76,6 +77,7 @@ struct stm32_usart_info stm32f7_info = {
.cfg = {
.uart_enable_bit = 0,
.has_7bits_data = true,
+   .has_swap = true,
.fifosize = 1,
}
 };
@@ -97,6 +99,7 @@ struct stm32_usart_info stm32h7_info = {
.cfg = {
.uart_enable_bit = 0,
.has_7bits_data = true,
+   .has_swap = true,
.has_wakeup = true,
.has_fifo = true,
.fifosize = 16,
@@ -271,6 +274,7 @@ struct stm32_port {
int last_res;
bool tx_dma_busy;/* dma tx busy   */
bool hw_flow_control;
+   bool swap;   /* swap RX & TX pins */
bool fifoen;
int wakeirq;
int rdr_mask;   /* receive data register mask */
-- 
2.11.0

[PATCH v7 1/2] dt-bindings: serial: Add rx-tx-swap to stm32-usart

[Martin Devera]

Add new rx-tx-swap property to allow for RX & TX pin swapping.

Signed-off-by: Martin Devera 
Acked-by: Fabrice Gasnier 
---
v7:
  - fix yaml linter warning
v6: 
  - add version changelog
v5: 
  - yaml fixes based on Rob Herring comments
- add serial.yaml reference
- move compatible from 'then' to 'if'
v3:
  - don't allow rx-tx-swap for st,stm32-uart (suggested
by Fabrice Gasnier)
v2:
  - change st,swap to rx-tx-swap (suggested by Rob Herring)
---
 .../devicetree/bindings/serial/st,stm32-uart.yaml  | 29 ++
 1 file changed, 19 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml 
b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
index 8631678283f9..68a0f3ce8328 100644
--- a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
@@ -9,9 +9,6 @@ maintainers:
 
 title: STMicroelectronics STM32 USART bindings
 
-allOf:
-  - $ref: rs485.yaml
-
 properties:
   compatible:
 enum:
@@ -40,6 +37,8 @@ properties:
 
   uart-has-rtscts: true
 
+  rx-tx-swap: true
+
   dmas:
 minItems: 1
 maxItems: 2
@@ -66,13 +65,23 @@ properties:
   linux,rs485-enabled-at-boot-time: true
   rs485-rx-during-tx: true
 
-if:
-  required:
-- st,hw-flow-ctrl
-then:
-  properties:
-cts-gpios: false
-rts-gpios: false
+allOf:
+  - $ref: rs485.yaml#
+  - $ref: serial.yaml#
+  - if:
+  required:
+- st,hw-flow-ctrl
+then:
+  properties:
+cts-gpios: false
+rts-gpios: false
+  - if:
+  properties:
+compatible:
+  const: st,stm32-uart
+then:
+  properties:
+rx-tx-swap: false
 
 required:
   - compatible
-- 
2.11.0

Re: [PATCH v6 1/2] dt-bindings: serial: Add rx-tx-swap to stm32-usart

[Martin DEVERA]

On 3/12/21 3:56 PM, Martin DEVERA wrote:

On 3/12/21 3:23 PM, Rob Herring wrote:

On Fri, 12 Mar 2021 11:27:12 +0100, Martin Devera wrote:

Add new rx-tx-swap property to allow for RX & TX pin swapping.

Signed-off-by: Martin Devera 
Acked-by: Fabrice Gasnier 
---
v6:
   - add version changelog
v5:
   - yaml fixes based on Rob Herring comments
 - add serial.yaml reference
 - move compatible from 'then' to 'if'
v3:
   - don't allow rx-tx-swap for st,stm32-uart (suggested
 by Fabrice Gasnier)
v2:
   - change st,swap to rx-tx-swap (suggested by Rob Herring)
---
  .../devicetree/bindings/serial/st,stm32-uart.yaml  | 29 
++

  1 file changed, 19 insertions(+), 10 deletions(-)


My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:
./Documentation/devicetree/bindings/serial/st,stm32-uart.yaml:81:12: 
[warning] wrong indentation: expected 10 but found 11 (indentation)


dtschema/dtc warnings/errors:

See https://patchwork.ozlabs.org/patch/1451861

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Yoy are right, there is one extra space. But for some reason the check 
doesn't
find it: 

Argh... sorry, ignore it please. It seems I removed yamllint.
I see the error now.

Re: [PATCH v6 1/2] dt-bindings: serial: Add rx-tx-swap to stm32-usart

[Martin DEVERA]

On 3/12/21 3:23 PM, Rob Herring wrote:

On Fri, 12 Mar 2021 11:27:12 +0100, Martin Devera wrote:

Add new rx-tx-swap property to allow for RX & TX pin swapping.

Signed-off-by: Martin Devera 
Acked-by: Fabrice Gasnier 
---
v6:
   - add version changelog
v5:
   - yaml fixes based on Rob Herring comments
 - add serial.yaml reference
 - move compatible from 'then' to 'if'
v3:
   - don't allow rx-tx-swap for st,stm32-uart (suggested
 by Fabrice Gasnier)
v2:
   - change st,swap to rx-tx-swap (suggested by Rob Herring)
---
  .../devicetree/bindings/serial/st,stm32-uart.yaml  | 29 ++
  1 file changed, 19 insertions(+), 10 deletions(-)


My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:
./Documentation/devicetree/bindings/serial/st,stm32-uart.yaml:81:12: [warning] 
wrong indentation: expected 10 but found 11 (indentation)

dtschema/dtc warnings/errors:

See https://patchwork.ozlabs.org/patch/1451861

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Yoy are right, there is one extra space. But for some reason the check 
doesn't

find it:
$ make dt_binding_check 
DT_SCHEMA_FILES=Documentation/devicetree/bindings/serial/st,stm32-uart.yaml

  CHKDT Documentation/devicetree/bindings/processed-schema-examples.json
  SCHEMA Documentation/devicetree/bindings/processed-schema-examples.json
/home/devik/.local/lib/python3.9/site-packages/dtschema/schemas/serial/rs485.yaml: 
duplicate '$id' value 'http://devicetree.org/schemas/serial/rs485.yaml#'

  DTEX Documentation/devicetree/bindings/serial/st,stm32-uart.example.dts
  DTC 
Documentation/devicetree/bindings/serial/st,stm32-uart.example.dt.yaml
  CHECK 
Documentation/devicetree/bindings/serial/st,stm32-uart.example.dt.yaml


$ git describe
v5.12-rc2-2-g2f2a4a95dd38

$ pip3 show dtschema
Name: dtschema
Version: 2021.2.1

Any idea why ?

Thanks, Martin

[PATCH v6 2/2] tty/serial: Add rx-tx-swap OF option to stm32-usart

[Martin Devera]

STM32 F7/H7 usarts supports RX & TX pin swapping.
Add option to turn it on.
Tested on STM32MP157.

Signed-off-by: Martin Devera 
Acked-by: Fabrice Gasnier 
---
v6: 
  - add version changelog
v4:
  - delete superfluous has_swap=false
v3:
  - add has_swap to stm32_usart_info (because F4 line
doesn't support swapping)
  - move swap variable init from stm32_usart_of_get_port
to stm32_usart_init_port because info struct is not
initialized in stm32_usart_of_get_port yet
  - set USART_CR2_SWAP in stm32_usart_startup too
v2:
  - change st,swap to rx-tx-swap (pointed out by Rob Herring)
  - rebase patches as suggested by Greg Kroah-Hartman
---
 drivers/tty/serial/stm32-usart.c | 11 ++-
 drivers/tty/serial/stm32-usart.h |  4 
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/stm32-usart.c b/drivers/tty/serial/stm32-usart.c
index b3675cf25a69..d390f7da1441 100644
--- a/drivers/tty/serial/stm32-usart.c
+++ b/drivers/tty/serial/stm32-usart.c
@@ -644,6 +644,12 @@ static int stm32_usart_startup(struct uart_port *port)
if (ret)
return ret;
 
+   if (stm32_port->swap) {
+   val = readl_relaxed(port->membase + ofs->cr2);
+   val |= USART_CR2_SWAP;
+   writel_relaxed(val, port->membase + ofs->cr2);
+   }
+
/* RX FIFO Flush */
if (ofs->rqr != UNDEF_REG)
stm32_usart_set_bits(port, ofs->rqr, USART_RQR_RXFRQ);
@@ -758,7 +764,7 @@ static void stm32_usart_set_termios(struct uart_port *port,
cr1 = USART_CR1_TE | USART_CR1_RE;
if (stm32_port->fifoen)
cr1 |= USART_CR1_FIFOEN;
-   cr2 = 0;
+   cr2 = stm32_port->swap ? USART_CR2_SWAP : 0;
cr3 = readl_relaxed(port->membase + ofs->cr3);
cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTCFG_MASK | USART_CR3_RXFTIE
| USART_CR3_TXFTCFG_MASK;
@@ -1006,6 +1012,9 @@ static int stm32_usart_init_port(struct stm32_port 
*stm32port,
return stm32port->wakeirq ? : -ENODEV;
}
 
+   stm32port->swap = stm32port->info->cfg.has_swap &&
+   of_property_read_bool(pdev->dev.of_node, "rx-tx-swap");
+
stm32port->fifoen = stm32port->info->cfg.has_fifo;
 
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
diff --git a/drivers/tty/serial/stm32-usart.h b/drivers/tty/serial/stm32-usart.h
index cb4f327c46db..a85391e71e8e 100644
--- a/drivers/tty/serial/stm32-usart.h
+++ b/drivers/tty/serial/stm32-usart.h
@@ -25,6 +25,7 @@ struct stm32_usart_offsets {
 struct stm32_usart_config {
u8 uart_enable_bit; /* USART_CR1_UE */
bool has_7bits_data;
+   bool has_swap;
bool has_wakeup;
bool has_fifo;
int fifosize;
@@ -76,6 +77,7 @@ struct stm32_usart_info stm32f7_info = {
.cfg = {
.uart_enable_bit = 0,
.has_7bits_data = true,
+   .has_swap = true,
.fifosize = 1,
}
 };
@@ -97,6 +99,7 @@ struct stm32_usart_info stm32h7_info = {
.cfg = {
.uart_enable_bit = 0,
.has_7bits_data = true,
+   .has_swap = true,
.has_wakeup = true,
.has_fifo = true,
.fifosize = 16,
@@ -271,6 +274,7 @@ struct stm32_port {
int last_res;
bool tx_dma_busy;/* dma tx busy   */
bool hw_flow_control;
+   bool swap;   /* swap RX & TX pins */
bool fifoen;
int wakeirq;
int rdr_mask;   /* receive data register mask */
-- 
2.11.0

[PATCH v6 1/2] dt-bindings: serial: Add rx-tx-swap to stm32-usart

[Martin Devera]

Add new rx-tx-swap property to allow for RX & TX pin swapping.

Signed-off-by: Martin Devera 
Acked-by: Fabrice Gasnier 
---
v6: 
  - add version changelog
v5: 
  - yaml fixes based on Rob Herring comments
- add serial.yaml reference
- move compatible from 'then' to 'if'
v3:
  - don't allow rx-tx-swap for st,stm32-uart (suggested
by Fabrice Gasnier)
v2:
  - change st,swap to rx-tx-swap (suggested by Rob Herring)
---
 .../devicetree/bindings/serial/st,stm32-uart.yaml  | 29 ++
 1 file changed, 19 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml 
b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
index 8631678283f9..68a0f3ce8328 100644
--- a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
@@ -9,9 +9,6 @@ maintainers:
 
 title: STMicroelectronics STM32 USART bindings
 
-allOf:
-  - $ref: rs485.yaml
-
 properties:
   compatible:
 enum:
@@ -40,6 +37,8 @@ properties:
 
   uart-has-rtscts: true
 
+  rx-tx-swap: true
+
   dmas:
 minItems: 1
 maxItems: 2
@@ -66,13 +65,23 @@ properties:
   linux,rs485-enabled-at-boot-time: true
   rs485-rx-during-tx: true
 
-if:
-  required:
-- st,hw-flow-ctrl
-then:
-  properties:
-cts-gpios: false
-rts-gpios: false
+allOf:
+  - $ref: rs485.yaml#
+  - $ref: serial.yaml#
+  - if:
+  required:
+- st,hw-flow-ctrl
+then:
+  properties:
+cts-gpios: false
+rts-gpios: false
+  - if:
+  properties:
+compatible:
+   const: st,stm32-uart
+then:
+  properties:
+rx-tx-swap: false
 
 required:
   - compatible
-- 
2.11.0

[PATCH v5 1/2] dt-bindings: serial: Add rx-tx-swap to stm32-usart

[Martin Devera]

Add new rx-tx-swap property to allow for RX & TX pin swapping.

Signed-off-by: Martin Devera 
Acked-by: Fabrice Gasnier 
---
 .../devicetree/bindings/serial/st,stm32-uart.yaml  | 29 ++
 1 file changed, 19 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml 
b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
index 8631678283f9..68a0f3ce8328 100644
--- a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
@@ -9,9 +9,6 @@ maintainers:
 
 title: STMicroelectronics STM32 USART bindings
 
-allOf:
-  - $ref: rs485.yaml
-
 properties:
   compatible:
 enum:
@@ -40,6 +37,8 @@ properties:
 
   uart-has-rtscts: true
 
+  rx-tx-swap: true
+
   dmas:
 minItems: 1
 maxItems: 2
@@ -66,13 +65,23 @@ properties:
   linux,rs485-enabled-at-boot-time: true
   rs485-rx-during-tx: true
 
-if:
-  required:
-- st,hw-flow-ctrl
-then:
-  properties:
-cts-gpios: false
-rts-gpios: false
+allOf:
+  - $ref: rs485.yaml#
+  - $ref: serial.yaml#
+  - if:
+  required:
+- st,hw-flow-ctrl
+then:
+  properties:
+cts-gpios: false
+rts-gpios: false
+  - if:
+  properties:
+compatible:
+   const: st,stm32-uart
+then:
+  properties:
+rx-tx-swap: false
 
 required:
   - compatible
-- 
2.11.0

[PATCH v5 2/2] tty/serial: Add rx-tx-swap OF option to stm32-usart

[Martin Devera]

STM32 F7/H7 usarts supports RX & TX pin swapping.
Add option to turn it on.
Tested on STM32MP157.

Signed-off-by: Martin Devera 
Acked-by: Fabrice Gasnier 
---
 drivers/tty/serial/stm32-usart.c | 11 ++-
 drivers/tty/serial/stm32-usart.h |  4 
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/stm32-usart.c b/drivers/tty/serial/stm32-usart.c
index b3675cf25a69..d390f7da1441 100644
--- a/drivers/tty/serial/stm32-usart.c
+++ b/drivers/tty/serial/stm32-usart.c
@@ -644,6 +644,12 @@ static int stm32_usart_startup(struct uart_port *port)
if (ret)
return ret;
 
+   if (stm32_port->swap) {
+   val = readl_relaxed(port->membase + ofs->cr2);
+   val |= USART_CR2_SWAP;
+   writel_relaxed(val, port->membase + ofs->cr2);
+   }
+
/* RX FIFO Flush */
if (ofs->rqr != UNDEF_REG)
stm32_usart_set_bits(port, ofs->rqr, USART_RQR_RXFRQ);
@@ -758,7 +764,7 @@ static void stm32_usart_set_termios(struct uart_port *port,
cr1 = USART_CR1_TE | USART_CR1_RE;
if (stm32_port->fifoen)
cr1 |= USART_CR1_FIFOEN;
-   cr2 = 0;
+   cr2 = stm32_port->swap ? USART_CR2_SWAP : 0;
cr3 = readl_relaxed(port->membase + ofs->cr3);
cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTCFG_MASK | USART_CR3_RXFTIE
| USART_CR3_TXFTCFG_MASK;
@@ -1006,6 +1012,9 @@ static int stm32_usart_init_port(struct stm32_port 
*stm32port,
return stm32port->wakeirq ? : -ENODEV;
}
 
+   stm32port->swap = stm32port->info->cfg.has_swap &&
+   of_property_read_bool(pdev->dev.of_node, "rx-tx-swap");
+
stm32port->fifoen = stm32port->info->cfg.has_fifo;
 
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
diff --git a/drivers/tty/serial/stm32-usart.h b/drivers/tty/serial/stm32-usart.h
index cb4f327c46db..a85391e71e8e 100644
--- a/drivers/tty/serial/stm32-usart.h
+++ b/drivers/tty/serial/stm32-usart.h
@@ -25,6 +25,7 @@ struct stm32_usart_offsets {
 struct stm32_usart_config {
u8 uart_enable_bit; /* USART_CR1_UE */
bool has_7bits_data;
+   bool has_swap;
bool has_wakeup;
bool has_fifo;
int fifosize;
@@ -76,6 +77,7 @@ struct stm32_usart_info stm32f7_info = {
.cfg = {
.uart_enable_bit = 0,
.has_7bits_data = true,
+   .has_swap = true,
.fifosize = 1,
}
 };
@@ -97,6 +99,7 @@ struct stm32_usart_info stm32h7_info = {
.cfg = {
.uart_enable_bit = 0,
.has_7bits_data = true,
+   .has_swap = true,
.has_wakeup = true,
.has_fifo = true,
.fifosize = 16,
@@ -271,6 +274,7 @@ struct stm32_port {
int last_res;
bool tx_dma_busy;/* dma tx busy   */
bool hw_flow_control;
+   bool swap;   /* swap RX & TX pins */
bool fifoen;
int wakeirq;
int rdr_mask;   /* receive data register mask */
-- 
2.11.0

[PATCH] ubifs: Report max LEB count at mount time

[Martin Devera]

There is no other way to directly report/query this
quantity. It is useful when planing how given filesystem
can be resized.

Signed-off-by: Martin Devera 
---
 fs/ubifs/super.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c
index ddb2ca636c93..178680d2338f 100644
--- a/fs/ubifs/super.c
+++ b/fs/ubifs/super.c
@@ -1552,8 +1552,8 @@ static int mount_ubifs(struct ubifs_info *c)
ubifs_msg(c, "LEB size: %d bytes (%d KiB), min./max. I/O unit sizes: %d 
bytes/%d bytes",
  c->leb_size, c->leb_size >> 10, c->min_io_size,
  c->max_write_size);
-   ubifs_msg(c, "FS size: %lld bytes (%lld MiB, %d LEBs), journal size 
%lld bytes (%lld MiB, %d LEBs)",
- x, x >> 20, c->main_lebs,
+   ubifs_msg(c, "FS size: %lld bytes (%lld MiB, %d LEBs), max %d LEBs, 
journal size %lld bytes (%lld MiB, %d LEBs)",
+ x, x >> 20, c->main_lebs, c->max_leb_cnt,
  y, y >> 20, c->log_lebs + c->max_bud_cnt);
ubifs_msg(c, "reserved for root: %llu bytes (%llu KiB)",
  c->report_rp_size, c->report_rp_size >> 10);
-- 
2.11.0

Re: [PATCH v3 2/2] tty/serial: Add rx-tx-swap OF option to stm32-usart

[Martin DEVERA]

On 3/2/21 6:44 PM, Fabrice Gasnier wrote:

On 3/2/21 2:15 PM, Martin Devera wrote:

STM32 F7/H7 usarts supports RX & TX pin swapping.
Add option to turn it on.
Tested on STM32MP157.

Signed-off-by: Martin Devera 
---
  drivers/tty/serial/stm32-usart.c | 11 ++-
  drivers/tty/serial/stm32-usart.h |  5 +
  2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/stm32-usart.c b/drivers/tty/serial/stm32-usart.c
index b3675cf25a69..d390f7da1441 100644
--- a/drivers/tty/serial/stm32-usart.c
+++ b/drivers/tty/serial/stm32-usart.c
@@ -644,6 +644,12 @@ static int stm32_usart_startup(struct uart_port *port)
if (ret)
return ret;
  
+	if (stm32_port->swap) {

+   val = readl_relaxed(port->membase + ofs->cr2);
+   val |= USART_CR2_SWAP;
+   writel_relaxed(val, port->membase + ofs->cr2);
+   }
+
/* RX FIFO Flush */
if (ofs->rqr != UNDEF_REG)
stm32_usart_set_bits(port, ofs->rqr, USART_RQR_RXFRQ);
@@ -758,7 +764,7 @@ static void stm32_usart_set_termios(struct uart_port *port,
cr1 = USART_CR1_TE | USART_CR1_RE;
if (stm32_port->fifoen)
cr1 |= USART_CR1_FIFOEN;
-   cr2 = 0;
+   cr2 = stm32_port->swap ? USART_CR2_SWAP : 0;
cr3 = readl_relaxed(port->membase + ofs->cr3);
cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTCFG_MASK | USART_CR3_RXFTIE
| USART_CR3_TXFTCFG_MASK;
@@ -1006,6 +1012,9 @@ static int stm32_usart_init_port(struct stm32_port 
*stm32port,
return stm32port->wakeirq ? : -ENODEV;
}
  
+	stm32port->swap = stm32port->info->cfg.has_swap &&

+   of_property_read_bool(pdev->dev.of_node, "rx-tx-swap");
+
stm32port->fifoen = stm32port->info->cfg.has_fifo;
  
  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

diff --git a/drivers/tty/serial/stm32-usart.h b/drivers/tty/serial/stm32-usart.h
index cb4f327c46db..bd18dd1c1bcd 100644
--- a/drivers/tty/serial/stm32-usart.h
+++ b/drivers/tty/serial/stm32-usart.h
@@ -25,6 +25,7 @@ struct stm32_usart_offsets {
  struct stm32_usart_config {
u8 uart_enable_bit; /* USART_CR1_UE */
bool has_7bits_data;
+   bool has_swap;
bool has_wakeup;
bool has_fifo;
int fifosize;
@@ -55,6 +56,7 @@ struct stm32_usart_info stm32f4_info = {
.cfg = {
.uart_enable_bit = 13,
.has_7bits_data = false,
+   .has_swap = false,

Hi Martin,

Only one minor comment from me here. No need to add a false (zero)
initialization in this struct. I'm not sure why this is the case for the
has_7bits_data here...

With that fixed, you can add my:
Acked-by: Fabrice Gasnier 


The has_7bits_data was what made me a bit unsure. Ok fixed now.
Thank you for your review.

Martin

[PATCH v4 2/2] tty/serial: Add rx-tx-swap OF option to stm32-usart

[Martin Devera]

STM32 F7/H7 usarts supports RX & TX pin swapping.
Add option to turn it on.
Tested on STM32MP157.

Signed-off-by: Martin Devera 
---
 drivers/tty/serial/stm32-usart.c | 11 ++-
 drivers/tty/serial/stm32-usart.h |  4 
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/stm32-usart.c b/drivers/tty/serial/stm32-usart.c
index b3675cf25a69..d390f7da1441 100644
--- a/drivers/tty/serial/stm32-usart.c
+++ b/drivers/tty/serial/stm32-usart.c
@@ -644,6 +644,12 @@ static int stm32_usart_startup(struct uart_port *port)
if (ret)
return ret;
 
+   if (stm32_port->swap) {
+   val = readl_relaxed(port->membase + ofs->cr2);
+   val |= USART_CR2_SWAP;
+   writel_relaxed(val, port->membase + ofs->cr2);
+   }
+
/* RX FIFO Flush */
if (ofs->rqr != UNDEF_REG)
stm32_usart_set_bits(port, ofs->rqr, USART_RQR_RXFRQ);
@@ -758,7 +764,7 @@ static void stm32_usart_set_termios(struct uart_port *port,
cr1 = USART_CR1_TE | USART_CR1_RE;
if (stm32_port->fifoen)
cr1 |= USART_CR1_FIFOEN;
-   cr2 = 0;
+   cr2 = stm32_port->swap ? USART_CR2_SWAP : 0;
cr3 = readl_relaxed(port->membase + ofs->cr3);
cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTCFG_MASK | USART_CR3_RXFTIE
| USART_CR3_TXFTCFG_MASK;
@@ -1006,6 +1012,9 @@ static int stm32_usart_init_port(struct stm32_port 
*stm32port,
return stm32port->wakeirq ? : -ENODEV;
}
 
+   stm32port->swap = stm32port->info->cfg.has_swap &&
+   of_property_read_bool(pdev->dev.of_node, "rx-tx-swap");
+
stm32port->fifoen = stm32port->info->cfg.has_fifo;
 
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
diff --git a/drivers/tty/serial/stm32-usart.h b/drivers/tty/serial/stm32-usart.h
index cb4f327c46db..a85391e71e8e 100644
--- a/drivers/tty/serial/stm32-usart.h
+++ b/drivers/tty/serial/stm32-usart.h
@@ -25,6 +25,7 @@ struct stm32_usart_offsets {
 struct stm32_usart_config {
u8 uart_enable_bit; /* USART_CR1_UE */
bool has_7bits_data;
+   bool has_swap;
bool has_wakeup;
bool has_fifo;
int fifosize;
@@ -76,6 +77,7 @@ struct stm32_usart_info stm32f7_info = {
.cfg = {
.uart_enable_bit = 0,
.has_7bits_data = true,
+   .has_swap = true,
.fifosize = 1,
}
 };
@@ -97,6 +99,7 @@ struct stm32_usart_info stm32h7_info = {
.cfg = {
.uart_enable_bit = 0,
.has_7bits_data = true,
+   .has_swap = true,
.has_wakeup = true,
.has_fifo = true,
.fifosize = 16,
@@ -271,6 +274,7 @@ struct stm32_port {
int last_res;
bool tx_dma_busy;/* dma tx busy   */
bool hw_flow_control;
+   bool swap;   /* swap RX & TX pins */
bool fifoen;
int wakeirq;
int rdr_mask;   /* receive data register mask */
-- 
2.11.0

[PATCH v4 1/2] dt-bindings: serial: Add rx-tx-swap to stm32-usart

[Martin Devera]

Add new rx-tx-swap property to allow for RX & TX pin swapping.

Signed-off-by: Martin Devera 
---
 .../devicetree/bindings/serial/st,stm32-uart.yaml  | 32 +++---
 1 file changed, 22 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml 
b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
index 8631678283f9..6eab2debebb5 100644
--- a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
@@ -9,9 +9,6 @@ maintainers:
 
 title: STMicroelectronics STM32 USART bindings
 
-allOf:
-  - $ref: rs485.yaml
-
 properties:
   compatible:
 enum:
@@ -40,6 +37,10 @@ properties:
 
   uart-has-rtscts: true
 
+  rx-tx-swap:
+type: boolean
+maxItems: 1
+
   dmas:
 minItems: 1
 maxItems: 2
@@ -66,13 +67,24 @@ properties:
   linux,rs485-enabled-at-boot-time: true
   rs485-rx-during-tx: true
 
-if:
-  required:
-- st,hw-flow-ctrl
-then:
-  properties:
-cts-gpios: false
-rts-gpios: false
+allOf:
+  - $ref: rs485.yaml
+  - if:
+  required:
+- st,hw-flow-ctrl
+then:
+  properties:
+cts-gpios: false
+rts-gpios: false
+  - if:
+  required:
+- rx-tx-swap
+then:
+  properties:
+compatible:
+  enum:
+- st,stm32f7-uart
+- st,stm32h7-uart
 
 required:
   - compatible
-- 
2.11.0

[PATCH v3 1/2] dt-bindings: serial: Add rx-tx-swap to stm32-usart

[Martin Devera]

Add new rx-tx-swap property to allow for RX & TX pin swapping.

Signed-off-by: Martin Devera 
---
 .../devicetree/bindings/serial/st,stm32-uart.yaml  | 32 +++---
 1 file changed, 22 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml 
b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
index 8631678283f9..6eab2debebb5 100644
--- a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
@@ -9,9 +9,6 @@ maintainers:
 
 title: STMicroelectronics STM32 USART bindings
 
-allOf:
-  - $ref: rs485.yaml
-
 properties:
   compatible:
 enum:
@@ -40,6 +37,10 @@ properties:
 
   uart-has-rtscts: true
 
+  rx-tx-swap:
+type: boolean
+maxItems: 1
+
   dmas:
 minItems: 1
 maxItems: 2
@@ -66,13 +67,24 @@ properties:
   linux,rs485-enabled-at-boot-time: true
   rs485-rx-during-tx: true
 
-if:
-  required:
-- st,hw-flow-ctrl
-then:
-  properties:
-cts-gpios: false
-rts-gpios: false
+allOf:
+  - $ref: rs485.yaml
+  - if:
+  required:
+- st,hw-flow-ctrl
+then:
+  properties:
+cts-gpios: false
+rts-gpios: false
+  - if:
+  required:
+- rx-tx-swap
+then:
+  properties:
+compatible:
+  enum:
+- st,stm32f7-uart
+- st,stm32h7-uart
 
 required:
   - compatible
-- 
2.11.0

[PATCH v3 2/2] tty/serial: Add rx-tx-swap OF option to stm32-usart

[Martin Devera]

STM32 F7/H7 usarts supports RX & TX pin swapping.
Add option to turn it on.
Tested on STM32MP157.

Signed-off-by: Martin Devera 
---
 drivers/tty/serial/stm32-usart.c | 11 ++-
 drivers/tty/serial/stm32-usart.h |  5 +
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/stm32-usart.c b/drivers/tty/serial/stm32-usart.c
index b3675cf25a69..d390f7da1441 100644
--- a/drivers/tty/serial/stm32-usart.c
+++ b/drivers/tty/serial/stm32-usart.c
@@ -644,6 +644,12 @@ static int stm32_usart_startup(struct uart_port *port)
if (ret)
return ret;
 
+   if (stm32_port->swap) {
+   val = readl_relaxed(port->membase + ofs->cr2);
+   val |= USART_CR2_SWAP;
+   writel_relaxed(val, port->membase + ofs->cr2);
+   }
+
/* RX FIFO Flush */
if (ofs->rqr != UNDEF_REG)
stm32_usart_set_bits(port, ofs->rqr, USART_RQR_RXFRQ);
@@ -758,7 +764,7 @@ static void stm32_usart_set_termios(struct uart_port *port,
cr1 = USART_CR1_TE | USART_CR1_RE;
if (stm32_port->fifoen)
cr1 |= USART_CR1_FIFOEN;
-   cr2 = 0;
+   cr2 = stm32_port->swap ? USART_CR2_SWAP : 0;
cr3 = readl_relaxed(port->membase + ofs->cr3);
cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTCFG_MASK | USART_CR3_RXFTIE
| USART_CR3_TXFTCFG_MASK;
@@ -1006,6 +1012,9 @@ static int stm32_usart_init_port(struct stm32_port 
*stm32port,
return stm32port->wakeirq ? : -ENODEV;
}
 
+   stm32port->swap = stm32port->info->cfg.has_swap &&
+   of_property_read_bool(pdev->dev.of_node, "rx-tx-swap");
+
stm32port->fifoen = stm32port->info->cfg.has_fifo;
 
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
diff --git a/drivers/tty/serial/stm32-usart.h b/drivers/tty/serial/stm32-usart.h
index cb4f327c46db..bd18dd1c1bcd 100644
--- a/drivers/tty/serial/stm32-usart.h
+++ b/drivers/tty/serial/stm32-usart.h
@@ -25,6 +25,7 @@ struct stm32_usart_offsets {
 struct stm32_usart_config {
u8 uart_enable_bit; /* USART_CR1_UE */
bool has_7bits_data;
+   bool has_swap;
bool has_wakeup;
bool has_fifo;
int fifosize;
@@ -55,6 +56,7 @@ struct stm32_usart_info stm32f4_info = {
.cfg = {
.uart_enable_bit = 13,
.has_7bits_data = false,
+   .has_swap = false,
.fifosize = 1,
}
 };
@@ -76,6 +78,7 @@ struct stm32_usart_info stm32f7_info = {
.cfg = {
.uart_enable_bit = 0,
.has_7bits_data = true,
+   .has_swap = true,
.fifosize = 1,
}
 };
@@ -97,6 +100,7 @@ struct stm32_usart_info stm32h7_info = {
.cfg = {
.uart_enable_bit = 0,
.has_7bits_data = true,
+   .has_swap = true,
.has_wakeup = true,
.has_fifo = true,
.fifosize = 16,
@@ -271,6 +275,7 @@ struct stm32_port {
int last_res;
bool tx_dma_busy;/* dma tx busy   */
bool hw_flow_control;
+   bool swap;   /* swap RX & TX pins */
bool fifoen;
int wakeirq;
int rdr_mask;   /* receive data register mask */
-- 
2.11.0

Re: [PATCH v2 1/2] tty/serial: Add rx-tx-swap OF option to stm32-usart

[Martin DEVERA]

On 3/1/21 11:28 AM, Fabrice Gasnier wrote:

On 2/27/21 5:41 PM, Martin Devera wrote:

STM32 F7/H7 usarts supports RX & TX pin swapping.
Add option to turn it on.
Tested on STM32MP157.

Signed-off-by: Martin Devera 
---
  drivers/tty/serial/stm32-usart.c | 3 ++-
  drivers/tty/serial/stm32-usart.h | 1 +
  2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/stm32-usart.c b/drivers/tty/serial/stm32-usart.c
index b3675cf25a69..3650c8798061 100644
--- a/drivers/tty/serial/stm32-usart.c
+++ b/drivers/tty/serial/stm32-usart.c
@@ -758,7 +758,7 @@ static void stm32_usart_set_termios(struct uart_port *port,
cr1 = USART_CR1_TE | USART_CR1_RE;
if (stm32_port->fifoen)
cr1 |= USART_CR1_FIFOEN;
-   cr2 = 0;
+   cr2 = stm32_port->swap ? USART_CR2_SWAP : 0;

Hi Martin,

Same could be done in the startup routine, that enables the port for
reception (as described in Documentation/driver-api/serial/driver.rst)

Hello Fabrice,

I already incorporated all your comments but I'm struggling with the one 
above.

The code must be in stm32_usart_set_termios too, because CR2 is modified.
What is the reason to have it in startup() ?
Is it because USART can be started without calling set_termios at all ? Like
to reuse bootloader's last settings ?

Thanks, Martin

[PATCH] usb: dwc2: Add STM32 related debugfs entries

[Martin Devera]

These are entries related to STM32MP1 PHY control.

Signed-off-by: Martin Devera 
---
 drivers/usb/dwc2/debugfs.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/usb/dwc2/debugfs.c b/drivers/usb/dwc2/debugfs.c
index aaafd463d72a..f13eed4231e1 100644
--- a/drivers/usb/dwc2/debugfs.c
+++ b/drivers/usb/dwc2/debugfs.c
@@ -691,6 +691,8 @@ static int params_show(struct seq_file *seq, void *v)
print_param(seq, p, ulpi_fs_ls);
print_param(seq, p, host_support_fs_ls_low_power);
print_param(seq, p, host_ls_low_power_phy_clk);
+   print_param(seq, p, activate_stm_fs_transceiver);
+   print_param(seq, p, activate_stm_id_vb_detection);
print_param(seq, p, ts_dline);
print_param(seq, p, reload_ctl);
print_param_hex(seq, p, ahbcfg);
-- 
2.11.0

[PATCH v2 2/2] dt-bindings: serial: Add rx-tx-swap to stm32-usart

[Martin Devera]

Add new rx-tx-swap property to allow for RX & TX pin swapping.

Signed-off-by: Martin Devera 
---
 Documentation/devicetree/bindings/serial/st,stm32-uart.yaml | 4 
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml 
b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
index 8631678283f9..45f2a19997da 100644
--- a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
@@ -40,6 +40,10 @@ properties:
 
   uart-has-rtscts: true
 
+  rx-tx-swap:
+type: boolean
+maxItems: 1
+
   dmas:
 minItems: 1
 maxItems: 2
-- 
2.11.0

[PATCH v2 1/2] tty/serial: Add rx-tx-swap OF option to stm32-usart

[Martin Devera]

STM32 F7/H7 usarts supports RX & TX pin swapping.
Add option to turn it on.
Tested on STM32MP157.

Signed-off-by: Martin Devera 
---
 drivers/tty/serial/stm32-usart.c | 3 ++-
 drivers/tty/serial/stm32-usart.h | 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/stm32-usart.c b/drivers/tty/serial/stm32-usart.c
index b3675cf25a69..3650c8798061 100644
--- a/drivers/tty/serial/stm32-usart.c
+++ b/drivers/tty/serial/stm32-usart.c
@@ -758,7 +758,7 @@ static void stm32_usart_set_termios(struct uart_port *port,
cr1 = USART_CR1_TE | USART_CR1_RE;
if (stm32_port->fifoen)
cr1 |= USART_CR1_FIFOEN;
-   cr2 = 0;
+   cr2 = stm32_port->swap ? USART_CR2_SWAP : 0;
cr3 = readl_relaxed(port->membase + ofs->cr3);
cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTCFG_MASK | USART_CR3_RXFTIE
| USART_CR3_TXFTCFG_MASK;
@@ -1078,6 +1078,7 @@ static struct stm32_port *stm32_usart_of_get_port(struct 
platform_device *pdev)
stm32_ports[id].hw_flow_control =
of_property_read_bool (np, "st,hw-flow-ctrl") /*deprecated*/ ||
of_property_read_bool (np, "uart-has-rtscts");
+   stm32_ports[id].swap = of_property_read_bool(np, "rx-tx-swap");
stm32_ports[id].port.line = id;
stm32_ports[id].cr1_irq = USART_CR1_RXNEIE;
stm32_ports[id].cr3_irq = 0;
diff --git a/drivers/tty/serial/stm32-usart.h b/drivers/tty/serial/stm32-usart.h
index cb4f327c46db..2f054e2dc0ab 100644
--- a/drivers/tty/serial/stm32-usart.h
+++ b/drivers/tty/serial/stm32-usart.h
@@ -271,6 +271,7 @@ struct stm32_port {
int last_res;
bool tx_dma_busy;/* dma tx busy   */
bool hw_flow_control;
+   bool swap;   /* swap RX & TX pins */
bool fifoen;
int wakeirq;
int rdr_mask;   /* receive data register mask */
-- 
2.11.0

Re: armmmci rmmod causes hung tasks

[Martin DEVERA]

On 11/30/20 4:08 PM, Ulf Hansson wrote:

On Sun, 29 Nov 2020 at 19:20, Martin DEVERA  wrote:

Hello,

on STM32MP1 with almost vanilla 5.7.7 in single CPU mode. Pair of
modprobe armmmci ; rmmod armmmci

causes rmmod and kworker to hang. I should note that no MMC is detected
on the board (SDIO device on MMC bus is not responding).
On another board (where SDIO is responding) rmmod works.

It seems as another manifestation of https://lkml.org/lkml/2019/8/27/945

Thanks.

INFO: task kworker/0:1:12 blocked for more than 368 seconds.
Not tainted 5.7.7kdb-3-g10397828596c-dirty #224
"echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
kworker/0:1 D012  2 0x
Workqueue: events_freezable mmc_rescan
(__schedule) from (schedule+0x5b/0x90)
(schedule) from (schedule_timeout+0x1b/0xa0)
(schedule_timeout) from (__wait_for_common+0x7d/0xdc)
(__wait_for_common) from (mmc_wait_for_req_done+0x1b/0x8c)
(mmc_wait_for_req_done) from (mmc_wait_for_cmd+0x4d/0x68)
(mmc_wait_for_cmd) from (mmc_io_rw_direct_host+0x87/0xc8)
(mmc_io_rw_direct_host) from (sdio_reset+0x3b/0x58)
(sdio_reset) from (mmc_rescan+0x15d/0x1d4)
(mmc_rescan) from (process_one_work+0xdd/0x168)
(process_one_work) from (worker_thread+0x17d/0x1ec)
(worker_thread) from (kthread+0x9b/0xa4)
(kthread) from (ret_from_fork+0x11/0x28)

It looks like the worker thread, which runs mmc_rescan() to try to
detect the SDIO card is hanging. Exactly why, I don't know.

Could be a misconfigured clock, pinctrl or a power domain being
suddenly gated...


I turned some logging on (see below), IIUC pl18x is starting CMD52 with arg
SDIO_CCCR_ABORT read and it got IRQ later along with response. Then sending
again SDIO_CCCR_ABORT write but no IRQ comes back.

[  135.810802] mmc0: mmc_rescan_try_freq: trying to init card at 40 Hz
[  135.810832] mmc0: starting CMD52 arg 0c00 flags 0195
[  135.810862] mmci-pl18x 48004000.sdmmc: op 34 arg 0c00 flags 0195
[  135.811155] mmci-pl18x 48004000.sdmmc: irq0 (data+cmd) 0040
[  135.811178] mmc0: req done (CMD52): 0:    


[  135.811202] mmci-pl18x 48004000.sdmmc: irq0 (data+cmd) 
[  135.816487] mmc0: starting CMD52 arg 8c08 flags 0195
[  135.816506] mmci-pl18x 48004000.sdmmc: op 34 arg 8c08 flags 0195
[  172.150614] random: crng init done
[  172.150642] random: 6 urandom warning(s) missed due to ratelimiting
[  173.290565] INFO: task kworker/0:0:5 blocked for more than 20 seconds.

Here is the same system, only with different (working) SDIO device on 
the same bus:


[  495.654596] mmc0: mmc_rescan_try_freq: trying to init card at 40 Hz
[  495.654628] mmc0: starting CMD52 arg 0c00 flags 0195
[  495.654658] mmci-pl18x 48004000.sdmmc: op 34 arg 0c00 flags 0195
[  495.654996] mmci-pl18x 48004000.sdmmc: irq0 (data+cmd) 0004
[  495.655017] mmc0: req done (CMD52): -110:    


[  495.655042] mmci-pl18x 48004000.sdmmc: irq0 (data+cmd) 
[  495.660201] mmc0: starting CMD52 arg 8c08 flags 0195
[  495.660222] mmci-pl18x 48004000.sdmmc: op 34 arg 8c08 flags 0195
[  495.660549] mmci-pl18x 48004000.sdmmc: irq0 (data+cmd) 0004
[  495.660567] mmc0: req done (CMD52): -110:    


[  495.660591] mmci-pl18x 48004000.sdmmc: irq0 (data+cmd) 

Should it be expected, that invalid (probably non-responding) device on 
the SDIO bus

causes it to be locked up forever ?
Or is it bug in pl18x driver not handling the error correctly ?

best regards,
Martin

armmmci rmmod causes hung tasks

[Martin DEVERA]

Hello,

on STM32MP1 with almost vanilla 5.7.7 in single CPU mode. Pair of
modprobe armmmci ; rmmod armmmci

causes rmmod and kworker to hang. I should note that no MMC is detected
on the board (SDIO device on MMC bus is not responding).
On another board (where SDIO is responding) rmmod works.

It seems as another manifestation of https://lkml.org/lkml/2019/8/27/945

Thanks.

INFO: task kworker/0:1:12 blocked for more than 368 seconds.
  Not tainted 5.7.7kdb-3-g10397828596c-dirty #224
"echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
kworker/0:1 D    0    12  2 0x
Workqueue: events_freezable mmc_rescan
(__schedule) from (schedule+0x5b/0x90)
(schedule) from (schedule_timeout+0x1b/0xa0)
(schedule_timeout) from (__wait_for_common+0x7d/0xdc)
(__wait_for_common) from (mmc_wait_for_req_done+0x1b/0x8c)
(mmc_wait_for_req_done) from (mmc_wait_for_cmd+0x4d/0x68)
(mmc_wait_for_cmd) from (mmc_io_rw_direct_host+0x87/0xc8)
(mmc_io_rw_direct_host) from (sdio_reset+0x3b/0x58)
(sdio_reset) from (mmc_rescan+0x15d/0x1d4)
(mmc_rescan) from (process_one_work+0xdd/0x168)
(process_one_work) from (worker_thread+0x17d/0x1ec)
(worker_thread) from (kthread+0x9b/0xa4)
(kthread) from (ret_from_fork+0x11/0x28)

INFO: task rmmod:308 blocked for more than 368 seconds.
  Not tainted 5.7.7kdb-3-g10397828596c-dirty #224
"echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
rmmod   D    0   308    222 0x
(__schedule) from (schedule+0x5b/0x90)
(schedule) from (schedule_timeout+0x1b/0xa0)
(schedule_timeout) from (__wait_for_common+0x7d/0xdc)
(__wait_for_common) from (__flush_work+0xb3/0x110)
(__flush_work) from (__cancel_work_timer+0x97/0xf0)
(__cancel_work_timer) from (mmc_stop_host+0x29/0x88)
(mmc_stop_host) from (mmc_remove_host+0x9/0x22)
(mmc_remove_host) from (mmci_remove+0x19/0x92 [armmmci])
(mmci_remove [armmmci]) from (amba_remove+0x13/0x42)
(amba_remove) from (device_release_driver_internal+0x89/0xe4)
(device_release_driver_internal) from (driver_detach+0x57/0x60)
(driver_detach) from (bus_remove_driver+0x53/0x84)
(bus_remove_driver) from (mmci_driver_exit+0x9/0x11dc [armmmci])
(mmci_driver_exit [armmmci]) from (sys_delete_module+0x115/0x154)
(sys_delete_module) from (ret_fast_syscall+0x1/0x5a)

pinctrl: sx150x bug

[Martin DEVERA]

Hello,

I encountered bug in SX1502 expander driver in 5.7.7. Here is relevant 
DTS part:


compatible = "semtech,sx1502q";
gpio4_cfg_pins: gpio2-cfg {
    pins = "gpio5";
    output-high;
    };

And part of OOPS:

[    0.673996] [] (gpiochip_get_data) from [] 
(sx150x_gpio_direction_output+0xd)
[    0.683259] [] (sx150x_gpio_direction_output) from 
[] (sx150x_pinconf_set+0x)
[    0.692796] [] (sx150x_pinconf_set) from [] 
(pinconf_apply_setting+0x39/0x7e)
[    0.701635] [] (pinconf_apply_setting) from [] 
(pinctrl_commit_state+0xa5/0x)
[    0.710648] [] (pinctrl_commit_state) from [] 
(pinctrl_enable+0xff/0x1d4)
[    0.719139] [] (pinctrl_enable) from [] 
(sx150x_probe+0x1a3/0x358)
[    0.727027] [] (sx150x_probe) from [] 
(i2c_device_probe+0x1bb/0x1dc)


The problem is that sx150x_pinconf_set uses sx150x_gpio_direction_output 
but gpio is not

setup yet. Patch below fixes it but I'm not sure whether is it correct:

diff --git a/drivers/pinctrl/pinctrl-sx150x.c 
b/drivers/pinctrl/pinctrl-sx150x.c

index 6e74bd87d959..3f5651edd336 100644
--- a/drivers/pinctrl/pinctrl-sx150x.c
+++ b/drivers/pinctrl/pinctrl-sx150x.c
@@ -1154,12 +1154,6 @@ static int sx150x_probe(struct i2c_client *client,
    return ret;
    }

-   ret = pinctrl_enable(pctl->pctldev);
-   if (ret) {
-   dev_err(dev, "Failed to enable pinctrl device\n");
-   return ret;
-   }
-
    /* Register GPIO controller */
    pctl->gpio.base = -1;
    pctl->gpio.ngpio = pctl->data->npins;
@@ -1191,6 +1185,12 @@ static int sx150x_probe(struct i2c_client *client,
    if (ret)
    return ret;

+   ret = pinctrl_enable(pctl->pctldev);
+   if (ret) {
+   dev_err(dev, "Failed to enable pinctrl device\n");
+   return ret;
+   }
+
    ret = gpiochip_add_pin_range(>gpio, dev_name(dev),
 0, 0, pctl->data->npins);
    if (ret)

Re: [PATCH 1/2] Add NXP LPC32XX SPI driver

[Martin Devera]

Paul Bolle wrote:

(This hit my box with lkml mesages without lkml in the To: header. What
happened here?)


Ahh, have to check my sending script ..


On zo, 2015-07-12 at 11:20 +0200, Martin Devera wrote:

--- /dev/null
+++ b/drivers/spi/spi-lpc32xx.c



+#define DRIVER_NAME"spi-lpc32xx"



+MODULE_ALIAS("platform:" DRIVER_NAME);


This alias seems only useful if there's a corresponding struct
platform_device. Ie, a struct platform_device with a .name of "spi
-lpc32xx", which will fire off a "MODALIAS=platform:spi-lpc32xx" uevent
when it's created.


My fault, thanks for spotting. It is leftover from driver I used
as template...
In any case, I has other comments from Joachim Eastwood thus I plan
to do more cleanup and resubmit the driver later..

thanks,
Martin
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Re: [PATCH 1/2] Add NXP LPC32XX SPI driver

[Martin Devera]

Paul Bolle wrote:

(This hit my box with lkml mesages without lkml in the To: header. What
happened here?)


Ahh, have to check my sending script ..


On zo, 2015-07-12 at 11:20 +0200, Martin Devera wrote:

--- /dev/null
+++ b/drivers/spi/spi-lpc32xx.c



+#define DRIVER_NAMEspi-lpc32xx



+MODULE_ALIAS(platform: DRIVER_NAME);


This alias seems only useful if there's a corresponding struct
platform_device. Ie, a struct platform_device with a .name of spi
-lpc32xx, which will fire off a MODALIAS=platform:spi-lpc32xx uevent
when it's created.


My fault, thanks for spotting. It is leftover from driver I used
as template...
In any case, I has other comments from Joachim Eastwood thus I plan
to do more cleanup and resubmit the driver later..

thanks,
Martin
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[PATCH] Cleanup of NXP LPC32XX SPI driver

[Martin Devera]

Debug code is removed.
---
 drivers/spi/spi-lpc32xx.c |   16 
 1 file changed, 16 deletions(-)

diff --git a/drivers/spi/spi-lpc32xx.c b/drivers/spi/spi-lpc32xx.c
index 5c6b1ca..11b2c21 100644
--- a/drivers/spi/spi-lpc32xx.c
+++ b/drivers/spi/spi-lpc32xx.c
@@ -71,15 +71,6 @@ struct spi_lpc32xx_data {
unsigned long   rate;   /* master clock rate */
 };
 
-static int spi_lpc32xx_setup(struct spi_device *spi)
-{
-   /* We are expect that SPI-device is not selected */
-   //gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
-//
-   printk(" Setup spi\n");
-   return 0;
-}
-
 static int spi_lpc32xx_start(struct spi_lpc32xx_data *hw)
 {
int sz,mode;
@@ -88,8 +79,6 @@ static int spi_lpc32xx_start(struct spi_lpc32xx_data *hw)
 
mode = hw->mode;
mode |= (hw->bpw-1)<<9;
-// printk("in spi_lpc32xx_start sz=%d buf=%p isrd=%d mode=%X io=%p 
stat=%X\n",
-// 
sz,hw->buf,hw->is_rd,mode,hw->syncio,readl(SPI_STAT(hw->syncio)));
writel(mode,SPI_CON(hw->syncio));
writel(sz,SPI_FRM(hw->syncio));
writel(SPI_IER_INTEOT,SPI_IER(hw->syncio));
@@ -145,10 +134,6 @@ static irqreturn_t spi_lpc32xx_isr(int irq, void *dev_id)
int sz,i;
sz = hw->len;
if (sz > 64) sz = 64;
-#if 0
-   printk("in spi_lpc32xx_isr sz=%d buf=%p isrd=%d stat=%X\n",
-   sz,hw->buf,hw->is_rd,readl(SPI_STAT(hw->syncio)));
-#endif
 
if (hw->is_rd) {
writel(0,SPI_FRM(hw->syncio));
@@ -192,7 +177,6 @@ static int spi_lpc32xx_probe(struct platform_device *pdev)
master->bus_num = pdev->id;
master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST | SPI_3WIRE;
master->bits_per_word_mask =  SPI_BPW_RANGE_MASK(1, 8);
-   master->setup = spi_lpc32xx_setup;
master->transfer_one = spi_lpc32xx_transfer_one;
master->flags = SPI_MASTER_HALF_DUPLEX;
master->dev.of_node = pdev->dev.of_node;
-- 
1.7.10.4

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[PATCH 2/2] Add clock support for NXP LPC32XX SPI

[Martin Devera]

Clock support for SPIs on LPC32XX SoC.
---
 arch/arm/mach-lpc32xx/clock.c |   20 
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
index dd5d6f5..672c9b3 100644
--- a/arch/arm/mach-lpc32xx/clock.c
+++ b/arch/arm/mach-lpc32xx/clock.c
@@ -683,6 +683,24 @@ static struct clk clk_i2c2 = {
.get_rate   = local_return_parent_rate,
 };
 
+static struct clk clk_spi1 = {
+   .parent = _hclk,
+   .enable = local_onoff_enable,
+   .enable_reg = LPC32XX_CLKPWR_SPI_CLK_CTRL,
+   .enable_mask= LPC32XX_CLKPWR_SPICLK_SPI1CLK_EN|
+   LPC32XX_CLKPWR_SPICLK_USE_SPI1,
+   .get_rate   = local_return_parent_rate,
+};
+
+static struct clk clk_spi2 = {
+   .parent = _hclk,
+   .enable = local_onoff_enable,
+   .enable_reg = LPC32XX_CLKPWR_SPI_CLK_CTRL,
+   .enable_mask= LPC32XX_CLKPWR_SPICLK_SPI2CLK_EN|
+   LPC32XX_CLKPWR_SPICLK_USE_SPI2,
+   .get_rate   = local_return_parent_rate,
+};
+
 static struct clk clk_ssp0 = {
.parent = _hclk,
.enable = local_onoff_enable,
@@ -1217,6 +1235,8 @@ static struct clk_lookup lookups[] = {
CLKDEV_INIT("400a.i2c", NULL, _i2c0),
CLKDEV_INIT("400a8000.i2c", NULL, _i2c1),
CLKDEV_INIT("31020300.i2c", NULL, _i2c2),
+   CLKDEV_INIT("20088000.spi", NULL, _spi1),
+   CLKDEV_INIT("2009.spi", NULL, _spi2),
CLKDEV_INIT("dev:ssp0", NULL, _ssp0),
CLKDEV_INIT("dev:ssp1", NULL, _ssp1),
CLKDEV_INIT("4005.key", NULL, _kscan),
-- 
1.7.10.4

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[PATCH 1/2] Add NXP LPC32XX SPI driver

[Martin Devera]

This SPI device is found at least on NXP LPC32XX ARM
family. It has 64 entry FIFO and is quite fast when
using only IRQ.
The driver uses generic SPI and OF frameworks to
minimize its size.
It is tested in HW (SPI flash with JFFS2).
---
 .../devicetree/bindings/spi/spi_lpc32xx.txt|   32 +++
 drivers/spi/Kconfig|8 +
 drivers/spi/Makefile   |1 +
 drivers/spi/spi-lpc32xx.c  |  265 
 4 files changed, 306 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/spi_lpc32xx.txt
 create mode 100644 drivers/spi/spi-lpc32xx.c

diff --git a/Documentation/devicetree/bindings/spi/spi_lpc32xx.txt 
b/Documentation/devicetree/bindings/spi/spi_lpc32xx.txt
new file mode 100644
index 000..aef86f4
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi_lpc32xx.txt
@@ -0,0 +1,32 @@
+NXP LPC32XX SPI controller
+
+Required properties:
+- compatible : "nxp,lpc3220-spi"
+- reg : Offset and length of the register set for the device
+- interrupts : Should contain SPI controller interrupt
+- cs-gpios : should specify GPIOs used for chipselects.
+  The gpios will be referred to as reg =  in the SPI child nodes.
+
+SPI slave nodes must be children of the SPI master node and can
+contain the following properties.
+
+   spi-max-frequency = ;
+   spi-cpol;
+   spi-cpha;
+
+Example:
+   spi1: spi@20088000 {
+   status="okay";
+   interrupts = <55 0>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   num-cs = <1>;
+   cs-gpios = < 3 5 1>;
+   m25p80@1 {
+   compatible = "st,m25p80";
+   reg = <0>;
+   spi-max-frequency = <100>;
+   spi-cpol;
+   spi-cpha;
+   };
+   };
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 72b0590..373f013 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -375,6 +375,14 @@ config SPI_ORION
help
  This enables using the SPI master controller on the Orion chips.
 
+config SPI_LPC32XX
+   tristate "NXP LPC32XX SPI controller"
+   depends on ARCH_LPC32XX
+   help
+ This selects SPI controller found on NXP LPC32XX SoC. There
+ are also ARM AMBA PL022 SSP controllers, but NXP's SPI one
+ has 64 entry FIFOs as opossed to 8 entry in SSP.
+
 config SPI_PL022
tristate "ARM AMBA PL022 SSP controller"
depends on ARM_AMBA
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index d8cbf65..62a09bd 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_SPI_GPIO)+= spi-gpio.o
 obj-$(CONFIG_SPI_IMG_SPFI) += spi-img-spfi.o
 obj-$(CONFIG_SPI_IMX)  += spi-imx.o
 obj-$(CONFIG_SPI_LM70_LLP) += spi-lm70llp.o
+obj-$(CONFIG_SPI_LPC32XX)  += spi-lpc32xx.o
 obj-$(CONFIG_SPI_MESON_SPIFC)  += spi-meson-spifc.o
 obj-$(CONFIG_SPI_MPC512x_PSC)  += spi-mpc512x-psc.o
 obj-$(CONFIG_SPI_MPC52xx_PSC)  += spi-mpc52xx-psc.o
diff --git a/drivers/spi/spi-lpc32xx.c b/drivers/spi/spi-lpc32xx.c
new file mode 100644
index 000..5c6b1ca
--- /dev/null
+++ b/drivers/spi/spi-lpc32xx.c
@@ -0,0 +1,265 @@
+/*
+ *  LPC32XX SPI bus driver
+ *
+ *  Copyright (C) 2015 Martin Devera 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DRIVER_NAME"spi-lpc32xx"
+
+#define _BIT(n) (1<<(n))
+#define SPI_GLOB_RST_BIT(1) /* SPI interfase sw reset */
+#define SPI_GLOB_ENABLE _BIT(0) /* SPI interface enable */
+
+#define SPI_CON_UNIDIR  _BIT(23)/* DATIO pin dir control */
+#define SPI_CON_BHALT   _BIT(22)/* Busy halt control */
+#define SPI_CON_BPOL_BIT(21)/* Busy line polarity */
+#define SPI_CON_MSB _BIT(19)/* MSB/LSB control */
+#define SPI_CON_CPOL_BIT(17)/* CPOL control*/
+#define SPI_CON_CPHA_BIT(16)/* CPHA control*/
+#define SPI_CON_MODE00  0   /* mode = 00 */
+#define SPI_CON_MODE01  _BIT(16)/* mode = 01 */
+#define SPI_CON_MODE10  _BIT(17)/* mode = 10 */
+#define SPI_CON_MODE11  _SBF(16,0x3)/* mode = 11 */
+#define SPI_CON_RXTX_BIT(15)/* Tx/Rx control */
+#define SPI_CON_THR _BIT(14)/* FIFO threshold control */
+#d

[PATCH] Fix ARM LPC32XX platform broken by older commit

[Martin Devera]

In commit a71b092a9c68685a270ebdde7b5986ba8787e575
__handle_domain_irq was introduced by Marc Zyngier.
It tests hwirq on zero and rejects it. At least
LPC32XX uses IRQ 0 as chained entry for SIC1. Thus
all SIC1 connected devices doesn't work just now.
This patch fixes it - not sure whether it is correct
way however.
---
 kernel/irq/irqdesc.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/kernel/irq/irqdesc.c b/kernel/irq/irqdesc.c
index 99793b9..3c90794 100644
--- a/kernel/irq/irqdesc.c
+++ b/kernel/irq/irqdesc.c
@@ -381,7 +381,7 @@ int __handle_domain_irq(struct irq_domain *domain, unsigned 
int hwirq,
 * Some hardware gives randomly wrong interrupts.  Rather
 * than crashing, do something sensible.
 */
-   if (unlikely(!irq || irq >= nr_irqs)) {
+   if (unlikely(irq >= nr_irqs)) {
ack_bad_irq(irq);
ret = -EINVAL;
} else {
-- 
1.7.10.4

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[PATCH] Fix ARM LPC32XX platform broken by older commit

[Martin Devera]

In commit a71b092a9c68685a270ebdde7b5986ba8787e575
__handle_domain_irq was introduced by Marc Zyngier.
It tests hwirq on zero and rejects it. At least
LPC32XX uses IRQ 0 as chained entry for SIC1. Thus
all SIC1 connected devices doesn't work just now.
This patch fixes it - not sure whether it is correct
way however.
---
 kernel/irq/irqdesc.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/kernel/irq/irqdesc.c b/kernel/irq/irqdesc.c
index 99793b9..3c90794 100644
--- a/kernel/irq/irqdesc.c
+++ b/kernel/irq/irqdesc.c
@@ -381,7 +381,7 @@ int __handle_domain_irq(struct irq_domain *domain, unsigned 
int hwirq,
 * Some hardware gives randomly wrong interrupts.  Rather
 * than crashing, do something sensible.
 */
-   if (unlikely(!irq || irq = nr_irqs)) {
+   if (unlikely(irq = nr_irqs)) {
ack_bad_irq(irq);
ret = -EINVAL;
} else {
-- 
1.7.10.4

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[PATCH] Cleanup of NXP LPC32XX SPI driver

[Martin Devera]

Debug code is removed.
---
 drivers/spi/spi-lpc32xx.c |   16 
 1 file changed, 16 deletions(-)

diff --git a/drivers/spi/spi-lpc32xx.c b/drivers/spi/spi-lpc32xx.c
index 5c6b1ca..11b2c21 100644
--- a/drivers/spi/spi-lpc32xx.c
+++ b/drivers/spi/spi-lpc32xx.c
@@ -71,15 +71,6 @@ struct spi_lpc32xx_data {
unsigned long   rate;   /* master clock rate */
 };
 
-static int spi_lpc32xx_setup(struct spi_device *spi)
-{
-   /* We are expect that SPI-device is not selected */
-   //gpio_direction_output(spi-cs_gpio, !(spi-mode  SPI_CS_HIGH));
-//
-   printk( Setup spi\n);
-   return 0;
-}
-
 static int spi_lpc32xx_start(struct spi_lpc32xx_data *hw)
 {
int sz,mode;
@@ -88,8 +79,6 @@ static int spi_lpc32xx_start(struct spi_lpc32xx_data *hw)
 
mode = hw-mode;
mode |= (hw-bpw-1)9;
-// printk(in spi_lpc32xx_start sz=%d buf=%p isrd=%d mode=%X io=%p 
stat=%X\n,
-// 
sz,hw-buf,hw-is_rd,mode,hw-syncio,readl(SPI_STAT(hw-syncio)));
writel(mode,SPI_CON(hw-syncio));
writel(sz,SPI_FRM(hw-syncio));
writel(SPI_IER_INTEOT,SPI_IER(hw-syncio));
@@ -145,10 +134,6 @@ static irqreturn_t spi_lpc32xx_isr(int irq, void *dev_id)
int sz,i;
sz = hw-len;
if (sz  64) sz = 64;
-#if 0
-   printk(in spi_lpc32xx_isr sz=%d buf=%p isrd=%d stat=%X\n,
-   sz,hw-buf,hw-is_rd,readl(SPI_STAT(hw-syncio)));
-#endif
 
if (hw-is_rd) {
writel(0,SPI_FRM(hw-syncio));
@@ -192,7 +177,6 @@ static int spi_lpc32xx_probe(struct platform_device *pdev)
master-bus_num = pdev-id;
master-mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST | SPI_3WIRE;
master-bits_per_word_mask =  SPI_BPW_RANGE_MASK(1, 8);
-   master-setup = spi_lpc32xx_setup;
master-transfer_one = spi_lpc32xx_transfer_one;
master-flags = SPI_MASTER_HALF_DUPLEX;
master-dev.of_node = pdev-dev.of_node;
-- 
1.7.10.4

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[PATCH 2/2] Add clock support for NXP LPC32XX SPI

[Martin Devera]

Clock support for SPIs on LPC32XX SoC.
---
 arch/arm/mach-lpc32xx/clock.c |   20 
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
index dd5d6f5..672c9b3 100644
--- a/arch/arm/mach-lpc32xx/clock.c
+++ b/arch/arm/mach-lpc32xx/clock.c
@@ -683,6 +683,24 @@ static struct clk clk_i2c2 = {
.get_rate   = local_return_parent_rate,
 };
 
+static struct clk clk_spi1 = {
+   .parent = clk_hclk,
+   .enable = local_onoff_enable,
+   .enable_reg = LPC32XX_CLKPWR_SPI_CLK_CTRL,
+   .enable_mask= LPC32XX_CLKPWR_SPICLK_SPI1CLK_EN|
+   LPC32XX_CLKPWR_SPICLK_USE_SPI1,
+   .get_rate   = local_return_parent_rate,
+};
+
+static struct clk clk_spi2 = {
+   .parent = clk_hclk,
+   .enable = local_onoff_enable,
+   .enable_reg = LPC32XX_CLKPWR_SPI_CLK_CTRL,
+   .enable_mask= LPC32XX_CLKPWR_SPICLK_SPI2CLK_EN|
+   LPC32XX_CLKPWR_SPICLK_USE_SPI2,
+   .get_rate   = local_return_parent_rate,
+};
+
 static struct clk clk_ssp0 = {
.parent = clk_hclk,
.enable = local_onoff_enable,
@@ -1217,6 +1235,8 @@ static struct clk_lookup lookups[] = {
CLKDEV_INIT(400a.i2c, NULL, clk_i2c0),
CLKDEV_INIT(400a8000.i2c, NULL, clk_i2c1),
CLKDEV_INIT(31020300.i2c, NULL, clk_i2c2),
+   CLKDEV_INIT(20088000.spi, NULL, clk_spi1),
+   CLKDEV_INIT(2009.spi, NULL, clk_spi2),
CLKDEV_INIT(dev:ssp0, NULL, clk_ssp0),
CLKDEV_INIT(dev:ssp1, NULL, clk_ssp1),
CLKDEV_INIT(4005.key, NULL, clk_kscan),
-- 
1.7.10.4

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[PATCH 1/2] Add NXP LPC32XX SPI driver

[Martin Devera]

This SPI device is found at least on NXP LPC32XX ARM
family. It has 64 entry FIFO and is quite fast when
using only IRQ.
The driver uses generic SPI and OF frameworks to
minimize its size.
It is tested in HW (SPI flash with JFFS2).
---
 .../devicetree/bindings/spi/spi_lpc32xx.txt|   32 +++
 drivers/spi/Kconfig|8 +
 drivers/spi/Makefile   |1 +
 drivers/spi/spi-lpc32xx.c  |  265 
 4 files changed, 306 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/spi_lpc32xx.txt
 create mode 100644 drivers/spi/spi-lpc32xx.c

diff --git a/Documentation/devicetree/bindings/spi/spi_lpc32xx.txt 
b/Documentation/devicetree/bindings/spi/spi_lpc32xx.txt
new file mode 100644
index 000..aef86f4
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi_lpc32xx.txt
@@ -0,0 +1,32 @@
+NXP LPC32XX SPI controller
+
+Required properties:
+- compatible : nxp,lpc3220-spi
+- reg : Offset and length of the register set for the device
+- interrupts : Should contain SPI controller interrupt
+- cs-gpios : should specify GPIOs used for chipselects.
+  The gpios will be referred to as reg = index in the SPI child nodes.
+
+SPI slave nodes must be children of the SPI master node and can
+contain the following properties.
+
+   spi-max-frequency = hz;
+   spi-cpol;
+   spi-cpha;
+
+Example:
+   spi1: spi@20088000 {
+   status=okay;
+   interrupts = 55 0;
+   #address-cells = 1;
+   #size-cells = 0;
+   num-cs = 1;
+   cs-gpios = gpio 3 5 1;
+   m25p80@1 {
+   compatible = st,m25p80;
+   reg = 0;
+   spi-max-frequency = 100;
+   spi-cpol;
+   spi-cpha;
+   };
+   };
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 72b0590..373f013 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -375,6 +375,14 @@ config SPI_ORION
help
  This enables using the SPI master controller on the Orion chips.
 
+config SPI_LPC32XX
+   tristate NXP LPC32XX SPI controller
+   depends on ARCH_LPC32XX
+   help
+ This selects SPI controller found on NXP LPC32XX SoC. There
+ are also ARM AMBA PL022 SSP controllers, but NXP's SPI one
+ has 64 entry FIFOs as opossed to 8 entry in SSP.
+
 config SPI_PL022
tristate ARM AMBA PL022 SSP controller
depends on ARM_AMBA
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index d8cbf65..62a09bd 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_SPI_GPIO)+= spi-gpio.o
 obj-$(CONFIG_SPI_IMG_SPFI) += spi-img-spfi.o
 obj-$(CONFIG_SPI_IMX)  += spi-imx.o
 obj-$(CONFIG_SPI_LM70_LLP) += spi-lm70llp.o
+obj-$(CONFIG_SPI_LPC32XX)  += spi-lpc32xx.o
 obj-$(CONFIG_SPI_MESON_SPIFC)  += spi-meson-spifc.o
 obj-$(CONFIG_SPI_MPC512x_PSC)  += spi-mpc512x-psc.o
 obj-$(CONFIG_SPI_MPC52xx_PSC)  += spi-mpc52xx-psc.o
diff --git a/drivers/spi/spi-lpc32xx.c b/drivers/spi/spi-lpc32xx.c
new file mode 100644
index 000..5c6b1ca
--- /dev/null
+++ b/drivers/spi/spi-lpc32xx.c
@@ -0,0 +1,265 @@
+/*
+ *  LPC32XX SPI bus driver
+ *
+ *  Copyright (C) 2015 Martin Devera de...@cdi.cz
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include linux/io.h
+#include linux/clk.h
+#include linux/interrupt.h
+#include linux/platform_device.h
+#include linux/of_gpio.h
+#include linux/spi/spi.h
+
+#define DRIVER_NAMEspi-lpc32xx
+
+#define _BIT(n) (1(n))
+#define SPI_GLOB_RST_BIT(1) /* SPI interfase sw reset */
+#define SPI_GLOB_ENABLE _BIT(0) /* SPI interface enable */
+
+#define SPI_CON_UNIDIR  _BIT(23)/* DATIO pin dir control */
+#define SPI_CON_BHALT   _BIT(22)/* Busy halt control */
+#define SPI_CON_BPOL_BIT(21)/* Busy line polarity */
+#define SPI_CON_MSB _BIT(19)/* MSB/LSB control */
+#define SPI_CON_CPOL_BIT(17)/* CPOL control*/
+#define SPI_CON_CPHA_BIT(16)/* CPHA control*/
+#define SPI_CON_MODE00  0   /* mode = 00 */
+#define SPI_CON_MODE01  _BIT(16)/* mode = 01 */
+#define SPI_CON_MODE10  _BIT(17)/* mode = 10 */
+#define SPI_CON_MODE11  _SBF(16,0x3)/* mode = 11 */
+#define SPI_CON_RXTX_BIT(15)/* Tx/Rx control */
+#define SPI_CON_THR _BIT(14)/* FIFO threshold control */
+#define SPI_CON_SHIFT_OFF   _BIT

bug in ARM/LPC32XX eth init code / probably OF related

[Martin Devera]

Hi,

I compiled vanilla 4.1.1 for LPC3240 MPU without loadable module support.
I created own dts and board .c source:

static void __init lpc3250_machine_init(void)
{
__raw_writel(0x1600 ,LPC32XX_GPIO_P_MUX_SET); // SSP0
__raw_writel(1<<6 , io_p2v(0x40028004)); // ETH unreset

lpc32xx_serial_init();
of_platform_populate(NULL, of_default_bus_match_table,
 lpc32xx_auxdata_lookup, NULL);
}

All seems to be ok, only ETH doesn't work. I found the problem -
Micrel PHY driver is inited later than lpc_eth driver and it doesn't bind
to the eth.
I solved it by ugly hack - set status="disabled" for eth in dts and adding:

static struct of_device_id __initdata of_ids[] = {
 { .compatible = "nxp,lpc-eth" },{}
};
static void __init devik_late_init(void) // errorchecking omited
{
struct device_node *np;
np = of_find_compatible_node(NULL, NULL, "nxp,lpc-eth");
struct property *p = of_find_property(np,"status",NULL);
of_remove_property(np,p);
of_node_clear_flag(np, OF_POPULATED);
of_platform_bus_probe(np,of_ids,NULL);
}

Other solutiuon is to make it module a load later (we prefer no modules 
here),

or editing lpc_eth.c to register in device_initcall_sync.

Is there some better solution for the bug ?

devik
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bug in ARM/LPC32XX eth init code / probably OF related

[Martin Devera]

Hi,

I compiled vanilla 4.1.1 for LPC3240 MPU without loadable module support.
I created own dts and board .c source:

static void __init lpc3250_machine_init(void)
{
__raw_writel(0x1600 ,LPC32XX_GPIO_P_MUX_SET); // SSP0
__raw_writel(16 , io_p2v(0x40028004)); // ETH unreset

lpc32xx_serial_init();
of_platform_populate(NULL, of_default_bus_match_table,
 lpc32xx_auxdata_lookup, NULL);
}

All seems to be ok, only ETH doesn't work. I found the problem -
Micrel PHY driver is inited later than lpc_eth driver and it doesn't bind
to the eth.
I solved it by ugly hack - set status=disabled for eth in dts and adding:

static struct of_device_id __initdata of_ids[] = {
 { .compatible = nxp,lpc-eth },{}
};
static void __init devik_late_init(void) // errorchecking omited
{
struct device_node *np;
np = of_find_compatible_node(NULL, NULL, nxp,lpc-eth);
struct property *p = of_find_property(np,status,NULL);
of_remove_property(np,p);
of_node_clear_flag(np, OF_POPULATED);
of_platform_bus_probe(np,of_ids,NULL);
}

Other solutiuon is to make it module a load later (we prefer no modules 
here),

or editing lpc_eth.c to register in device_initcall_sync.

Is there some better solution for the bug ?

devik
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Re: [PATCH 2.6.24 1/1] sch_htb: fix "too many events" situation

[Martin Devera]

David Miller wrote:

From: Martin Devera <[EMAIL PROTECTED]>
Date: Mon, 18 Feb 2008 09:03:52 +0100


aha, ok, I'm not so informed about crossplatform issues.
I was also thining about looking at jiffies value and stop once
it is startjiffy+2, but with NO_HZ introduction, are jiffies
still incremented ?


There should always be at least once cpu tasked with incrementing
jiffies.  Lots of stuff would break if not :-)



Aha ok, so that when (at least one) cpu is busy then I can count on
jiffies incrementing via do_timer, can't I ?
So that I'd remove the loop limit altogether but limiting it to
1 or 2 jiffies to prevent livelock.
Like
max_jiff = jiffies+2; /* not +1 at we could be at +0. now */
while (jiffieshttp://vger.kernel.org/majordomo-info.html
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Re: [PATCH 2.6.24 1/1] sch_htb: fix "too many events" situation

[Martin Devera]

up to single jiffy interval and then delay remainder to other
jiffy.

Signed-off-by: Martin Devera <[EMAIL PROTECTED]>


I think we would be wise to use something other than loops_per_jiffy.

Depending upon the loop calibration method used by a particular
architecture it can me one of many different things.

Some platforms don't even make use of it and thus leave it at it's


aha, ok, I'm not so informed about crossplatform issues.
I was also thining about looking at jiffies value and stop once
it is startjiffy+2, but with NO_HZ introduction, are jiffies
still incremented ?
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Re: [PATCH 2.6.24 1/1] sch_htb: fix too many events situation

[Martin Devera]

up to single jiffy interval and then delay remainder to other
jiffy.

Signed-off-by: Martin Devera [EMAIL PROTECTED]


I think we would be wise to use something other than loops_per_jiffy.

Depending upon the loop calibration method used by a particular
architecture it can me one of many different things.

Some platforms don't even make use of it and thus leave it at it's


aha, ok, I'm not so informed about crossplatform issues.
I was also thining about looking at jiffies value and stop once
it is startjiffy+2, but with NO_HZ introduction, are jiffies
still incremented ?
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Re: [PATCH 2.6.24 1/1] sch_htb: fix too many events situation

[Martin Devera]

David Miller wrote:

From: Martin Devera [EMAIL PROTECTED]
Date: Mon, 18 Feb 2008 09:03:52 +0100


aha, ok, I'm not so informed about crossplatform issues.
I was also thining about looking at jiffies value and stop once
it is startjiffy+2, but with NO_HZ introduction, are jiffies
still incremented ?


There should always be at least once cpu tasked with incrementing
jiffies.  Lots of stuff would break if not :-)



Aha ok, so that when (at least one) cpu is busy then I can count on
jiffies incrementing via do_timer, can't I ?
So that I'd remove the loop limit altogether but limiting it to
1 or 2 jiffies to prevent livelock.
Like
max_jiff = jiffies+2; /* not +1 at we could be at +0. now */
while (jiffiesmax_jiff) do_hard_potentionaly_long_work();
if (more_work) schedule_to_next_jiffie();

This will keep event queue work load under 66% of system load which
seems reasonable to me.

Would you accept such solution ?
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[PATCH 2.6.24 1/1] sch_htb: fix "too many events" situation

[Martin Devera]

From: Martin Devera <[EMAIL PROTECTED]>

HTB is event driven algorithm and part of its work is to apply
scheduled events at proper times. It tried to defend itself from
livelock by processing only limited number of events per dequeue.
Because of faster computers some users already hit this hardcoded
limit.
This patch uses loops_per_jiffy variable to limit event processing
up to single jiffy interval and then delay remainder to other
jiffy.

Signed-off-by: Martin Devera <[EMAIL PROTECTED]>
---
BTW, from my measurement is seems that value 500 was good one
for my first 600MHz machine :-)
Maybe I can make something self-converging (using tasklets probably)
but I'm not sure if it is worth of the complexity.

--- a/net/sched/sch_htb.c   2008-02-14 22:56:48.0 +0100
+++ b/net/sched/sch_htb.c   2008-02-14 23:37:02.0 +0100
@@ -704,13 +704,17 @@ static void htb_charge_class(struct htb_
  *
  * Scans event queue for pending events and applies them. Returns time of
  * next pending event (0 for no event in pq).
+ * One event costs about 1300 cycles on x86_64, let's be conservative
+ * and round it to 4096. We will allow only loops_per_jiffy/4096 events
+ * in one call to prevent us from livelock.
  * Note: Applied are events whose have cl->pq_key <= q->now.
  */
+#define HTB_EVENT_COST_SHIFTS 12
 static psched_time_t htb_do_events(struct htb_sched *q, int level)
 {
-   int i;
-
-   for (i = 0; i < 500; i++) {
+   int i, max_events = loops_per_jiffy >> HTB_EVENT_COST_SHIFTS;
+   /* <= below is just for case where max_events==0 (unlikely) */
+   for (i = 0; i <= max_events; i++) {
struct htb_class *cl;
long diff;
struct rb_node *p = rb_first(>wait_pq[level]);
@@ -728,9 +732,8 @@ static psched_time_t htb_do_events(struc
if (cl->cmode != HTB_CAN_SEND)
htb_add_to_wait_tree(q, cl, diff);
}
-   if (net_ratelimit())
-   printk(KERN_WARNING "htb: too many events !\n");
-   return q->now + PSCHED_TICKS_PER_SEC / 10;
+   /* too much load - let's continue on next tick */
+   return q->now + PSCHED_TICKS_PER_SEC / HZ;
 }
 
 /* Returns class->node+prio from id-tree where classe's id is >= id. NULL
--
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[PATCH 2.6.24 1/1] sch_htb: fix too many events situation

[Martin Devera]

From: Martin Devera [EMAIL PROTECTED]

HTB is event driven algorithm and part of its work is to apply
scheduled events at proper times. It tried to defend itself from
livelock by processing only limited number of events per dequeue.
Because of faster computers some users already hit this hardcoded
limit.
This patch uses loops_per_jiffy variable to limit event processing
up to single jiffy interval and then delay remainder to other
jiffy.

Signed-off-by: Martin Devera [EMAIL PROTECTED]
---
BTW, from my measurement is seems that value 500 was good one
for my first 600MHz machine :-)
Maybe I can make something self-converging (using tasklets probably)
but I'm not sure if it is worth of the complexity.

--- a/net/sched/sch_htb.c   2008-02-14 22:56:48.0 +0100
+++ b/net/sched/sch_htb.c   2008-02-14 23:37:02.0 +0100
@@ -704,13 +704,17 @@ static void htb_charge_class(struct htb_
  *
  * Scans event queue for pending events and applies them. Returns time of
  * next pending event (0 for no event in pq).
+ * One event costs about 1300 cycles on x86_64, let's be conservative
+ * and round it to 4096. We will allow only loops_per_jiffy/4096 events
+ * in one call to prevent us from livelock.
  * Note: Applied are events whose have cl-pq_key = q-now.
  */
+#define HTB_EVENT_COST_SHIFTS 12
 static psched_time_t htb_do_events(struct htb_sched *q, int level)
 {
-   int i;
-
-   for (i = 0; i  500; i++) {
+   int i, max_events = loops_per_jiffy  HTB_EVENT_COST_SHIFTS;
+   /* = below is just for case where max_events==0 (unlikely) */
+   for (i = 0; i = max_events; i++) {
struct htb_class *cl;
long diff;
struct rb_node *p = rb_first(q-wait_pq[level]);
@@ -728,9 +732,8 @@ static psched_time_t htb_do_events(struc
if (cl-cmode != HTB_CAN_SEND)
htb_add_to_wait_tree(q, cl, diff);
}
-   if (net_ratelimit())
-   printk(KERN_WARNING htb: too many events !\n);
-   return q-now + PSCHED_TICKS_PER_SEC / 10;
+   /* too much load - let's continue on next tick */
+   return q-now + PSCHED_TICKS_PER_SEC / HZ;
 }
 
 /* Returns class-node+prio from id-tree where classe's id is = id. NULL
--
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Re: [PATCH 2.6.15.4 rel.2 1/1] libata: add hotswap to sata_svw

[Martin Devera]

Benjamin Herrenschmidt wrote:

On Tue, 2006-11-28 at 23:22 +, David Woodhouse wrote:

On Thu, 2006-02-16 at 16:09 +0100, Martin Devera wrote:

From: Martin Devera <[EMAIL PROTECTED]>

Add hotswap capability to Serverworks/BroadCom SATA controlers. The
controler has SIM register and it selects which bits in SATA_ERROR
register fires interrupt.
The solution hooks on COMWAKE (plug), PHYRDY change and 10B8B decode 
error (unplug) and calls into Lukasz's hotswap framework.
The code got one day testing on dual core Athlon64 H8SSL Supermicro 
MoBo with HT-1000 SATA, SMP kernel and two CaviarRE SATA HDDs in

hotswap bays.

Signed-off-by: Martin Devera <[EMAIL PROTECTED]>

What became of this?


I might be to blame for not testing it... The Xserve I had on my desk
was too noisy for most of my co-workers so I kept delaying and forgot
about it 


Also the Xserve I have only has one disk, which makes hotplug testing a
bit harder :-)


Unfortunately my box with ht1000 is already deployed. Another similar one should
arrive soon so that I'll retest it.
Just now I've VIA based mobo here - and hotswap is NOT working with it ..

Martin
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Re: [PATCH 2.6.15.4 rel.2 1/1] libata: add hotswap to sata_svw

[Martin Devera]

Benjamin Herrenschmidt wrote:

On Tue, 2006-11-28 at 23:22 +, David Woodhouse wrote:

On Thu, 2006-02-16 at 16:09 +0100, Martin Devera wrote:

From: Martin Devera [EMAIL PROTECTED]

Add hotswap capability to Serverworks/BroadCom SATA controlers. The
controler has SIM register and it selects which bits in SATA_ERROR
register fires interrupt.
The solution hooks on COMWAKE (plug), PHYRDY change and 10B8B decode 
error (unplug) and calls into Lukasz's hotswap framework.
The code got one day testing on dual core Athlon64 H8SSL Supermicro 
MoBo with HT-1000 SATA, SMP kernel and two CaviarRE SATA HDDs in

hotswap bays.

Signed-off-by: Martin Devera [EMAIL PROTECTED]

What became of this?


I might be to blame for not testing it... The Xserve I had on my desk
was too noisy for most of my co-workers so I kept delaying and forgot
about it 


Also the Xserve I have only has one disk, which makes hotplug testing a
bit harder :-)


Unfortunately my box with ht1000 is already deployed. Another similar one should
arrive soon so that I'll retest it.
Just now I've VIA based mobo here - and hotswap is NOT working with it ..

Martin
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Re: Threads are processes that share more

[Martin Devera]

> Threads are processes that share more

BTW is not possible to implement threads as subset of process ?
Like thread list pointed to from task_struct. It'd contain
thread_structs plus another scheduler's data.
The thread could be much smaller than process.

Probably there is another problem I don't see, I'm just
currious whether can it work like this ..

devik

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Re: Threads are processes that share more

[Martin Devera]

 Threads are processes that share more

BTW is not possible to implement threads as subset of process ?
Like thread list pointed to from task_struct. It'd contain
thread_structs plus another scheduler's data.
The thread could be much smaller than process.

Probably there is another problem I don't see, I'm just
currious whether can it work like this ..

devik

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possible deadlock in 2.4.4 sys_getdents ?

[Martin Devera]

Hello all,

after weeks of uptime, 2.4.4 kernel freezed several of
my processes. It seems like deadlock.
I typed "whereis perl" and system got frozen. After quick
look I found that I typed the command while "makedb" script
was running. All processes are on down:
budha:~# ps -A -o pid,cmd,eip,wchan|grep down
 1131 find / /dev/pts  400cd923 down
 5740 ls --color /usr/ 400bb923 down
 5738 whereis perl 400bb79e down

budha:~# ls /proc/1131/fd -l
total 0
lr-x--1 root root 64 Jun 19 14:37 0 -> /dev/null
l-wx--1 root root 64 Jun 19 14:37 1 -> pipe:[2577]
l-wx--1 root root 64 Jun 19 14:37 2 -> pipe:[2558]
lr-x--1 root root 64 Jun 19 14:37 3 -> /
lr-x--1 root root 64 Jun 19 14:37 4 -> /usr/share/man/man1

Now see strace output of whereis:
5738  getdents(5, /* 0 entries */, 3933) = 0
5738  close(5)  = 0
5738  stat("/usr/share/man/man1", {st_mode=S_IFDIR|0755, st_size=22528,
...}) = 
0
5738  open("/usr/share/man/man1", O_RDONLY|O_NONBLOCK|0x1) = 5
5738  fstat(5, {st_mode=S_IFDIR|0755, st_size=22528, ...}) = 0
5738  fcntl(5, F_SETFD, FD_CLOEXEC) = 0
5738  getdents(5, 

It stops at getdents. I don't know how to trace it further down ..
I have to reboot machine and probably will not be able to simulate
it again. Only it is evident that it is possible to hang it up 
and kill -9 doesn't work (uninteruptible sleep).

I hope this helps improve stability.
devik

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possible deadlock in 2.4.4 sys_getdents ?

[Martin Devera]

Hello all,

after weeks of uptime, 2.4.4 kernel freezed several of
my processes. It seems like deadlock.
I typed whereis perl and system got frozen. After quick
look I found that I typed the command while makedb script
was running. All processes are on down:
budha:~# ps -A -o pid,cmd,eip,wchan|grep down
 1131 find / /dev/pts  400cd923 down
 5740 ls --color /usr/ 400bb923 down
 5738 whereis perl 400bb79e down

budha:~# ls /proc/1131/fd -l
total 0
lr-x--1 root root 64 Jun 19 14:37 0 - /dev/null
l-wx--1 root root 64 Jun 19 14:37 1 - pipe:[2577]
l-wx--1 root root 64 Jun 19 14:37 2 - pipe:[2558]
lr-x--1 root root 64 Jun 19 14:37 3 - /
lr-x--1 root root 64 Jun 19 14:37 4 - /usr/share/man/man1

Now see strace output of whereis:
5738  getdents(5, /* 0 entries */, 3933) = 0
5738  close(5)  = 0
5738  stat(/usr/share/man/man1, {st_mode=S_IFDIR|0755, st_size=22528,
...}) = 
0
5738  open(/usr/share/man/man1, O_RDONLY|O_NONBLOCK|0x1) = 5
5738  fstat(5, {st_mode=S_IFDIR|0755, st_size=22528, ...}) = 0
5738  fcntl(5, F_SETFD, FD_CLOEXEC) = 0
5738  getdents(5, 

It stops at getdents. I don't know how to trace it further down ..
I have to reboot machine and probably will not be able to simulate
it again. Only it is evident that it is possible to hang it up 
and kill -9 doesn't work (uninteruptible sleep).

I hope this helps improve stability.
devik

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oops in kswapd with 2.4.4 on gigabyte MB

[Martin Devera]

Hello,
I installed 2.4.4 on host which was running win95 (without problems).
It is MB Gigabyte GA6BXC with one PCI net card (J2585B) and 128MB memory.
CPU is Pentium III (Katmai) fam.6 model 7 @ 450MHz.
One 15G IDE HDD.
After approx 1hr it gines me oops. I used ksymoops and result is
attached. 
The problem seems to be related to this particular MB plus Linux. MB
works for Win95 and the same Linux instalation works with another MB/CPU.
If someone wants to look at it .. it would be nice. If not .. dont worry.

thanks, devik


ksymoops 2.4.1 on i686 2.4.4.  Options used
 -v /boot/vmlinux (specified)
 -k /proc/ksyms (default)
 -l /proc/modules (default)
 -o /lib/modules/2.4.4/ (default)
 -m /usr/src/linux/System.map (default)
 -1

Unable to handle kernel paging request at virtual address a68b11c0
c013f161
*pde = 
Oops: 0002
CPU:0
EIP:0010:[]
Using defaults from ksymoops -t elf32-i386 -a i386
EFLAGS: 00010216
eax: c0287104   ebx: c7c783c0   ecx: c7c78560   edx: a68b11c0
esi: c6e11140   edi: 0fb1   ebp:    esp: c7f9dfac
ds: 0018   es: 0018   ss: 0018
Process kswapd (pid: 3, stackpage=c7f9d000)
Stack: 00010f00 0004 0182 c013f4e1 13a5 c0127eb7 0006 0004 
   00010f00 c0238a17 c7f9c239 0008e000 c0127f3b 0004  c123ffbc 
    c0105454  0078 c029dfc0 
Call Trace: [] [] [] [] 
Code: 89 02 89 09 89 49 04 8d 59 e0 f6 43 58 08 74 1f 80 63 58 f7 

>>EIP; c013f161<=
Trace; c013f4e1 
Trace; c0127eb7 
Trace; c0127f3b 
Trace; c0105454 
Code;  c013f161 
 <_EIP>:
Code;  c013f161<=
   0:   89 02 mov%eax,(%edx)   <=
Code;  c013f163 
   2:   89 09 mov%ecx,(%ecx)
Code;  c013f165 
   4:   89 49 04  mov%ecx,0x4(%ecx)
Code;  c013f168 
   7:   8d 59 e0  lea0xffe0(%ecx),%ebx
Code;  c013f16b 
   a:   f6 43 58 08   testb  $0x8,0x58(%ebx)
Code;  c013f16f 
   e:   74 1f je 2f <_EIP+0x2f> c013f190 
Code;  c013f171 
  10:   80 63 58 f7   andb   $0xf7,0x58(%ebx)



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oops in kswapd with 2.4.4 on gigabyte MB

[Martin Devera]

Hello,
I installed 2.4.4 on host which was running win95 (without problems).
It is MB Gigabyte GA6BXC with one PCI net card (J2585B) and 128MB memory.
CPU is Pentium III (Katmai) fam.6 model 7 @ 450MHz.
One 15G IDE HDD.
After approx 1hr it gines me oops. I used ksymoops and result is
attached. 
The problem seems to be related to this particular MB plus Linux. MB
works for Win95 and the same Linux instalation works with another MB/CPU.
If someone wants to look at it .. it would be nice. If not .. dont worry.

thanks, devik


ksymoops 2.4.1 on i686 2.4.4.  Options used
 -v /boot/vmlinux (specified)
 -k /proc/ksyms (default)
 -l /proc/modules (default)
 -o /lib/modules/2.4.4/ (default)
 -m /usr/src/linux/System.map (default)
 -1

Unable to handle kernel paging request at virtual address a68b11c0
c013f161
*pde = 
Oops: 0002
CPU:0
EIP:0010:[c013f161]
Using defaults from ksymoops -t elf32-i386 -a i386
EFLAGS: 00010216
eax: c0287104   ebx: c7c783c0   ecx: c7c78560   edx: a68b11c0
esi: c6e11140   edi: 0fb1   ebp:    esp: c7f9dfac
ds: 0018   es: 0018   ss: 0018
Process kswapd (pid: 3, stackpage=c7f9d000)
Stack: 00010f00 0004 0182 c013f4e1 13a5 c0127eb7 0006 0004 
   00010f00 c0238a17 c7f9c239 0008e000 c0127f3b 0004  c123ffbc 
    c0105454  0078 c029dfc0 
Call Trace: [c013f4e1] [c0127eb7] [c0127f3b] [c0105454] 
Code: 89 02 89 09 89 49 04 8d 59 e0 f6 43 58 08 74 1f 80 63 58 f7 

EIP; c013f161 prune_dcache+21/13c   =
Trace; c013f4e1 shrink_dcache_memory+21/30
Trace; c0127eb7 do_try_to_free_pages+5f/7c
Trace; c0127f3b kswapd+67/f4
Trace; c0105454 kernel_thread+28/38
Code;  c013f161 prune_dcache+21/13c
 _EIP:
Code;  c013f161 prune_dcache+21/13c   =
   0:   89 02 mov%eax,(%edx)   =
Code;  c013f163 prune_dcache+23/13c
   2:   89 09 mov%ecx,(%ecx)
Code;  c013f165 prune_dcache+25/13c
   4:   89 49 04  mov%ecx,0x4(%ecx)
Code;  c013f168 prune_dcache+28/13c
   7:   8d 59 e0  lea0xffe0(%ecx),%ebx
Code;  c013f16b prune_dcache+2b/13c
   a:   f6 43 58 08   testb  $0x8,0x58(%ebx)
Code;  c013f16f prune_dcache+2f/13c
   e:   74 1f je 2f _EIP+0x2f c013f190 prune_dcache+50/13c
Code;  c013f171 prune_dcache+31/13c
  10:   80 63 58 f7   andb   $0xf7,0x58(%ebx)



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