by the drivers. The framework also provides helpers to
> sync the data written to the pages with appropriate directions.
>
> This will be later used by the TMC ETR SG unit.
>
> Cc: Mathieu Poirier
> Signed-off-by: Suzuki K Poulose
> ---
> ---
> drivers/hwtracing/cores
ge with pointers to data.
>
> The code takes care of handling the system page size which could
> be different than 4K. So we could end up putting multiple ETR
> SG tables in a single system page, vice versa for the data pages.
>
> Cc: Mathieu Poirier
> Signed-off-by: Suzuki K P
e table address.
> This works as the TMC doesn't mandate that the page table
> base address should be 4K page aligned.
>
> Cc: Mathieu Poirier
> Signed-off-by: Suzuki K Poulose
> ---
> drivers/hwtracing/coresight/coresight-tmc-etr.c | 159
> +---
On 2 November 2017 at 06:00, Suzuki K Poulose wrote:
> On 01/11/17 23:47, Mathieu Poirier wrote:
>>
>> On Thu, Oct 19, 2017 at 06:15:42PM +0100, Suzuki K Poulose wrote:
>>>
>>> Make the ETR SG table Circular buffer so that we could start
>>> at any of
on configured the trace buffer size. Also, since ETR will use the
> new infrastructure to manage the buffer, we can get rid of some
> of the members in the tmc_drvdata and clean up the fields a bit.
>
> Cc: Mathieu Poirier
> Signed-off-by: Suzuki K Poulose
> ---
> dr
On Thu, Oct 19, 2017 at 06:15:44PM +0100, Suzuki K Poulose wrote:
> Now that we can dynamically switch between contiguous memory and
> SG table depending on the trace buffer size, provide the support
> for selecting an appropriate buffer size.
>
> Cc: Mathieu Poirier
> Signe
On Thu, Oct 19, 2017 at 06:15:46PM +0100, Suzuki K Poulose wrote:
> Track if the ETR is dma-coherent or not. This will be useful
> in deciding if we should use software buffering for perf.
>
> Cc: Mathieu Poirier
> Signed-off-by: Suzuki K Poulose
> ---
> drivers/hwtracin
ffer from a sysfs mode
>even if the etr is now used in perf mode, without disrupting the
>current session.)
>
> Towards this, we introduce a sysfs specific data which will hold the
> etr_buf used for sysfs mode of operation, controlled solely by the
> sysfs mode handli
ollow you with "... restoring a session in perf mode ...".
When operating from the perf interface all the memory allocated for a session is
cleanup after, there is no re-using of memory as in sysFS.
> Get rid of this step, if someone wants to debug, they can always
> add it as and when ne
.@vger.kernel.org
> Cc: Tommaso Cucinotta
> Cc: Mathieu Poirier
> ---
Please add a short description for your change, even if it is trivial.
> Documentation/scheduler/sched-deadline.txt | 13 ++---
> 1 file changed, 10 insertions(+), 3 deletions(-)
>
> diff --g
On 3 November 2017 at 04:02, Suzuki K Poulose wrote:
> On 02/11/17 17:48, Mathieu Poirier wrote:
>>
>> On Thu, Oct 19, 2017 at 06:15:43PM +0100, Suzuki K Poulose wrote:
>>>
>>> At the moment we always use contiguous memory for TMC ETR tracing
>>> when
On 3 November 2017 at 04:10, Suzuki K Poulose wrote:
> On 02/11/17 20:36, Mathieu Poirier wrote:
>>
>> On Thu, Oct 19, 2017 at 06:15:49PM +0100, Suzuki K Poulose wrote:
>>>
>>> We zero out the entire trace buffer used for ETR before it
>>> is enabled, for
On 3 November 2017 at 04:08, Suzuki K Poulose wrote:
> On 02/11/17 20:26, Mathieu Poirier wrote:
>>
>> On Thu, Oct 19, 2017 at 06:15:47PM +0100, Suzuki K Poulose wrote:
>>>
>>> Since the ETR could be driven either by SYSFS or by perf, it
>>> becomes com
using the term backend simply write continuous buffer or SG mode. It
is a lot less cryptic that way.
> if it doesn't, we should fall back to using in built SG mechanism,
> where we can rotate the SG table by making some adjustments in the
> page table.
>
> Cc: Mathieu Poiri
e table address.
> This works as the TMC doesn't mandate that the page table
> base address should be 4K page aligned.
>
> Cc: Mathieu Poirier
> Signed-off-by: Suzuki K Poulose
> ---
> drivers/hwtracing/coresight/coresight-tmc-etr.c | 159
> +---
heir buffer gets full. Those are coming
and when we do need to support them we'll find ourselves splitting the update
and reset operation again.
See comment below.
>
> Cc: Mathieu Poirier
> Signed-off-by: Suzuki K Poulose
> ---
> drivers/hwtracing/coresight/coresig
On 19 October 2017 at 09:45, Suzuki K Poulose wrote:
> Add ARM Cortex A-73 ETM PIDs to the known ETM ips. While at it
> also add description of the CPU to which the ETM belongs, to make
> it easier to identify the ETM devices.
>
> Cc: Mathieu Poirier
> Signed-off-by
On Thu, Oct 19, 2017 at 06:15:39PM +0100, Suzuki K Poulose wrote:
> Right now we open code filling the trace buffer with synchronization
> packets when the circular buffer wraps around in different drivers.
> Move this to a common place.
>
> Cc: Mathieu Poirier
> Cc: Mike Leac
Good morning,
Please consider the following patches for merging in the 4.4 cycle.
Thanks,
Mathieu
Chunyan Zhang (1):
Coresight: ETMv4: Prevent TRCRSCTLR0&1 from being accessed
Mathieu Poirier (5):
coresight: fixing typographical error
coresight: adding comments to remove ambig
By adding the function name at the beginning of the error
message there is no doubt as to where the failing condition
occurred.
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm3x.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers
Tracing gets enabled _for_ a source rather than _from_ a source.
Signed-off-by: Mathieu Poirier
---
include/linux/coresight.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index c69e1b932809..a7cabfa23b55 100644
--- a
ource selection pair, 1 indicates two pairs, and so on ...
So, the total number of resource selection control registers which we can
access is (TRCIDR4.NUMRSPAIR * 2)
Signed-off-by: Chunyan Zhang
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm4x.c | 22 +++
Add comment to function coresight_enable_path() to make
sure there is no misunderstanding about what the code does.
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight.c
b
ned-off-by: Mathieu Poirier
---
.../ABI/testing/sysfs-bus-coresight-devices-etm3x | 77 ++--
drivers/hwtracing/coresight/coresight-etm3x.c | 100 +++--
2 files changed, 121 insertions(+), 56 deletions(-)
diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-device
Without access to the device tree, it is impossible to know
what CPU a tracer is affined to. As such adding a new sysFS
interface to convey the information.
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm3x.c | 13 +
1 file changed, 13 insertions
On 27 August 2015 at 22:10, Chunyan Zhang wrote:
> 1. TRCRSCTLRn - Resource Selection Control Registers n=0~1 are reserved,
>we shouldn't access them.
> 2. The max number of 'n' here is defined in TRCIDR4.NUMRSPAIR whoes value
>indicates the number of resource selection *pairs*, and 0 indi
justed
> to just include moduleparam.h for that purpose.
>
> Since module_amba_driver() uses the same init level priority as
> builtin_amba_driver() the init ordering remains unchanged with
> this commit.
>
> Cc: Mathieu Poirier
> Cc: linux-arm-ker...@lists.in
There is no need to use the event enable's "always false" event to
stop trace collection. For that purpose setting the programming bit
(ETMCR:10) is enough.
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm3x.c | 3 ---
1 file changed, 3 deletions(-
ously.
* Changed sink_ops::unset_buffer() to sink_ops::reset_buffer().
* Moves ETM's sysFS interface from driver core to dedicated file.
* Removed spinlock in "etm_cpu_id()".
* Aggregated PMU driver pieces in a single patch.
* Added user space changes and rebased everything to
Adding an API to deal with runtime PM (and anything else)
that might be required by a tracer before and after it is
to be used by the Perf framework.
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm3x.c | 12
include/linux/coresight.h
Adding new define for auxiliary traces collected by ETM tracers.
Signed-off-by: Mathieu Poirier
---
tools/perf/util/auxtrace.c | 1 +
tools/perf/util/auxtrace.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/tools/perf/util/auxtrace.c b/tools/perf/util/auxtrace.c
index 430df9575dbe
There is really no point having two functions to take care
of doing the initials tracer configuration. As such moving
everything to 'etm_set_default()'.
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm3x.c | 37 ++-
1 file c
Adding new mode to limit tracing to kernel or user space.
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm.h| 9 +++-
.../hwtracing/coresight/coresight-etm3x-sysfs.c| 4 ++
drivers/hwtracing/coresight/coresight-etm3x.c | 60
Keep track of enabled sink buffers as a path between source
and sinks is being built. That way sinks associated to a
source can be accessed quickly.
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-priv.h | 3 ++-
drivers/hwtracing/coresight/coresight.c | 16
Moving etm_drvdata::enable to an atomic type that gives the
'state' of the tracer, i.e disabled, handled via sysFS or Perf.
That way a tracer can't be used if it is already marshaled by
another subsystem.
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/
Adding the required mechanic allowing 'perf list pmu' to
discover coresight ETM/PTM tracers.
Signed-off-by: Mathieu Poirier
---
tools/perf/arch/arm/util/Build | 2 ++
tools/perf/arch/arm/util/pmu.c | 18 ++
tools/perf/builtin-inject.c| 2 +-
tools/perf/builti
Coresight ETMs are IP blocks allowing to perform HW assisted tracing
on a CPU core. This patch introduce the required auxiliary API
functions allowing the perf core to interact with a tracer.
Signed-off-by: Mathieu Poirier
---
tools/perf/arch/arm/util/Build | 2 +-
tools/perf/arch/arm
Adding an X86 specific flag to split AUX components that are
generic and specific to architectures. That way the auxiliary
area mechanic can be compiled in for other architecture without
including X86 specific code.
Signed-off-by: Mathieu Poirier
---
tools/perf/arch/x86/util/Build | 6
cpu__max_cpu().
Signed-off-by: Mathieu Poirier
---
tools/perf/util/cpumap.c | 2 +-
tools/perf/util/cpumap.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/tools/perf/util/cpumap.c b/tools/perf/util/cpumap.c
index 3667e2123e5b..97ef46e4a0f6 100644
--- a/tools/perf/util/cpumap.c
parameter into account.
Signed-off-by: Mathieu Poirier
---
tools/perf/arch/x86/util/intel-bts.c | 4 +++-
tools/perf/arch/x86/util/intel-pt.c | 4 +++-
tools/perf/util/auxtrace.c | 7 ---
tools/perf/util/auxtrace.h | 6 --
4 files changed, 14 insertions(+), 7 deletion
Other perf tools may want access to the event source device
directory. As such moving the path definition to pmu.h for
easy inclusion by other clients.
Signed-off-by: Mathieu Poirier
---
tools/perf/util/pmu.c | 2 --
tools/perf/util/pmu.h | 1 +
2 files changed, 1 insertion(+), 2 deletions
Adding a new section giving information on how coresight has been
integrated with the perf subsystem along with a general idea of how
to control tracing from the perf tool cmd line.
Signed-off-by: Mathieu Poirier
---
Documentation/trace/coresight.txt | 138
Implementing buffer API to update the location of the ETB
internal ring buffer once a trace session has ended.
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etb10.c | 128 ++
include/linux/coresight.h | 14 ++-
2 files
Perf is a well known and used tool for performance monitoring
and much more. A such it is an ideal condaditate for integration
with coresight based HW tracing.
This patch introduces a PMU that represent a coresight tracer to
the Perf core.
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing
Implementing perf related APIs to activate and terminate
a trace session. More specifically dealing with the sink
buffer's internal mechanic along with perf's API to start
and stop interactions with the ring buffers.
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight
Adding an ETB10 specific auxiliary area setup operation to be
used by the perf framework when events are initialised.
Part of this operation involves modeling the mmap'ed area based
on the specific ways a sink buffer gathers information.
Signed-off-by: Mathieu Poirier
---
drivers/hwtr
modification.
Signed-off-by: Mathieu Poirier
---
arch/x86/kernel/cpu/perf_event_intel_bts.c | 4 +++-
arch/x86/kernel/cpu/perf_event_intel_pt.c | 5 +++--
include/linux/perf_event.h | 2 +-
kernel/events/ring_buffer.c| 2 +-
4 files changed, 8 insertions(+), 5
Moving to use local atomic operations to take advantage of the
lockless implementation, something that will come handy when
the ETB is accessed from the Perf subsystem.
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etb10.c | 6 +++---
1 file changed, 3 insertions
That way a path can be built outside of the core framework,
something useful when a PMU is initialised from the perf
subsystem.
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-priv.h | 3 +++
drivers/hwtracing/coresight/coresight.c | 5 ++---
2 files changed, 5
That way traces can be enable and disabled automatically
from the Perf subystem using the PMU abstraction.
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm3x.c | 50 ---
include/linux/coresight.h | 4 +++
2 files changed
,
the possibility of associating a tracer with a configuration is
also provided. As such Perf can assign session configuration to
tracers as it sees fit.
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm3x.c | 70 +--
include/linux/coresi
Changing default configuration to include the entire address
range rather than just the kernel. That way traces are more
inclusive and it is easier to narrow down if needed.
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm.h | 2 ++
drivers/hwtracing/coresight
Adding an interface to lookup the CPU a tracer has been affined
to along with a source operation allowing external customers to
access it.
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm3x.c | 8
include/linux/coresight.h | 3 +++
2
When integrating coresight with Perf, it is important to
clearly identify which operations are used by sysFS and
which ones by Perf.
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm3x.c | 8
drivers/hwtracing/coresight/coresight-etm4x.c | 8
SysFS entries are big enough to justify their own file.
As such moving all sysFS related declarations to a dedicated
location.
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/Makefile |3 +-
drivers/hwtracing/coresight/coresight-etm.h|4
ifting all the code affected by this new
arrangement. No loss or gain of functionality (other than what is
mentioned above) is introduced by this patch.
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm.h| 102 ++---
.../hwtracing/coresight/coresight-etm3x-sysfs.c
Moving functions etm_readl/writel to file "coresight-etm.h"
for access by code outside of the main ETM3x driver.
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm.h | 29 +++
drivers/hwtracing/coresight/coresight-et
while saving
one call to 'smp_call_function_single()'.
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm3x.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c
b/drivers/hwtracing/coresight/coresight-etm3x
On 19 October 2015 at 07:44, Alexander Shishkin
wrote:
> Mathieu Poirier writes:
>
>> Adding an ETB10 specific auxiliary area setup operation to be
>> used by the perf framework when events are initialised.
>>
>> Part of this operation involves modeling the mmap&#x
On 19 October 2015 at 09:37, Alexander Shishkin
wrote:
> Mathieu Poirier writes:
>
>> +static int etm_event_pmu_start(struct perf_event *event)
>> +{
>> + int cpu, ret;
>> + cpumask_t mask;
>> + struct coresight_device *csdev;
>> +
>>
On 20 October 2015 at 03:56, Alexander Shishkin
wrote:
> Mathieu Poirier writes:
>
>> Implementing perf related APIs to activate and terminate
>> a trace session. More specifically dealing with the sink
>> buffer's internal mechanic along with perf's API to s
On 20 October 2015 at 03:34, Alexander Shishkin
wrote:
> Mathieu Poirier writes:
>
>> +static void *etm_setup_aux(struct perf_event *event, void **pages,
>> +int nr_pages, bool overwrite)
>> +{
>> + int cpu;
>> + cpumask_t *
m.
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight.c
b/drivers/hwtracing/coresight/coresight.c
index e25492137d8b..93738dfbf631 100644
--- a/drivers/hwtracing
On 30 September 2015 at 02:52, Alexander Shishkin
wrote:
> Mathieu Poirier writes:
>
>> This patchset aims to integrate configuration and control of
>> the Coresight tracers with the perf sub-system.
>>
>> The goal is to use PMUs to represent tracers and the auxi
On 30 September 2015 at 03:01, Alexander Shishkin
wrote:
> Mathieu Poirier writes:
>
>> This patchset aims to integrate configuration and control of
>> the Coresight tracers with the perf sub-system.
>>
>> The goal is to use PMUs to represent tracers and the auxi
On 30 September 2015 at 03:58, Alexander Shishkin
wrote:
> Mathieu Poirier writes:
>
>> -static void etm_enable_hw(void *info)
>> +static void etm_power_up_cpu(void *info)
>> {
>> - int i;
>> - u32 etmcr;
>> - struct etm_drvdata *drvdat
On 30 September 2015 at 05:33, Alexander Shishkin
wrote:
> Mathieu Poirier writes:
>
>> Calling function 'smp_call_function_single()' to unlock the
>> tracer and calling it right after to perform the default
>> initialisation doesn't make sense.
>>
&
On 30 September 2015 at 05:16, Alexander Shishkin
wrote:
> Mathieu Poirier writes:
>
>> Adding an interface to lookup the CPU a tracer has been affined
>> to along with a source operation allowing external customers to
>> access it.
>>
>> Signed-off-by:
On 30 September 2015 at 05:50, Alexander Shishkin
wrote:
> Mathieu Poirier writes:
>
>> +static void *etm_setup_aux(int cpu, void **pages,
>> + int nr_pages, bool overwrite)
>> +{
>> + struct coresight_device *csdev;
>> +
>>
On 30 September 2015 at 04:16, Alexander Shishkin
wrote:
> Mathieu Poirier writes:
>
>> Configure tracers in accordance with the specification conveyed
>> by the perf cmd line tool. For example if only user space is
>> requested, configure the address range com
On 1 October 2015 at 22:53, Alexander Shishkin
wrote:
> Mathieu Poirier writes:
>
>> On 30 September 2015 at 02:52, Alexander Shishkin
>> wrote:
>>> Mathieu Poirier writes:
>>>
>>>> This patchset aims to integrate configuration and control of
>
On 30 September 2015 at 03:43, Alexander Shishkin
wrote:
> Mathieu Poirier writes:
>
>> On 22 September 2015 at 08:29, Alexander Shishkin
>> wrote:
>>> Mathieu Poirier writes:
>>>
>>>> +static void etm_event_destroy(struct perf_event *event)
>
On 1 October 2015 at 22:47, Alexander Shishkin
wrote:
> Mathieu Poirier writes:
>
>> On 30 September 2015 at 05:33, Alexander Shishkin
>> wrote:
>>> Mathieu Poirier writes:
>>>
>>>> Calling function 'smp_call_function_single()' to un
0 of :
> "Arm Coresight System-on-Chip SoC-600 Technical Reference Manual".
>
> Cc: Mathieu Poirier
> Signed-off-by: Suzuki K Poulose
> ---
> drivers/hwtracing/coresight/Kconfig | 11 ++
> drivers/hwtracing/coresight/Makefile| 1 +
> dr
has an "Invalid" previous pointer and the
> next pointer entry points to the second page table if there is one.
> Similarly the last table page has an "Invalid" next pointer to
> indicate the end of the table chain.
>
> Cc: Mathieu Poirier
> Signed-off-by
On Fri, 22 Jun 2018 at 03:01, Suzuki K Poulose wrote:
>
> Hi Mathieu,
>
> On 21/06/18 18:13, Mathieu Poirier wrote:
>
> >> +
> >> +/*
> >> + * catu_populate_table : Populate the given CATU table.
> >> + * The table is always populated as a c
Hi Robert,
Your patch landed in the middle of the merge window and will have to be sent
again rebased on 4.19-rc1 and long with minor fix found below.
Regards,
Mathieu
On Wed, Aug 22, 2018 at 05:03:57PM +0100, Robert Walker wrote:
> This patch adds support for generating instruction samples fro
On Mon, 13 Aug 2018 at 11:46, Kim Phillips wrote:
>
> On Wed, 18 Jul 2018 15:48:00 -0600
> Mathieu Poirier wrote:
>
> > This set adds the capability to communiate event specific configuration
> > to the PMU kernel driver using an ioctl(). The functionatlity is made
>
On Mon, 20 Aug 2018 at 08:36, Suzuki K Poulose wrote:
>
> On 08/20/2018 03:22 PM, Kim Phillips wrote:
> > On Mon, 20 Aug 2018 11:03:03 +0100
> > Suzuki K Poulose wrote:
> >
> >> On 08/16/2018 08:28 PM, Mathieu Poirier wrote:
> >>> On W
On Fri, Jul 27, 2018 at 11:15:28AM +0100, Suzuki K Poulose wrote:
> Coresight uses DT graph bindings to describe the connections of the
> components. However we have some undocumented usage of the bindings
> to describe some of the properties of the connections.
>
> The coresight driver needs to k
x){+.+.}, at:
perf_event_ctx_lock_nested+0xf8/0x1f0
This is fixed by working with the cpu_present_mask, avoinding at the same
the need to use get/put_online_cpus() that triggers lockdep.
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm-perf.c | 39 +--
Adding a new IOCTL command to communicate PMU specific configuration to
PMU kernel drivers. This can be anything a PMU might need for
configuration that doesn't fit in the perf_event_attr structure, such
as the CoreSight sink to use for a session.
Signed-off-by: Mathieu Poirier
---
in
Using sysFS to communicate sink information for a trace session doesn't
work when more than one CPU is involved in the scenario. As such
communicate the sink information to each event by using the SET_DRV_CONFIG
ioctl command.
Signed-off-by: Mathieu Poirier
---
tools/perf/arch/arm/ut
perf_event_process_drv_config() (Jiri)
. Reordered data copy in perf_event_set_drv_config() (Jiri)
. Went from 2 to 1 step driver configuration process (Alex)
. Moved structure name "perf_drv_config" to "pmu_drv_config".
V1: https://lkml.org/lkml/2018/7/2/1008
Mathieu Poirier (7):
perf
-off-by: Mathieu Poirier
---
tools/perf/util/evsel.c | 7 +++
tools/perf/util/evsel.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c
index 94fce4f537e9..534aca4c642c 100644
--- a/tools/perf/util/evsel.c
+++ b/tools/perf/util/evsel.c
entries in sysFS.
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm-perf.c | 134 +--
drivers/hwtracing/coresight/coresight-etm-perf.h | 4 +
2 files changed, 126 insertions(+), 12 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight
Make structure perf_evsel available to the PMU driver configuration code.
That way function perf_evsel__apply_drv_config() can be used from within
that code and information pertaining to the 'perf_evsel_config_term' is
still available.
Signed-off-by: Mathieu Poirier
---
tools/perf/arc
.
Signed-off-by: Mathieu Poirier
---
arch/s390/kernel/perf_cpum_sf.c | 6 +++---
arch/x86/events/intel/bts.c | 4 +++-
arch/x86/events/intel/pt.c | 5 +++--
drivers/hwtracing/coresight/coresight-etm-perf.c | 6 +++---
drivers/perf
d-off-by: Mathieu Poirier
---
include/linux/perf_event.h | 45 ++
kernel/events/core.c | 78 ++
2 files changed, 123 insertions(+)
diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index 1fa1288
On Wed, 18 Jul 2018 at 15:31, Suzuki K Poulose wrote:
>
> Hi Mathieu,
>
> On 07/18/2018 08:43 PM, Mathieu Poirier wrote:
> > When enabling the lockdep mechanic and working with CPU-wide scenarios we
> > get the following console output:
> >
>
> > This is fix
ring buffer once a session completes.
>
> The TMC-ETR would try to match the larger of perf ring buffer
> or the ETR buffer size configured via sysfs, scaling down to
> a minimum limit of 1MB.
>
> Cc: Mathieu Poirier
> Signed-off-by: Suzuki K Poulose
> ---
> drivers/
ack.
>
> Cc: Mathieu Poirier
> Signed-off-by: Suzuki K Poulose
> ---
> drivers/hwtracing/coresight/coresight-etm-perf.c | 14 -
> drivers/hwtracing/coresight/coresight-etm-perf.h | 26
>
> 2 files changed, 26 insertions(+), 14 de
ceed in setting the memory for
the sink but fail in any of the subsequent steps i.e, enabling the rest of the
compoment on the path or the source, the sink is left unchanged.
> Cc: Mathieu Poirier
> Signed-off-by: Suzuki K Poulose
> ---
> drivers/hwtracing/coresight/coresight-etb
[...]
> >
> > Suzuki K Poulose (9):
> > coresight: Document error handling in coresight_register
> > coresight: platform: Refactor graph endpoint parsing
> > coresight: platform: Fix refcounting for graph nodes
> > coresight: platform: Fix leaking device reference
> > coresight: Fix remo
Hello,
On Thu, Jul 26, 2018 at 01:54:40PM +0100, Suzuki K Poulose wrote:
> If the ETB is already enabled in sysfs mode, the ETB reports
> success even if a perf mode is requested. Fix this by checking
> the requested mode.
>
> Cc: Mathieu Poirier
> Signed-off-by
the tracing.
>
> This patch changes to use the cpu_present_mask and tries
> to build path for as much CPUs as possible ignoring the
> failures in building path for some of the CPUs. If ever
> we try to trace on those CPUs, we fail the operation.
>
> Based on a patch from
On Tue, 31 Jul 2018 at 23:45, Stephen Rothwell wrote:
>
> Hi Mathieu,
>
> All but the last 9 commits in the coresight tree have been merged into
> the char-misc tree as different commits (they were sent to Greg as a
> patch series rather than a merge request). Can you please rebase your
> tree in
On Tue, 31 Jul 2018 at 09:40, zhong jiang wrote:
>
> Use ERR_CAT inlined function to replace the ERR_PTR(PTR_ERR). It
> make the code more concise.
>
> Signed-off-by: zhong jiang
> ---
> drivers/hwtracing/coresight/coresight-tmc-etr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> d
On Tue, 31 Jul 2018 at 15:32, Suzuki K Poulose wrote:
>
> On 07/31/2018 06:07 PM, Mathieu Poirier wrote:
> > Hello,
> >
> > On Thu, Jul 26, 2018 at 01:54:40PM +0100, Suzuki K Poulose wrote:
> >> If the ETB is already enabled in sysfs mode, the ETB reports
&g
On Fri, 20 Jul 2018 at 02:43, Suzuki K Poulose wrote:
>
> On 19/07/18 21:07, Mathieu Poirier wrote:
> > On Tue, Jul 17, 2018 at 06:11:39PM +0100, Suzuki K Poulose wrote:
> >> We can always find the sink configuration for a given perf_output_handle.
> >> Add
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