From: Mathieu Poirier
mpoirier@t430:~/work/kernel1$ make C=1 M=drivers/staging/vt6655/
LD drivers/staging/vt6655/built-in.o
CHECK drivers/staging/vt6655/device_main.c
drivers/staging/vt6655/device_main.c:1503:25: warning: incorrect type in
argument 1 (different address spaces
From: Mathieu Poirier
mpoirier@t430:~/work/kernel1$ make C=1 M=drivers/staging/vt6655/
LD drivers/staging/vt6655/built-in.o
CHECK drivers/staging/vt6655/device_main.c
CC [M] drivers/staging/vt6655/device_main.o
CHECK drivers/staging/vt6655/card.c
CC [M] drivers/staging
From: Mathieu Poirier
mpoirier@t430:~/work/kernel1$ make C=1 M=drivers/staging/vt6655/
CHECK drivers/staging/vt6655/mac.c
drivers/staging/vt6655/mac.c:162:6: warning: symbol 'MACvGetShortRetryLimit'
was not declared. Should it be static?
CC [M] drivers/staging/vt6655/mac
On 25 January 2015 at 04:39, Greg KH wrote:
> On Sat, Jan 17, 2015 at 07:04:23PM -0700, mathieu.poir...@linaro.org wrote:
>> From: Mathieu Poirier
>>
>> mpoirier@t430:~/work/kernel1$ make C=1 M=drivers/staging/vt6655/
>> LD drivers/staging/vt6655/built-in.o
&
On 19 March 2015 at 08:23, Alexander Shishkin
wrote:
> Mathieu Poirier writes:
>
>> I forgot to mention in my previous email... I think the hierarchy of
>> our respective tracing module along with the generic-stm probably
>> needs a review.
>>
>> Currentl
On 27 February 2015 at 16:04, Mathieu Poirier
wrote:
> These are the latest coresight patches that I'd like you to consider for
> inclusion in your tree. The set is based on v4.0-rc1.
>
> Thanks,
> Mathieu
>
> Mathieu Poirier (4):
> coresight: making cpu
On 17 March 2015 at 04:37, Alexander Shishkin
wrote:
> Mathieu Poirier writes:
>
>> On 7 March 2015 at 04:35, Alexander Shishkin
>> wrote:
>>> A System Trace Module (STM) is a device exporting data in System Trace
>>> Protocol (STP) format as defined by
On 19 March 2015 at 16:27, Greg KH wrote:
> On Thu, Mar 19, 2015 at 04:02:02PM -0600, Mathieu Poirier wrote:
>> Keeping drivers related to HW tracing on ARM, i.e coresight,
>> under "drivers/coresight" doesn't make sense when other
>> architectures start
On 20 March 2015 at 08:53, Alexander Shishkin
wrote:
> Mathieu Poirier writes:
>
>> As promised I worked on a prototype that connects the coresight-stm
>> driver with the generic STM interface you have suggested. Things work
>> quite well and aside from the enhancem
kind can reside, reducing namespace
pollution under "drivers/".
Signed-off-by: Mathieu Poirier
---
Change for v2:
- generated patch with -M option
---
MAINTAINERS | 2 +-
arch/arm/Kconfig.debug
> +
> +[1]
> https://software.intel.com/sites/default/files/managed/d3/3c/intel-th-developer-manual.pdf
> +[2]
> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0444b/index.html
> diff --git a/drivers/Kconfig b/drivers/Kconfig
> index c0cc96bab9..9850ab81cc 100644
> --- a/drivers/K
Please find in this patchset a driver implementation that conforms
to the coresight framework and provide support for the Embedded
Trace Macrocell version 4.
With this driver support for ARM's juno platform can be added to the
list of coresight supported architecture.
Best regards,
Mathieu
Prati
From: Pratik Patel
Adding sysfs entries to access and configure specifics about the
context ID comparator functions.
Signed-off-by: Pratik Patel
Signed-off-by: Mathieu Poirier
---
.../ABI/testing/sysfs-bus-coresight-devices-etm4x | 19 +++
drivers/hwtracing/coresight/coresight-etm4x.c
From: Pratik Patel
Adding sysfs entries to access and configure specifics about the
virtual machine ID comparator functions.
Signed-off-by: Pratik Patel
Signed-off-by: Mathieu Poirier
---
.../ABI/testing/sysfs-bus-coresight-devices-etm4x | 20 +++
drivers/hwtracing/coresight/coresight
From: Pratik Patel
Adding sysfs entries to control the selection of the resources the
trace unit will use as triggers to perform a trace run.
Signed-off-by: Pratik Patel
Signed-off-by: Mathieu Poirier
---
.../ABI/testing/sysfs-bus-coresight-devices-etm4x | 12
drivers/hwtracing
From: Pratik Patel
Adding sysfs entries related to the counter functionality, more specifically
to set, control and reload the counters.
Signed-off-by: Pratik Patel
Signed-off-by: Mathieu Poirier
---
.../ABI/testing/sysfs-bus-coresight-devices-etm4x | 26
drivers/hwtracing/coresight
From: Pratik Patel
This driver manages the CoreSight ETMv4 (Embedded Trace Macrocell) IP block
to support HW assisted tracing on ARMv7 and ARMv8 architectures.
Signed-off-by: Pratik Patel
Signed-off-by: Kaixu Xia
Signed-off-by: Mathieu Poirier
---
.../ABI/testing/sysfs-bus-coresight-devices
/testing/sysfs-bus-coresight-devices-etm4x
index 0f579eb24631..9caf70382088 100644
--- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
+++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
@@ -87,3 +87,36 @@ KernelVersion: 4.01
Contact: Mathieu Poirier
-off-by: Mathieu Poirier
---
.../ABI/testing/sysfs-bus-coresight-devices-etm4x | 61 +++
drivers/hwtracing/coresight/coresight-etm4x.c | 117 +
2 files changed, 178 insertions(+)
diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
b
From: Pratik Patel
Adding sysfs entries to configure:
. global timestamp.
. how often trace synchronisation occur.
. the threashold value for cycle counting.
. branch and broadcasting regions.
Signed-off-by: Pratik Patel
Signed-off-by: Mathieu Poirier
---
.../ABI/testing/sysfs-bus-coresight
From: Pratik Patel
Adding sysfs entries to access the sequencers related registers,
more specifically the sequencer state, the sequencer state
transition and the sequencer reset control registers.
Signed-off-by: Pratik Patel
Signed-off-by: Mathieu Poirier
---
.../ABI/testing/sysfs-bus
.
Signed-off-by: Pratik Patel
Signed-off-by: Mathieu Poirier
---
.../ABI/testing/sysfs-bus-coresight-devices-etm4x | 25 ++
drivers/hwtracing/coresight/coresight-etm4x.c | 423 +
2 files changed, 448 insertions(+)
diff --git a/Documentation/ABI/testing/sysfs-bus
From: Pratik Patel
Adding sysfs entries to control the ViewInst register's event
selector along with secure and non-secure exception level
instruction tracing.
Signed-off-by: Pratik Patel
Signed-off-by: Mathieu Poirier
---
.../ABI/testing/sysfs-bus-coresight-devices-etm4x
Adding compatible string for new coresight ETMv4 tracer.
Signed-off-by: Mathieu Poirier
---
Documentation/devicetree/bindings/arm/coresight.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/coresight.txt
b/Documentation/devicetree/bindings/arm
On 23 April 2015 at 09:08, Christopher Covington wrote:
> Hi Mathieu,
>
> On 04/22/2015 06:40 PM, Mathieu Poirier wrote:
>> From: Pratik Patel
>>
>> Adding sysfs entries to access and configure specifics about the
>> context ID comparator functions.
>>
&g
On 30 March 2015 at 08:19, Alexander Shishkin
wrote:
> Mathieu Poirier writes:
>
>> Hey Alex,
>
> Hi Mathieu,
>
>> Have a look at the following patch and see if you agree with my approach.
>> If so
>> simply add the code to a third version.
>
> Greg
On 30 March 2015 at 08:04, Alexander Shishkin
wrote:
> Mathieu Poirier writes:
>
>> +static int stm_send(void *addr, const void *data, u32 size)
>> +{
>> + u32 len = size;
>> +
>> + if (((unsigned long)data & 0x1) && (size >= 1))
kind can reside, reducing namespace
pollution under "drivers/".
Signed-off-by: Mathieu Poirier
---
MAINTAINERS | 2 +-
arch/arm/Kconfig.debug | 2 +-
arch/arm64/Kconfig.debug
Compiling coresight drivers with a 64-bit compiler highlights a couple
of formatting issues, which are fixed by this patch.
Signed-off-by: Mathieu Poirier
---
drivers/coresight/coresight-etb10.c | 4 ++--
drivers/coresight/coresight-tmc.c | 4 ++--
2 files changed, 4 insertions(+), 4
From: Kaixu Xia
The coresight-default-sink configuration option has been
removed from the framework. As such remove it from DT and bindings.
Signed-off-by: Kaixu Xia
Signed-off-by: Mathieu Poirier
---
Documentation/devicetree/bindings/arm/coresight.txt | 1 -
arch/arm/boot/dts/hip04.dtsi
Signed-off-by: Mathieu Poirier
---
Documentation/trace/coresight.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/trace/coresight.txt
b/Documentation/trace/coresight.txt
index 02361552a3ea..77d14d51a670 100644
--- a/Documentation/trace/coresight.txt
+++ b
From: Xia Kaixu
>From the TMC TRM, the ETF can be configured as buffer mode, so ETF can
be a sink type.
Signed-off-by: Xia Kaixu
Signed-off-by: Mathieu Poirier
---
drivers/coresight/coresight.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/coresi
Most CoreSight blocks are 64-bit ready. As such move configuration
entries from "arch/arm/Kconfig.config" to the driver's subdirectory
and source the newly created Kconfig from architecture specific
Kconfig.debug files.
Signed-off-by: Mathieu Poirier
Acked-by: Catalin Marinas
Knowing the state of various control register is always
useful for degging and tuning. As such add an entry in
sysfs that expose to userspace the most important registers.
Signed-off-by: Mathieu Poirier
---
drivers/coresight/coresight-tmc.c | 56 +++
1 file
Function "get_logical_index()" is not available on arm64.
Instead of adding the function simply using "of_get_cpu_node()" and
comparing the return value with cpu handles yields the same
result.
Signed-off-by: Mathieu Poirier
---
drivers/coresight/of_coresight.c | 18 ++
/1503.2/04095.html
[2]. http://lkml.iu.edu/hypermail/linux/kernel/1503.2/04716.html
Kaixu Xia (1):
coresight: remove the unnecessary configuration coresight-default-sink
Mathieu Poirier (6):
coresight: making cpu index lookup arm64 compliant
coresight: fixing compilation warnings picked up by
Adding Al Grant to the conversation - his knowledge on HW tracing for
the ARM architecture is definitely an asset for this kind of planning.
Please add him to future patchset as well.
On 31 March 2015 at 09:04, Alexander Shishkin
wrote:
> Mathieu Poirier writes:
>
>> On 30 March 2
+ Al Grant
On 1 April 2015 at 08:27, Mathieu Poirier wrote:
> Adding Al Grant to the conversation - his knowledge on HW tracing for
> the ARM architecture is definitely an asset for this kind of planning.
> Please add him to future patchset as well.
>
> On 31 March 2015 at 0
[...]
> +
> +static int __init stm_core_init(void)
> +{
> + int err;
> +
> + err = class_register(&stm_class);
> + if (err)
> + return err;
> +
> + err = class_register(&stm_source_class);
> + if (err)
> + goto err_stm;
> +
> + err =
On 24 April 2015 at 09:41, Ivan T. Ivanov wrote:
>
> On Wed, 2015-04-22 at 16:40 -0600, Mathieu Poirier wrote:
>>
>
>> +static struct amba_id etm4_ids[] = {
>> + { /* ETM 4.0 - Hi6220 board */
>> + .id = 0x0003b95d,
>&g
On 24 April 2015 at 09:05, Ivan T. Ivanov wrote:
>
> On Wed, 2015-04-22 at 16:40 -0600, Mathieu Poirier wrote:
>> From: Pratik Patel
>>
>> This driver manages the CoreSight ETMv4 (Embedded Trace Macrocell) IP block
>> to support HW assisted tracing on ARMv7 and ARM
On 28 April 2015 at 03:49, David Howells wrote:
> sysrq_register_handler() iterates over platform_sysrq_reset_seq[] using
> ARRAY_SIZE() on sysrq_reset_seq[] as a limit (indeed, the platform array is
> expected to be shorter). gcc-5 spots the potential dereference beyond the end
> of the array an
On 3 April 2015 at 13:51, Olof Johansson wrote:
> On Wed, Mar 25, 2015 at 08:52:11PM +0800, Chunyan Zhang wrote:
>> Support only for ETF, FUNNEL, STM are included currently.
>> Support for ETM, TPIU and the replicator linked to it are not included in
>> this version patch.
>>
>> Signed-off-by: Chu
On 27 April 2015 at 23:40, Pankaj Dubey wrote:
> fixes obvious typo in of_coresight.c
> %s/non-configuable/non-configurable
>
> Signed-off-by: Pankaj Dubey
> ---
> drivers/hwtracing/coresight/of_coresight.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/hwtracin
On 28 April 2015 at 02:30, Ivan T. Ivanov wrote:
>
> On Mon, 2015-04-27 at 09:48 -0600, Mathieu Poirier wrote:
>> On 24 April 2015 at 09:41, Ivan T. Ivanov wrote:
>> > On Wed, 2015-04-22 at 16:40 -0600, Mathieu Poirier wrote:
>> >
>>
On 29 April 2015 at 06:19, Ivan T. Ivanov wrote:
> From: Pratik Patel
Thanks for crediting the original author.
>
> This driver manages Qualcomm CoreSight Replicator device, which
> resides on the AMBA bus. Replicator has been made programmable to
> allow software to turn of the replicator bran
On 29 April 2015 at 06:20, Ivan T. Ivanov wrote:
> Add initial set of CoreSight components found on Qualcomm's 8x16 chipset.
>
> Signed-off-by: Ivan T. Ivanov
> ---
> arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi | 244
>
> 1 file changed, 244 insertions(+)
> create
Please find in this patchset a driver implementation that conforms
to the coresight framework and provide support for the Embedded
Trace Macrocell version 4.
Regards,
Mathieu
---
Changes for v2:
- Rebased on v4.1-rc1.
- Fixed mask in the amba_id cells.
- Fixed double pm_runtime_put() in error pa
/testing/sysfs-bus-coresight-devices-etm4x
index 0f579eb24631..9caf70382088 100644
--- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
+++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
@@ -87,3 +87,36 @@ KernelVersion: 4.01
Contact: Mathieu Poirier
From: Pratik Patel
Adding sysfs entries related to the counter functionality, more specifically
to set, control and reload the counters.
Signed-off-by: Pratik Patel
Signed-off-by: Mathieu Poirier
---
.../ABI/testing/sysfs-bus-coresight-devices-etm4x | 26
drivers/hwtracing/coresight
-off-by: Mathieu Poirier
---
.../ABI/testing/sysfs-bus-coresight-devices-etm4x | 61 +++
drivers/hwtracing/coresight/coresight-etm4x.c | 117 +
2 files changed, 178 insertions(+)
diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
b
From: Pratik Patel
Adding sysfs entries to access and configure specifics about the
context ID comparator functions.
Signed-off-by: Pratik Patel
Signed-off-by: Mathieu Poirier
---
.../ABI/testing/sysfs-bus-coresight-devices-etm4x | 19 +++
drivers/hwtracing/coresight/coresight-etm4x.c
From: Pratik Patel
Adding sysfs entries to access and configure specifics about the
virtual machine ID comparator functions.
Signed-off-by: Pratik Patel
Signed-off-by: Mathieu Poirier
---
.../ABI/testing/sysfs-bus-coresight-devices-etm4x | 20 +++
drivers/hwtracing/coresight/coresight
From: Pratik Patel
Adding sysfs entries to control the selection of the resources the
trace unit will use as triggers to perform a trace run.
Signed-off-by: Pratik Patel
Signed-off-by: Mathieu Poirier
---
.../ABI/testing/sysfs-bus-coresight-devices-etm4x | 12
drivers/hwtracing
From: Pratik Patel
Adding sysfs entries to access the sequencers related registers,
more specifically the sequencer state, the sequencer state
transition and the sequencer reset control registers.
Signed-off-by: Pratik Patel
Signed-off-by: Mathieu Poirier
---
.../ABI/testing/sysfs-bus
From: Pratik Patel
Adding sysfs entries to configure:
. global timestamp.
. how often trace synchronisation occur.
. the threashold value for cycle counting.
. branch and broadcasting regions.
Signed-off-by: Pratik Patel
Signed-off-by: Mathieu Poirier
---
.../ABI/testing/sysfs-bus-coresight
.
Signed-off-by: Pratik Patel
Signed-off-by: Mathieu Poirier
---
.../ABI/testing/sysfs-bus-coresight-devices-etm4x | 25 ++
drivers/hwtracing/coresight/coresight-etm4x.c | 423 +
2 files changed, 448 insertions(+)
diff --git a/Documentation/ABI/testing/sysfs-bus
From: Pratik Patel
Adding sysfs entries to control the ViewInst register's event
selector along with secure and non-secure exception level
instruction tracing.
Signed-off-by: Pratik Patel
Signed-off-by: Mathieu Poirier
---
.../ABI/testing/sysfs-bus-coresight-devices-etm4x
From: Pratik Patel
This driver manages the CoreSight ETMv4 (Embedded Trace Macrocell) IP block
to support HW assisted tracing on ARMv7 and ARMv8 architectures.
Signed-off-by: Pratik Patel
Signed-off-by: Kaixu Xia
Signed-off-by: Mathieu Poirier
---
.../ABI/testing/sysfs-bus-coresight-devices
On 30 April 2015 at 03:24, Ivan T. Ivanov wrote:
>
> On Wed, 2015-04-29 at 10:49 -0600, Mathieu Poirier wrote:
>> On 29 April 2015 at 06:20, Ivan T. Ivanov iva...@linaro.org> wrote:
>
>
>> > +
>> > + funnel@821000 {
>> > + com
On 30 April 2015 at 01:21, Ivan T. Ivanov wrote:
>
> On Wed, 2015-04-29 at 10:28 -0600, Mathieu Poirier wrote:
>> On 29 April 2015 at 06:19, Ivan T. Ivanov iva...@linaro.org> wrote:
>
>
>
>> > - "arm,coresight-etm4x", "arm,pr
@windriver.com
> [2]
> https://lkml.kernel.org/r/1431287385-1526-1-git-send-email-paul.gortma...@windriver.com
>
> Cc: Pratik Patel
> Cc: Kaixu Xia
> Cc: Mathieu Poirier
> Cc: Greg Kroah-Hartman
> Signed-off-by: Paul Gortmaker
> ---
>
> [Note: Commit 2e1cdfe184
kernel.org/r/1433276168-21550-1-git-send-email-paul.gortma...@windriver.com
> [2]
> https://lkml.kernel.org/r/1431287385-1526-1-git-send-email-paul.gortma...@windriver.com
>
> Cc: Pratik Patel
> Cc: Ivan T. Ivanov
> Cc: Mathieu Poirier
> Cc: Greg Kroah-Hartman
> Signed
for
CORESIGHT_LINKS_AND_SINKS. Once we've dealt with this topic we can refactor the
replicator driver.
Thanks,
Mathieu
>
> Suggested-by: Mathieu Poirier
> Cc: Alexander Shishkin
> Signed-off-by: Kim Phillips
> ---
> drivers/hwtracing/coresight/Kconfig | 7 ---
ight-etb10.c
> @@ -758,3 +758,8 @@ static struct amba_driver etb_driver = {
> .id_table = etb_ids,
> };
> builtin_amba_driver(etb_driver);
> +
> +MODULE_AUTHOR("Pratik Patel ");
> +MODULE_AUTHOR("Mathieu Poirier ");
> +MODULE_DESCRIPTION("Arm CoreSight
that unregisters the coresight bus, add
> remove fns for most others.
>
> - fix up modules with ID tables for autoloading on boot
>
> Cc: Mathieu Poirier
> Cc: Alexander Shishkin
> Cc: Randy Dunlap
> Signed-off-by: Kim Phillips
> ---
> drivers/hwtracing/core
On 18 May 2018 at 10:39, Suzuki K Poulose wrote:
> Advertise that the scatter-gather is properly integrated on
> all revisions of Juno board.
>
> Cc: Mathieu Poirier
> Cc: Sudeep Holla
> Cc: Liviu Dudau
> Cc: Lorenzo Pieralisi
> Signed-off-by: Suzuki K Poulose
Revi
by the drivers. The framework also provides helpers to
> sync the data written to the pages with appropriate directions.
>
> This will be later used by the TMC ETR SG unit and CATU.
>
> Cc: Mathieu Poirier
> Signed-off-by: Suzuki K Poulose
> ---
> Changes since v1:
>
On 26 March 2018 at 20:30, arvindY wrote:
>
>
> On Tuesday 27 March 2018 03:16 AM, Mathieu Poirier wrote:
>>
>> drivers/hwtracing/coresight/coresight.c
>> On 18 March 2018 at 01:38, Arvind Yadav wrote:
>>>
>>> Never directly free @dev after calling
On 27 March 2018 at 10:28, arvindY wrote:
>
>
> On Tuesday 27 March 2018 09:37 PM, Mathieu Poirier wrote:
>>
>> On 26 March 2018 at 20:30, arvindY wrote:
>>>
>>>
>>> On Tuesday 27 March 2018 03:16 AM, Mathieu Poirier wrote:
>>>>
>&g
On 18 March 2018 at 01:38, Arvind Yadav wrote:
> Never directly free @dev after calling device_register(), even
> if it returned an error. Always use put_device() to give up the
> reference initialized.
>
> Signed-off-by: Arvind Yadav
> ---
> drivers/hwtracing/coresight/coresight.c | 8
mal value.
>
> So this commit removes useless %px and update section "Output format"
> in the document for alignment between the code and document.
>
> Suggested-by: Kees Cook
> Cc: Mathieu Poirier
> Signed-off-by: Leo Yan
Applied - thanks,
Mathieu
> ---
&
On 27 May 2018 at 21:13, Leo Yan wrote:
> On Fri, May 25, 2018 at 05:10:54PM -0600, Mathieu Poirier wrote:
>> The tail of a queue is supposed to be pointing to the next available slot
>> in a queue. In this implementation the tail is incremented before it is
>> used and
Leo and/or Robert,
On Mon, May 28, 2018 at 04:45:00PM +0800, Leo Yan wrote:
> Commit e573e978fb12 ("perf cs-etm: Inject capabilitity for CoreSight
> traces") reworks the samples generation flow from CoreSight trace to
> match the correct format so Perf report tool can display the samples
> properl
On 28 May 2018 at 14:03, Arnaldo Carvalho de Melo wrote:
> Em Mon, May 28, 2018 at 04:44:59PM +0800, Leo Yan escreveu:
>> This patch series is to support for using 'perf script' for CoreSight
>> trace disassembler, for this purpose this patch series adds a new
>> python script to parse CoreSight t
On 5 June 2018 at 05:48, Arnd Bergmann wrote:
> The newly introduced code fails to build in some configurations
> unless we include the right headers:
>
> drivers/hwtracing/coresight/coresight-tmc-etr.c: In function
> 'tmc_free_table_pages':
> drivers/hwtracing/coresight/coresight-tmc-etr.c:206:3
On 1 June 2018 at 05:08, Suzuki K Poulose wrote:
> We request for "CORESIGHT_BARRIER_PKT_SIZE" length and we should
> be happy when we get that size.
>
> Cc: Mathieu Poirier
> Signed-off-by: Suzuki K Poulose
> ---
>
> Mathieu,
>
> Please could you p
On 15 May 2018 at 08:37, Kim Phillips wrote:
> On Tue, 15 May 2018 14:48:31 +0100
> Russell King - ARM Linux wrote:
>
>> On Tue, May 15, 2018 at 08:15:19AM -0500, Kim Phillips wrote:
>> > On Tue, 15 May 2018 08:59:02 +0200
>> > Ulf Hansson wrote:
>> >
>> > > On 8 May 2018 at 21:06, Kim Phillips
got changed in commit 7d83d17795ef ("coresight: tmc: adding sysFS
> management entries").
>
> Cc: Mathieu Poirier
> Cc: Randy Dunlap
> Cc: Jonathan Corbet
> Signed-off-by: Kim Phillips
I'm good with this version - Jonathan, should I take this through my
tree of yo
Hi Leo,
On Fri, 12 Apr 2019 at 04:28, Leo Yan wrote:
>
> CoreSight uses below bindings for replicator:
>
> Dynamic replicator, aka. configurable replicator:
> "arm,coresight-dynamic-replicator", "arm,primecell";
>
> Static replicator, aka. non-configurable replicator:
> "arm,coresight
gt; Dynamic funnel:
> "arm,coresight-dynamic-funnel", "arm,primecell";
> "arm,coresight-funnel", "arm,primecell"; (obsolete)
>
> At the end of this patch, it gives an example for static funnel DT
> binding, and updates the dynamic funn
On Tue, 16 Apr 2019 at 18:10, Leo Yan wrote:
>
> On Tue, Apr 16, 2019 at 02:18:40PM -0600, Mathieu Poirier wrote:
> > Hi Leo,
> >
> > On Fri, 12 Apr 2019 at 04:28, Leo Yan wrote:
> > >
> > > CoreSight uses below bindings for replicator:
> >
On Mon, 15 Apr 2019 at 10:05, Suzuki K Poulose wrote:
>
> Drop the power only if we were successful in probing the device.
>
> Cc: Mathieu Poirier
> Signed-off-by: Suzuki K Poulose
> ---
> drivers/hwtracing/coresight/coresight-tmc.c | 4 ++--
> 1 file changed, 2 in
urposes. All other requests (e.g, power management,
> DMA operations) must use the "real" device which is the parent device.
>
> Cc: Mathieu Poirier
> Signed-off-by: Suzuki K Poulose
> ---
> drivers/hwtracing/coresight/coresight-funnel.c | 10 --
> 1 file cha
nal purposes. All other requests (e.g, power management,
> DMA operations) must use the "real" device which is the parent device.
>
> Cc: Mathieu Poirier
> Signed-off-by: Suzuki K Poulose
> ---
> drivers/hwtracing/coresight/coresight-replicator.c | 7 ++-
> 1
nal purposes. All other requests (e.g, power management,
> DMA operations) must use the "real" device which is the parent device.
>
> Since the CATU driver also uses the TMC-SG infrastructure, update
> the callers to ensure they pass the appropriate device argument
> for the
On Mon, Apr 15, 2019 at 05:03:52PM +0100, Suzuki K Poulose wrote:
> Switch to using the CoreSight device instead of the real
> amba device.
>
> Cc: Mathieu Poirier
> Signed-off-by: Suzuki K Poulose
> ---
> drivers/hwtracing/coresight/coresight-catu.c | 13 +++--
On Mon, Apr 15, 2019 at 05:03:53PM +0100, Suzuki K Poulose wrote:
> Switch to using the coresight device instead of the parent
> amba device.
>
> Cc: Mathieu Poirier
> Signed-off-by: Suzuki K Poulose
> ---
> drivers/hwtracing/coresight/coresight-tpiu.c | 6 ++
On Mon, Apr 15, 2019 at 05:03:54PM +0100, Suzuki K Poulose wrote:
> Keep track of the STM coresight device which is a child device
> of the AMBA device. Since we can get to the coresight_device
> from the "device" instance, remove the explicit field.
>
> Cc: Mathieu
h this very short changelog, it would
certainly be cryptic.
Please enhance the description so that someone without background can have a
better understanding of what is going on.
With that:
Reviewed-by: Mathieu Poirier
>
> Cc: Mathieu Poirier
> Signed-off-by: Suzuki K Poulose
> -
n device of the respective
> CPU.
>
> Cc: "Rafael J. Wysocki"
> Cc: Mathieu Poirier
> Signed-off-by: Suzuki K Poulose
> ---
> drivers/hwtracing/coresight/coresight-platform.c | 409
> +++
> 1 file changed, 409 insertions(+)
>
On Mon, Apr 15, 2019 at 05:04:16PM +0100, Suzuki K Poulose wrote:
> All AMBA devices are handled via ACPI AMBA scan notifier
> infrastructure. The platform devices get the ACPI id
> added to their driver.
>
> Cc: "Rafael J. Wysocki"
> Cc: Mathieu Poirier
>
modify the HW is overlooked for as long as more than one source is using
a sink.
Signed-off-by: Mathieu Poirier
Tested-by: Leo Yan
Tested-by: Robert Walker
---
.../hwtracing/coresight/coresight-tmc-etf.c | 40 ---
1 file changed, 35 insertions(+), 5 deletions(-)
diff --git a
In preparation to handle device reference counting inside of the sink
drivers, add a return code to the sink::disable() operation so that
proper action can be taken if a sink has not been disabled.
Signed-off-by: Mathieu Poirier
Reviewed-by: Suzuki K Poulose
Tested-by: Leo Yan
Tested-by
In preparation to support CPU-wide trace scenarios, introduce the notion
of process ID to ETR devices. That way events monitoring the same process
can use the same etr_buf, allowing multiple CPUs to use the same sink.
Signed-off-by: Mathieu Poirier
Tested-by: Leo Yan
Tested-by: Robert Walker
Resource selector pair 0 is always implemented and reserved. As such
it should not be explicitly programmed.
Signed-off-by: Mathieu Poirier
Reviewed-by: Suzuki K Poulose
Tested-by: Leo Yan
Tested-by: Robert Walker
---
drivers/hwtracing/coresight/coresight-etm4x.c | 7 +--
1 file changed
When operating in CPU-wide trace scenarios and working with an N:1
source/sink HW topology, update() functions need to be made atomic
in order to avoid racing with start and stop operations.
Signed-off-by: Mathieu Poirier
Reviewed-by: Suzuki K Poulose
Tested-by: Leo Yan
Tested-by: Robert
This patch uses the PID of the process being traced to allocate and free
ETR memory buffers for CPU-wide scenarios. The implementation is tailored
to handle both N:1 and 1:1 source/sink HW topologies.
Signed-off-by: Mathieu Poirier
Tested-by: Leo Yan
Tested-by: Robert Walker
Make struct perf_event available to sink buffer allocation functions in
order to use the pid they carry to allocate and free buffer memory along
with regimenting access to what source a sink can collect data for.
Signed-off-by: Mathieu Poirier
Tested-by: Leo Yan
Tested-by: Robert Walker
Buffer allocation is different when dealing with per-thread and
CPU-wide sessions. In preparation to support CPU-wide trace scenarios
simplify things by keeping allocation functions for both type separate.
Signed-off-by: Mathieu Poirier
Tested-by: Leo Yan
Tested-by: Robert Walker
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