[PATCH 1/5] MIPS: Introduce irq_stack

Allocate a per-cpu irq stack for use within interrupt handlers. Also add a utility function on_irq_stack to determine if a given stack pointer is within the irq stack for that cpu. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- arch/mips/include/asm/irq.h

[PATCH 0/5] MIPS: Add per-cpu IRQ stack

than attempting to switch with do_softirq_own_stack(). This series has been tested on MIPS Boston, Malta and SEAD3 platforms, Pistachio on the Creator Ci40 board and Cavium Octeon III. Matt Redfearn (5): MIPS: Introduce irq_stack MIPS: Stack unwinding while on IRQ stack MIPS: Only change

[PATCH 3/5] MIPS: Only change $28 to thread_info if coming from user mode

, register $28 is only switched to it's kernel conventional usage of the currrent thread info pointer at the point at which execution enters kernel space. Doing it on every exception was redundant, but OK without an IRQ stack, but will be erroneous once that is introduced. Signed-off-by: Matt Redfearn

Re: [PATCH 3/5] MIPS: Only change $28 to thread_info if coming from user mode

Hi Maciej, On 05/12/16 16:20, Maciej W. Rozycki wrote: On Fri, 2 Dec 2016, Matt Redfearn wrote: diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h index eebf39549606..5782fa3d63be 100644 --- a/arch/mips/include/asm/stackframe.h +++ b/arch/mips/include/asm

Re: [PATCH 19/21] MIPS memblock: Add print out method of kernel virtual memory layout

Hi Serge, On 19/12/16 02:07, Serge Semin wrote: It's useful to have some printed map of the kernel virtual memory, at least for debugging purpose. Signed-off-by: Serge Semin --- arch/mips/mm/init.c | 47 +++ 1 file changed, 47

[PATCH v3 0/5] MIPS: Add per-cpu IRQ stack

now that the code is .set reorder. Changes in v2: Drop .set reorder/noreorder when updating $28 Matt Redfearn (5): MIPS: Introduce irq_stack MIPS: Stack unwinding while on IRQ stack MIPS: Only change $28 to thread_info if coming from user mode MIPS: Switch to the irq_stack in interrupts

[PATCH v3 1/5] MIPS: Introduce irq_stack

Allocate a per-cpu irq stack for use within interrupt handlers. Also add a utility function on_irq_stack to determine if a given stack pointer is within the irq stack for that cpu. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- Changes in v3: None Changes in v2: None arc

[PATCH v3 4/5] MIPS: Switch to the irq_stack in interrupts

here. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- Changes in v3: None Changes in v2: None arch/mips/kernel/genex.S | 81 +--- 1 file changed, 76 insertions(+), 5 deletions(-) diff --git a/arch/mips/kernel/genex.S b/arch/mips/

[PATCH v3 2/5] MIPS: Stack unwinding while on IRQ stack

Within unwind stack, check if the stack pointer being unwound is within the CPU's irq_stack and if so use that page rather than the task's stack page. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- Changes in v3: None Changes in v2: None arch/mips/kernel/process.

[PATCH v3 3/5] MIPS: Only change $28 to thread_info if coming from user mode

, register $28 is only switched to it's kernel conventional usage of the currrent thread info pointer at the point at which execution enters kernel space. Doing it on every exception was redundant, but OK without an IRQ stack, but will be erroneous once that is introduced. Signed-off-by: Matt Redfearn

[PATCH v3 5/5] MIPS: Select HAVE_IRQ_EXIT_ON_IRQ_STACK

Since do_IRQ is now invoked on a separate IRQ stack, we select HAVE_IRQ_EXIT_ON_IRQ_STACK so that softirq's may be invoked directly from irq_exit(), rather than requiring do_softirq_own_stack. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- Changes in v3: None Changes in v2

[PATCH v6 0/4] MIPS: Remote processor driver

att (1): MIPS: CPS: Add VP(E) stealing Matt Redfearn (3): irqchip: mips-gic: Add context saving for MIPS_REMOTEPROC remoteproc/MIPS: Add a remoteproc driver for MIPS MIPS: Deprecate VPE Loader Documentation/ABI/testing/sysfs-devices-mips-rproc | 13 + arch/mips/Kcon

[PATCH v6 3/4] remoteproc/MIPS: Add a remoteproc driver for MIPS

boot protocol in the startup code. Example firmware and host executables to test them are located at [1]. [1] https://github.com/MIPS/mips-rproc-example Signed-off-by: Lisa Parratt <lisa.parr...@imgtec.com> Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- Changes i

[PATCH v6 2/4] MIPS: CPS: Add VP(E) stealing

lisa.parr...@imgtec.com> Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None arch/mips/Kconfig | 7 ++ arch/mips/include/asm/smp-cps.h | 8 ++ arch/mips/kernel/sm

[PATCH v6 4/4] MIPS: Deprecate VPE Loader

The MIPS remote processor driver (CONFIG_MIPS_REMOTEPROC) provides a more standard mechanism for using one or more VPs as coprocessors running separate firmware. Here we deprecate this mechanism before it is removed. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- Changes

[PATCH v6 1/4] irqchip: mips-gic: Add context saving for MIPS_REMOTEPROC

is restored. These functions will also be useful for restoring GIC context after a suspend to RAM. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- Changes in v6: Rebase on Linux 4.11-rc3 Changes in v5: None Changes in v4: Fix inconsistency of Linux CPU number and VP ID Changes

[PATCH 0/2] Fix v4.11 malta_defconfig regressions

do_IRQ+0x18/0x24 [<803b83fc>] plat_irq_dispatch+0x54/0xa8 handlers: Disabling IRQ #23 This regression is fixed by Paul Burtons series "MIPS/irqchip: Use IPI IRQ domains for CPU interrupt controller IPIs", but it is a large change for this stage in the cycle so I don't know how bes

[PATCH 2/2] irqchip/mips-gic: Fix Local compare interrupt

rq numbers with the correct hw interrupts. Fixes: 4cfffcfa5106 ("irqchip/mips-gic: Fix local interrupts") Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- drivers/irqchip/irq-mips-gic.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/ir

[PATCH 1/2] MIPS: Malta: Fix i8259 irqchip setup

nit+0x19c/0x310 [<80752dd8>] arch_init_irq+0x28/0x19c [<80750a08>] start_kernel+0x2a8/0x434 Fix this by reserving the required i8259 virqs in malta platform code before probing any irq chips. Fixes: 4cfffcfa5106 ("irqchip/mips-gic: Fix local interrupts") Signed-off-by: Matt Redfearn <ma

[PATCH] MIPS: smp-cps: Fix potentially uninitialised value of core

this by always initialising the variable. Fixes: 0d2808f338c7 ("MIPS: smp-cps: Add support for CPU hotplug of MIPSr6 processors") Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- arch/mips/kernel/smp-cps.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) d

[PATCH] MIPS: KASLR: Add missing header files

After the split of linux/sched.h, KASLR stopped building. Fix this by including the correct header file for init_thread_union Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- arch/mips/kernel/relocate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arc

Re: [PATCH 0/2] Fix v4.11 malta_defconfig regressions

Hi Marc, On 31/03/17 13:04, Marc Zyngier wrote: Hi Matt, On 31/03/17 12:05, Matt Redfearn wrote: Since v4.11-rc1, 3 regressions have been observed on the Malta platform, using malta_defconfig. which prevent it booting. These patches fix 2 of them. The third one is that malta_defconfig, which

Re: [PATCH 1/2] MIPS: Malta: Fix i8259 irqchip setup

Hi Ralf, On 31/03/17 13:49, Ralf Baechle wrote: On Fri, Mar 31, 2017 at 12:05:31PM +0100, Matt Redfearn wrote: diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c index cb675ec6f283..474b372e0dd9 100644 --- a/arch/mips/mti-malta/malta-int.c +++ b/arch/mips/mti

Re: [PATCH v6 3/4] remoteproc/MIPS: Add a remoteproc driver for MIPS

Hi Bjorn, Please could you provide any comments / review on this driver? Thanks, Matt On 23/03/17 16:37, Matt Redfearn wrote: This driver allows a MIPS processor offlined from Linux to be used as a remote processor. The processor can then handle real-time tasks or perform coprocessing while

Re: [PATCH] MIPS: IRQ Stack: Unwind IRQ stack onto task stack

Hi Jason, On 04/04/17 12:58, Jason A. Donenfeld wrote: This indeed is useful. Out of curiosity, are other archs using a similar technique? In anycase, Acked-by: Jason A. Donenfeld Yes, at least x86 and ARM64 do the same thing (probably more) x86 saves the previous stack

[PATCH v2] MIPS: Malta: Fix i8259 irqchip setup

nit+0x19c/0x310 [<80752dd8>] arch_init_irq+0x28/0x19c [<80750a08>] start_kernel+0x2a8/0x434 Fix this by reserving the required i8259 virqs in malta platform code before probing any irq chips. Fixes: 4cfffcfa5106 ("irqchip/mips-gic: Fix local interrupts") Signed-off-by: Matt Redfearn <m

[PATCH] MIPS: Remove dead define of ST_OFF

Commit 1a3d59579b9f ("MIPS: Tidy up FPU context switching") removed the last usage of the macro ST_OFF. Remove the dead code. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> Cc: triv...@kernel.org --- arch/mips/kernel/r4k_switch.S | 6 -- 1 file changed, 6 deletion

Re: [PATCH 2/2] irqchip/mips-gic: Fix Local compare interrupt

Hi Paul, On 10/04/17 23:06, Paul Burton wrote: Hi Matt, On Friday, 31 March 2017 04:05:32 PDT Matt Redfearn wrote: Commit 4cfffcfa5106 ("irqchip/mips-gic: Fix local interrupts") added mapping of several local interrupts during initialisation of the gic driver. This associates vi

[PATCH 2/3] irqchip: mips-gic: Remove device IRQ domain

ng than the previous approach where the 2 child domains had to call up to their parent, which had to handle both types of interrupt & had all sorts of weird & wonderful duplication or outright clobbering of setup performed by multiple domains. Signed-off-by: Paul Burton <paul.bur...@imgtec.co

[PATCH 1/3] irqchip: mips-gic: Separate IPI reservation & usage tracking

962070 ("irqchip/mips-gic: Add a IPI hierarchy domain") Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- drivers/irqchip/irq-mips-gic.c | 12 +++- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/i

[PATCH 3/3] irqchip: mips-gic: Replace static map with dynamic

lta platform without breaking the perf interrupt fixed by commit e875bd66dfb ("irqchip/mips-gic: Fix local interrupts"). Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- drivers/irqchip/irq-mips-gic.c | 60 +- 1 file changed, 18

[PATCH 0/3] irqchip: mips-gic: Remove dev domain & fixes

. The third fixes an issue seen in v4.11 which broke the Malta platforms legacy IRQ controller. These patches have been tested on multiple MIPS platforms including Malta, Boston, Ci40 and SEAD3. Matt Redfearn (1): irqchip: mips-gic: Replace static map with dynamic Paul Burton (2): irqchip

[PATCH 1/2] MIPS: Malta: Probe gic-timer via devicetree

devicetree method. Before the driver is probed, set the "clock-frequency" property of the devicetree node to the value detected by Malta platform code. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- arch/mips/mti-malta/malta-time.c | 31 ++- 1

[PATCH 2/2] Clocksource: mips-gic: Remove redundant non devicetree init

Malta was the only platform probing this driver from platform code without using device tree. With that code removed, gic_clocksource_init is redundant so remove it. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- drivers/clocksource/mips-gic-timer.c | 13 - i

[PATCH v2 5/5] MIPS: microMIPS: Fix decoding of swsp16 instruction

nding the stack") Suggested-by: Paul Burton <paul.bur...@imgtec.com> Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- Changes in v2: None arch/mips/include/uapi/asm/inst.h | 2 +- arch/mips/kernel/process.c| 2 +- 2 files changed, 2 insertions(+), 2 deletions

[PATCH] MIPS: generic: Enable Root FS on NFS in generic_defconfig

ails to mount. There is little harm in having this feature enabled by default, so enable it in the defconfig. Kernel autoconfiguration & DHCP must also be selected to allow RFS on NFS. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- arch/mips/configs/generic_defconfig |

[PATCH] MIPS: smp-cps: Fix retrieval of VPE mask on big endian CPUs

failing to start in 64bit big endian systems. Change the load to a 32bit load word instruction to fix the bug. Fixes: f12401d7219f ("MIPS: smp-cps: Pull boot config retrieval out of mips_cps_boot_vpes") Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- arch/mips/kern

[PATCH] MIPS: IRQ Stack: Unwind IRQ stack onto task stack

to stop unwinding the stack 32 bytes from the top of a stack must be modified to allow unwinding to continue up to the location of the saved task stack pointer when on the IRQ stack. The low / high marks of the stack are set depending on whether the sp is on an irq stack or not. Signed-off-by: Matt

Re: [PATCH] MIPS: usercopy: Implement stack frame object validation

Hi Kees, On 08/08/17 20:11, Kees Cook wrote: On Tue, Aug 8, 2017 at 5:23 AM, Matt Redfearn <matt.redfe...@imgtec.com> wrote: This implements arch_within_stack_frames() for MIPS that validates if an object is wholly contained by a kernel stack frame. With CONFIG_HARDENED_USERCOPY e

Re: [PATCH 1/2] printk: Unconditionally unregister boot consoles if in init section

On 14/07/17 13:40, Petr Mladek wrote: On Wed 2017-07-12 13:11:17, Petr Mladek wrote: On Tue 2017-07-11 15:41:50, Matt Redfearn wrote: On 11/07/17 13:43, Petr Mladek wrote: IMHO, the reasonable solution is to move early console code and data out of the init sections. We should do

Re: [PATCH 1/2] printk: Unconditionally unregister boot consoles if in init section

Hi Petr, On 11/07/17 13:43, Petr Mladek wrote: Hi all, let's first make sure that we understand the code the same way. On Fri 2017-07-07 08:58:01, Matt Redfearn wrote: On 07/07/17 05:45, Sergey Senozhatsky wrote: On (07/06/17 11:38), Matt Redfearn wrote: Commit 4c30c6f566c0 ("k

[PATCH] MIPS: pistachio: Enable Root FS on NFS in defconfig

When the upstream kernel pistachio_defconfig is built & tested on the ci40 platform the current lack of these options leads to essentially false failures when the RFS fails to mount. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- arch/mips/configs/pistachio_defconfig |

[PATCH v2] MIPS: Fix minimum alignment requirement of IRQ stack

as <das...@yahoo.com> Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- Changes in v2: Don't include asm/asm.h since the definitions in it lead to breakage when it pollutes the C namespace (thanks kbuild test robot!) arch/mips/include/asm/irq.h | 2 +- 1 file changed, 1 i

[PATCH] MIPS: Fix minimum alignment requirement of IRQ stack

te minimum alignment. Use the ALMASK stack pointer mask to align the stack as appropriate for the kernel build. Fixes: db8466c581cc ("MIPS: IRQ Stack: Unwind IRQ stack onto task stack") Reported-by: Darius Ivanauskas <das...@yahoo.com> Suggested-by: James Hogan <james.ho...@imgtec.com&

[PATCH] irqchip/mips-gic: Remove population of irq domain names

ow that they are set by the irqdomain core. This effectively reverts commit 21c57fd13589 ("irqchip/mips-gic: Populate irq_domain names"). Fixes: d59f6617eef0f ("genirq: Allow fwnode to carry name information only") Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- drivers

[PATCH v2] MIPS: SMP: Constify smp ops

9430087 8fe447 vmlinux Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- Changes in v2: Constify plat_smp_ops structs in providers missed by v1. All upstream defconfigs now build. arch/mips/cavium-octeon/smp.c| 6 +++--- arch/mips/fw/arc/

[PATCH] MIPS: PCI: Fix smp_processor_id() in preemptible

0x14/0x118 [] ret_from_kernel_thread+0x14/0x1c Fix this by using raw_current_cpu_data instead. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- In heteregenerous systems the more correct fix for this would be to iterate over CPUs checking each ones cache hierarchy. However, as no such systems

[RFC PATCH] exec: Avoid recursive modprobe for binary format handlers

exists but couldn't execute it (error -8) Fixes: 6d7964a722af ("kmod: throttle kmod thread limit") Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- What we really need to detect is that exec'ing modprobe failed, but currently it does not get as far as an actual error

[PATCH v2] MIPS: PCI: Fix smp_processor_id() in preemptible

cessor_id() checks early") Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> Suggested-by: James Hogan <james.ho...@imgtec.com> Reviewed-by: James Hogan <james.ho...@imgtec.com> --- Changes in v2: Switch to using cpu_*cache_line_size() macros In heteregenerous systems the mo

[PATCH v3 2/2] MIPS: PCI: Fix smp_processor_id() in preemptible

checks early") Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> Suggested-by: James Hogan <james.ho...@imgtec.com> Reviewed-by: James Hogan <james.ho...@imgtec.com> --- Changes in v3: Split into 2 patches Changes in v2: Switch to using cpu_*cache_line_size() macros

[PATCH v3 1/2] MIPS: Introduce cpu_tcache_line_size

There exist macros to return the cache line size of the L1 dcache and L2 scache but there is currently no macro for the L3 tcache. Add this macro which will be used by the following patch "MIPS: PCI: Fix smp_processor_id() in preemptible" Signed-off-by: Matt Redfearn <matt.redfe.

[PATCH 1/2] printk: Unconditionally unregister boot consoles if in init section

init section. Fixes 81cc26f2bd11 ("printk: only unregister boot consoles when necessary"). Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- kernel/printk/printk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/printk/printk.c b/kernel/printk/print

[PATCH 2/2] serial: earlycon: Make early_con as __initdata

in commit d2fd6810a823 ("tty/serial: convert 8250 to generic earlycon") appears to have broken unregistraton of the boot console when its code and data are in __init. Fixes: d2fd6810a823 ("tty/serial: convert 8250 to generic earlycon") Signed-off-by: Matt Redfearn <m

Re: [PATCH 1/2] printk: Unconditionally unregister boot consoles if in init section

On 07/07/17 05:45, Sergey Senozhatsky wrote: On (07/06/17 11:38), Matt Redfearn wrote: Commit 4c30c6f566c0 ("kernel/printk: do not turn off bootconsole in printk_late_init() if keep_bootcon") added a check on keep_bootcon to ensure that boot consoles were kept around until the re

[PATCH v3 5/6] MIPS: Stacktrace: Fix microMIPS stack unwinding on big endian systems

the mm16_r5_format union member to avoid the need for a 16bit shift. Fixes: 34c2f668d0f6 ("MIPS: microMIPS: Add unaligned access support.") Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> Reviewed-by: James Hogan <james.ho...@imgtec.com> --- Changes in v3: New p

[PATCH v3 3/6] MIPS: microMIPS: Fix decoding of addiusp instruction

0x1fe 510 -> (0xfefe -258) 0x408 1032 0x1ff 511 -> (0xfeff -257) 0x404 1028 Thanks to James Hogan for the test code & verifying the logic. Fixes: 34c2f668d0f6 ("MIPS: microMIPS: Add unaligned access support.") Suggested-by: James

[PATCH v3 2/6] MIPS: microMIPS: Fix detection of addiusp instruction

the logical and with a bitwise and. Fixes: 34c2f668d0f6 ("MIPS: microMIPS: Add unaligned access support.") Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- Changes in v3: - New patch to fix detection of addiusp instruction Changes in v2: None arch/mips/kernel/process.c | 2 +-

[PATCH v3 6/6] MIPS: Refactor handling of stack pointer in get_frame_info

is reduces the amount of indentation required in get_frame_info, and more closely matches the operation of is_ra_save_ins. Suggested-by: Maciej W. Rozycki <ma...@imgtec.com> Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- Changes in v3: None Changes in v2: - Refactor is_sp

[PATCH] MIPS: usercopy: Implement stack frame object validation

, and for correct operation on microMIPS depends on my series "MIPS: Further microMIPS stack unwinding fixes" Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> Reviewed-by: James Hogan <james.ho...@imgtec.com> --- arch/mips/Kconfig | 1 + arch/mips/include/

[PATCH v3 1/6] MIPS: Handle non word sized instructions when examining frame

uction, but not any other). Fixes: 34c2f668d0f6b ("MIPS: microMIPS: Add unaligned access support.") Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- Changes in v3: - Remove hack which attempted to cope with 16bit instructions Changes in v2: - Keep locals in reverse chr

[PATCH v3 4/6] MIPS: microMIPS: Fix decoding of swsp16 instruction

nding the stack") Suggested-by: Paul Burton <paul.bur...@imgtec.com> Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> Reviewed-by: James Hogan <james.ho...@imgtec.com> --- Changes in v3: None Changes in v2: None arch/mips/include/uapi/asm/inst.h | 2 +- arch/mips/kerne

[PATCH v3 0/6] MIPS: Further microMIPS stack unwinding fixes

ndian systems Changes in v2: - Keep locals in reverse christmas tree order - Replace conditional with xor and subtract - Refactor is_sp_move_ins to interpret immediate inline. Matt Redfearn (6): MIPS: Handle non word sized instructions when examining frame MIPS: microMIPS: Fix detection o

Re: [RFC PATCH] exec: Avoid recursive modprobe for binary format handlers

Hi Luis, On 03/08/17 00:23, Luis R. Rodriguez wrote: On Tue, Aug 01, 2017 at 07:28:20PM -0700, Kees Cook wrote: On Tue, Aug 1, 2017 at 5:12 PM, Luis R. Rodriguez <mcg...@kernel.org> wrote: On Fri, Jul 21, 2017 at 03:05:20PM +0100, Matt Redfearn wrote: Commit 6d7964a722af ("kmo

[PATCH] MIPS: Revert "MIPS: Fix race on setting and getting cpu_online_mask"

ng a heavy load test at the same time as hotplugging CPUs. See commit 8f46cca1e6c06 ("MIPS: SMP: Fix possibility of deadlock when bringing CPUs online") for details. This reverts commit 6f542ebeaee0ee552a902ce3892220fc22c7ec8e. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec

[PATCH] MIPS: Sort MIPS Kconfig Alphabetically.

Sort the entries in config MIPS alphabetically so as to make entries easier to find. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- This patch is based on 4.12-rc1. My intention would be for it to be applied during the -rc's when it is less likely to cause merge con

Re: [PATCH 1/5] MIPS: Optimize uasm insn lookup.

Hi David, On 26/05/17 01:38, David Daney wrote: Instead of doing a linear search through the insn_table for each instruction, use the opcode as direct index into the table. This will give constant time lookup performance as the number of supported opcodes increases. Make the tables const as

Re: [PATCH 1/7] lib: Add shared copies of some GCC library routines

Hi Palmer On 23/05/17 23:05, Palmer Dabbelt wrote: Many ports (m32r, microblaze, mips, parisc, score, and sparc) use functionally identical copies of various GCC library routine files, which came up as we were submitting the RISC-V port (which also uses some of these). This patch adds a new

Re: [PATCH 4/7] mips: Use lib/{ashldi3,ashrdi3,cmpdi2,lshrdi3,ucmpdi2}.c

Thanks, Matt [PATCH] MIPS: Use generic libgcc intrinsics These routines in arch/mips/lib/ are functionally identical to those recently added to lib/ so remove them and select the generic ones. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- arch/mips

[PATCH] net: stmmac: Meet alignment requirements for DMA

rx_skbuff_head, the aligned head of the buffer, and the packet data, rx_skbuff_dma. Tested on a Creator Ci40 with Pistachio SoC. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- drivers/net/ethernet/stmicro/stmmac/stmmac.h | 1 + drivers/net/ethernet/stmicro/stmmac/stmmac_main.

[PATCH] MIPS: generic: Fix compilation error from include asm/mips-cpc.h

-cps.h instead. Fixes: e83f7e02af50c ("MIPS: CPS: Have asm/mips-cps.h include CM & CPC headers") Signed-off-by: Matt Redfearn <matt.redfe...@mips.com> --- arch/mips/generic/init.c | 2 +- arch/mips/kernel/smp.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff

Re: [PATCH 4.4 36/50] MIPS: IRQ Stack: Unwind IRQ stack onto task stack

On 16/10/17 22:28, Ben Hutchings wrote: On Fri, 2017-10-06 at 10:53 +0200, Greg Kroah-Hartman wrote: 4.4-stable review patch.  If anyone has any objections, please let me know. -- From: Matt Redfearn <matt.redfe...@imgtec.com> [ Upstream

[PATCH] MIPS: Boston: Fix earlycon baud rate selection

t the baud rate settings from the bootloader. By the time the real console is probed, the clock drivers necessary to calculate the divisor are enabled and the kernel can correctly configure the baud rate. Fixes: 31cb9a8575ca ("earlycon: initialise baud field of earlycon device structure")

[PATCH] MIPS: Fix exception entry when CONFIG_EVA enabled

delay slot of the branch, outside of the CONFIG_EVA section, restoring the expected instruction ordering when CONFIG_EVA is active. Fixes: 9fef68686317b ("MIPS: Make SAVE_SOME more standard") Signed-off-by: Matt Redfearn <matt.redfe...@mips.com> Reported-by: Vladimir Kondratiev <

[PATCH] MIPS: SMP: Fix deadlock & online race

07e7f21f ("cpu/hotplug: Let upcoming cpu bring itself fully up"). To apply cleanly it requires both commit a00eeede507c10 ("MIPS: SMP: Use a completion event to signal CPU up") and commit 6f542ebeaee0 ("MIPS: Fix race on setting and getting cpu_online_mask") to be applie

Re: [PATCH] net: stmmac: Meet alignment requirements for DMA

Hi David, Thanks for your feedback. On 23/09/17 02:26, David Miller wrote: From: Matt Redfearn <matt.redfe...@imgtec.com> Date: Fri, 22 Sep 2017 12:13:53 +0100 According to Documentation/DMA-API.txt: Warnings: Memory coherency operates at a granularity called the cache line

[PATCH] MIPS: bpf: Fix uninitialised target compiler error

l warnings being treated as errors Fix this by initialising "target" to 0. If it really is used uninitialised this would result in a jump to 0 and a detectable run time failure. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> Fixes: b6bd53f9c4e8 ("MIPS: Add missin

[PATCH v2] MIPS: SMP: Fix deadlock & online race

07e7f21f ("cpu/hotplug: Let upcoming cpu bring itself fully up"). Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> Fixes: 6f542ebeaee0 ("MIPS: Fix race on setting and getting cpu_online_mask") CC: Matija Glavinic Pecotic <matija.glavinic-pecotic@nokia.com

Re: [PATCH] MIPS: Revert "MIPS: Fix race on setting and getting cpu_online_mask"

Glavinic Pecotic <matija.glavinic-pecotic@nokia.com> wrote: On 08/23/2017 10:21 AM, Matt Redfearn wrote: As noted in the commit message, upstream differs in this area. The hotplug code now waits on a completion event in bringup_wait_for_ap, which is set by the starting CPU in cpuhp_onlin

[PATCH 1/3] clocksource/mips-gic-timer: Fix rcu_sched timeouts from multithreading

on the number of threads in the core (smp_num_siblings). This accounts for the greater average runtime of CPUs within a multithreading core. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> Fixes: b695d8e6ad6f ("clocksource: mips-gic: Use clockevents_config_and_register") Cc: <sta

[PATCH 2/3] clocksource/mips-gic-timer: Ensure IRQs disabled for read-update-write

registers through the VP redirect region, but given the timing critical nature of this code it just feels right to protect the whole read-update-write section, so move the local_irq_save before the current count is read. Signed-off-by: Matt Redfearn <matt.redfe...@mips.com> --- drivers/cloc

[PATCH 3/3] clocksource: mips-gic-timer: Add fastpath for local timer updates

Always accessing the compare register via the CM redirect region is (relatively) slow. If the timer being updated is the current CPUs then this can be shortcutted by writing to the CM VP local region. Signed-off-by: Matt Redfearn <matt.redfe...@mips.com> --- drivers/clocksource/mips-gic-t

Re: [PATCH v2] Update MIPS email addresses

id.yegos...@imgtec.com> Cc: Leonid Yegoshin <leonid.yegos...@mips.com> Cc: Marcin Nowakowski <marcin.nowakow...@imgtec.com> Cc: Marcin Nowakowski <marcin.nowakow...@mips.com> Cc: Matt Redfearn <matt.redfe...@imgtec.com> Cc: Matt Redfearn <matt.redfe...@mips.com>

Re: [PATCH V8 5/5] libata: Align DMA buffer to dma_get_cache_alignment()

On 18/10/17 14:03, Tejun Heo wrote: On Tue, Oct 17, 2017 at 04:05:42PM +0800, Huacai Chen wrote: In non-coherent DMA mode, kernel uses cache flushing operations to maintain I/O coherency, so in ata_do_dev_read_id() the DMA buffer should be aligned to ARCH_DMA_MINALIGN. Otherwise, If a DMA

Re: [PATCH 1/3] clocksource/mips-gic-timer: Fix rcu_sched timeouts from multithreading

On 18/10/17 21:34, Thomas Gleixner wrote: On Wed, 11 Oct 2017, Matt Redfearn wrote: When the MIPS GIC clockevent code was written, it appears to have inherited the 0x300 cycle min delta from the MIPS CPU timer driver. This is suboptimal for two reasons. Firstly, the CPU timer counts once

Re: [PATCH 1/3] clocksource/mips-gic-timer: Fix rcu_sched timeouts from multithreading

On 19/10/17 10:09, Daniel Lezcano wrote: On 11/10/2017 16:01, Matt Redfearn wrote: When the MIPS GIC clockevent code was written, it appears to have inherited the 0x300 cycle min delta from the MIPS CPU timer driver. This is suboptimal for two reasons. Firstly, the CPU timer counts once

[PATCH V2 3/3] clocksource: mips-gic-timer: Add fastpath for local timer updates

Always accessing the compare register via the CM redirect region is (relatively) slow. If the timer being updated is the current CPUs then this can be shortcutted by writing to the CM VP local region. Signed-off-by: Matt Redfearn <matt.redfe...@mips.com> --- drivers/clocksource/mips-gic-t

[PATCH 2/3] clocksource/mips-gic-timer: Remove pointless irq_save,restore

gic_next_event is always called with interrupts disabled, so the save / restore is pointless - remove it. Signed-off-by: Matt Redfearn <matt.redfe...@mips.com> Suggested-by: Thomas Gleixner <t...@linutronix.de> --- drivers/clocksource/mips-gic-timer.c | 2 -- 1 file changed,

[PATCH 1/3] clockevents: Retry programming min delta up to 10 times

times before giving up. Signed-off-by: James Hogan <jho...@kernel.org> Signed-off-by: Matt Redfearn <matt.redfe...@mips.com> Cc: Thomas Gleixner <t...@linutronix.de> Cc: Martin Schwidefsky <schwidef...@de.ibm.com> --- kernel/time/clockevents.c | 26 +++--

Re: [PATCH 2/2] MIPS: Add custom serial.h with BASE_BAUD override for generic kernel

On 28/11/17 14:35, Greg Kroah-Hartman wrote: On Wed, Nov 22, 2017 at 09:57:29AM +, Matt Redfearn wrote: Add a custom serial.h header for MIPS, allowing platforms to override the asm-generic version if required. The generic platform uses this header to set BASE_BAUD to 0. The generic

[PATCH v2] MIPS: Add custom serial.h with BASE_BAUD override for generic kernel

his commit, combined with "serial: 8250_early: Only set divisor if valid clk & baud" prevents the earlycon code setting a bad divisor and restores earlycon output. Fixes: 31cb9a8575ca ("earlycon: initialise baud field of earlycon device structure") Cc: stable <sta...@vger.k

[PATCH 1/2] serial: 8250_early: Only set divisor if valid clk & baud

rnel.org> # 4.14 Signed-off-by: Matt Redfearn <matt.redfe...@mips.com> --- drivers/tty/serial/8250/8250_early.c | 14 -- 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/tty/serial/8250/8250_early.c b/drivers/tty/serial/8250/8250_early.c index a

[PATCH 2/2] MIPS: Add custom serial.h with BASE_BAUD override for generic kernel

his commit, combined with "serial: 8250_early: Only set divisor if valid clk & baud" prevents the earlycon code setting a bad divisor and restores earlycon output. Fixes: 31cb9a8575ca ("earlycon: initialise baud field of earlycon device structure") Cc: stable <sta...@vger.k

[PATCH 1/2] MIPS: SMP-CPS: Remove duplicate assignment of core in play_dead

e duplicate. Signed-off-by: Matt Redfearn <matt.redfe...@mips.com> --- arch/mips/kernel/smp-cps.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index ecc1a853f48d..03f1026ad148 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/m

[PATCH 2/2] MIPS: pm-cps: Warn if JTAG presence will block power gating

powered down and will block a full power down of the cluster. We use a ratelimited pr_warn since this path will also be hit by cpu idle if it attempts to put cores into the powered down state. Signed-off-by: Matt Redfearn <matt.redfe...@mips.com> --- arch/mips/kernel/pm-cps.c | 13 +

[PATCH] MIPS: ath25: Avoid undefined early_serial_setup() without SERIAL_8250_CONSOLE

to the platform to force inclusion of SERIAL_8250_CONSOLE together with it's dependencies like TTY, HAS_IOMEM, etc, just make ath25_serial_setup() a no-op when the dependency is not selected in the kernel config. Signed-off-by: Matt Redfearn <matt.redfe...@mips.com> --- arch/mips/ath25/devices

[PATCH] watchdog: indydog: Add dependency on SGI_HAS_INDYDOG

undefined references to `sgimc' follow make: *** [Makefile:1005: vmlinux] Error 1 Fix this by ensuring that CONFIG_INDIDOG can only be selected when the necessary dependent platform symbols are built in. Fixes: da2a68b3eb47 ("watchdog: Enable COMPILE_TEST where possible") Signed-o

[PATCH 2/2] MIPS: RB532: Avoid undefined mac_pton without GENERIC_NET_UTILS

to force inclusion of GENERIC_NET_UTILS which is selected by CONFIG_NET, just exclude the setup of the MAC address if CONFIG_NET is not selected in the kernel config. Signed-off-by: Matt Redfearn <matt.redfe...@mips.com> --- arch/mips/rb532/devices.c | 4 1 file changed, 4 insertions(+)

[PATCH 1/2] MIPS: RB532: Avoid undefined early_serial_setup() without SERIAL_8250_CONSOLE

dependencies to the platform to force inclusion of SERIAL_8250_CONSOLE together with it's dependencies like TTY, HAS_IOMEM, etc, just exclude arch/mips/rb532/serial.c from the build when it's dependency is not selected in the kernel config. Reported-by: Ralf Baechle <r...@linux-mips.org> Signed-off-by

Re: [PATCH] MIPS: ath25: Avoid undefined early_serial_setup() without SERIAL_8250_CONSOLE

On 14/11/17 14:05, Ralf Baechle wrote: On Tue, Nov 14, 2017 at 01:29:17PM +, Matt Redfearn wrote: Currently MIPS allnoconfig with CONFIG_ATH25=y fails to link due to missing support for early_serial_setup(): LD vmlinux arch/mips/ath25/devices.o: In function ath25_serial_setup

Re: [PATCH] MIPS: Fix exception entry when CONFIG_EVA enabled

On 13/11/17 10:47, Maciej W. Rozycki wrote: On Tue, 31 Oct 2017, James Hogan wrote: I looked this over pretty carefully and it looks correct to me.  It makes no difference in the instructions generated by the non-EVA case.  I shouldn't have missed this :(. Reviewed-by: Corey Minyard

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