Hello,
On 15 August 2015 at 03:51, Bean Huo 霍斌斌 (beanhuo) wrote:
>>Hello,
>
>>with these patches SPI transfer errors are not silently ignored but rather
>>reported to spi-nor users.
>
>>This should prevent silently dropping data to the floor in cases when the SPI
>>transfer fails and the
Hello,
On 15 August 2015 at 03:51, Bean Huo 霍斌斌 (beanhuo) bean...@micron.com wrote:
Hello,
with these patches SPI transfer errors are not silently ignored but rather
reported to spi-nor users.
This should prevent silently dropping data to the floor in cases when the SPI
transfer fails and the
Hello,
On 17 August 2015 at 03:55, Jaehoon Chung jh80.ch...@samsung.com wrote:
Hi, Michal.
On 08/12/2015 09:23 PM, Michal Suchanek wrote:
The driver has open-coded test for SDIO cards. Use the mmc core provided
MMC_QUIRK_BROKEN_CLK_GATING flag instead.
Did you use the clock-gating for SDIO
On 14 August 2015 at 12:02, Andrew Murray wrote:
> On 14 August 2015 at 10:23, Michal Suchanek wrote:
>> mtdblock and ubi do not handle the situation when read returns less data
>> than requested. Loop in spi-nor until buffer is filled or an error is
>> returned.
>&g
On 14 August 2015 at 12:02, Andrew Murray amur...@embedded-bits.co.uk wrote:
On 14 August 2015 at 10:23, Michal Suchanek hramr...@gmail.com wrote:
mtdblock and ubi do not handle the situation when read returns less data
than requested. Loop in spi-nor until buffer is filled or an error
On 12 August 2015 at 15:19, Olliver Schinagl wrote:
> Hey,
>
> On 12-08-15 14:35, Hans de Goede wrote:
>>
>> Hi,
>>
>> On 12-08-15 14:23, Michal Suchanek wrote:
>>>
>>> When core does not set the MMC_QUIRK_BROKEN_CLK_GATING flag enable
>&g
rash with mmc clock gating enabled
>>> nonetheless.
>>>
>>> This patch sets the timeout to 750ms and adds debug prints which show
>>> how long enabling/disabling the clock took so more data can be collected
>>> from other systems.
>>>
>>> Si
On 12 August 2015 at 14:35, Hans de Goede wrote:
> Hi,
>
> On 12-08-15 14:23, Michal Suchanek wrote:
>>
>> When core does not set the MMC_QUIRK_BROKEN_CLK_GATING flag enable
>> automatic hardware controlled clock gating on the mmc interface.
>>
>> Signed-of
On 12 August 2015 at 13:55, Olliver Schinagl wrote:
> Actually, I've reverted hans's
>
> mmc: sunxi: Don't start commands while the card is busy
>
> and that makes it disapear as well. So it looks like that patch triggers the
> aggressiveness more?
It probably inserts delays which trigger the
On 12 August 2015 at 13:55, Olliver Schinagl oliver+l...@schinagl.nl wrote:
Actually, I've reverted hans's
mmc: sunxi: Don't start commands while the card is busy
and that makes it disapear as well. So it looks like that patch triggers the
aggressiveness more?
It probably inserts delays
On 12 August 2015 at 14:35, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 12-08-15 14:23, Michal Suchanek wrote:
When core does not set the MMC_QUIRK_BROKEN_CLK_GATING flag enable
automatic hardware controlled clock gating on the mmc interface.
Signed-off-by: Michal Suchanek hramr
long enabling/disabling the clock took so more data can be collected
from other systems.
Signed-off-by: Michal Suchanek hramr...@gmail.com
This is a big patch for just changing a timeout, most of this is in
extra verbosity which IMHO has little value, in the error path w
know we will have
On 12 August 2015 at 15:19, Olliver Schinagl oliver+l...@schinagl.nl wrote:
Hey,
On 12-08-15 14:35, Hans de Goede wrote:
Hi,
On 12-08-15 14:23, Michal Suchanek wrote:
When core does not set the MMC_QUIRK_BROKEN_CLK_GATING flag enable
automatic hardware controlled clock gating on the mmc
er_size;
>spi_message_add_tail([2], );
> spi_sync(spi, );
>
> On the spi-master side the driver would need to run:
> * if the spi-message (in this case the first byte) matches
>the "allowed" command pattern:
There is no 'allowed' pattern. Any message l
On 6 August 2015 at 23:33, Russell King - ARM Linux
wrote:
> On Thu, Aug 06, 2015 at 06:14:00PM +0200, Geert Uytterhoeven wrote:
>> On Thu, Aug 6, 2015 at 3:51 PM, Russell King - ARM Linux
>> wrote:
>> > On Thu, Aug 06, 2015 at 05:55:23PM +0530, Vignesh R wrote:
>> >> On the whole following are
On 6 August 2015 at 23:33, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Thu, Aug 06, 2015 at 06:14:00PM +0200, Geert Uytterhoeven wrote:
On Thu, Aug 6, 2015 at 3:51 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Thu, Aug 06, 2015 at 05:55:23PM +0530, Vignesh R
driver that
you will in fact not send a SPI message and reverse-engineer what
m25p80 really meant.
On 7 August 2015 at 10:35, Vignesh R vigne...@ti.com wrote:
On 08/07/2015 01:08 PM, Michal Suchanek wrote:
Now since the description is clearer it's obvious that ti-qspi cannot
work fully mmapped
On 6 August 2015 at 18:14, Geert Uytterhoeven wrote:
> On Thu, Aug 6, 2015 at 3:51 PM, Russell King - ARM Linux
> wrote:
>> On Thu, Aug 06, 2015 at 05:55:23PM +0530, Vignesh R wrote:
>>> On the whole following are my requirements:
>>> 1. to be able to communicate with non -flash SPI devices via
On 6 August 2015 at 13:23, Mark Brown wrote:
> On Thu, Aug 06, 2015 at 12:01:37PM +0200, Michal Suchanek wrote:
>
>> However, I am familiar m25p80.c and as I understand it the controller
>> is basically supposed to implement m25p80.c in hardware when this flag
>> is set.
On 6 August 2015 at 12:22, Russell King - ARM Linux
wrote:
> On Thu, Aug 06, 2015 at 12:01:37PM +0200, Michal Suchanek wrote:
>> Disclaimer: I am not familiar with the hardware for which this patch
>> adds support.
>>
>> However, I am familiar m25p80.c and as I u
On 6 August 2015 at 11:02, Mark Brown wrote:
> On Wed, Aug 05, 2015 at 02:56:09PM +0200, Michal Suchanek wrote:
>> On 5 August 2015 at 14:44, Mark Brown wrote:
>> > On Wed, Aug 05, 2015 at 02:40:01PM +0200, Michal Suchanek wrote:
>
>> >> I don't think sending 03
On 6 August 2015 at 11:02, Mark Brown broo...@kernel.org wrote:
On Wed, Aug 05, 2015 at 02:56:09PM +0200, Michal Suchanek wrote:
On 5 August 2015 at 14:44, Mark Brown broo...@kernel.org wrote:
On Wed, Aug 05, 2015 at 02:40:01PM +0200, Michal Suchanek wrote:
I don't think sending 03 or other
On 6 August 2015 at 13:23, Mark Brown broo...@kernel.org wrote:
On Thu, Aug 06, 2015 at 12:01:37PM +0200, Michal Suchanek wrote:
However, I am familiar m25p80.c and as I understand it the controller
is basically supposed to implement m25p80.c in hardware when this flag
is set.
But what
On 6 August 2015 at 12:22, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Thu, Aug 06, 2015 at 12:01:37PM +0200, Michal Suchanek wrote:
Disclaimer: I am not familiar with the hardware for which this patch
adds support.
However, I am familiar m25p80.c and as I understand
On 6 August 2015 at 18:14, Geert Uytterhoeven ge...@linux-m68k.org wrote:
On Thu, Aug 6, 2015 at 3:51 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Thu, Aug 06, 2015 at 05:55:23PM +0530, Vignesh R wrote:
On the whole following are my requirements:
1. to be able to communicate
On 5 August 2015 at 14:44, Mark Brown wrote:
> On Wed, Aug 05, 2015 at 02:40:01PM +0200, Michal Suchanek wrote:
>> On 5 August 2015 at 13:50, Mark Brown wrote:
>
>> > As far as I can tell you want to set a per spi_message flag saying that
>> > the message is a flash
On 5 August 2015 at 13:50, Mark Brown wrote:
> On Tue, Aug 04, 2015 at 11:29:52PM +0530, R, Vignesh wrote:
>> On 8/4/2015 9:21 PM, Mark Brown wrote:
>> > On Mon, Aug 03, 2015 at 10:27:19AM +0530, Vignesh R wrote:
>
>> > I still can't tell from the above what this interface is supposed to do.
>> >
On 4 August 2015 at 18:42, Marek Vasut wrote:
> On Tuesday, August 04, 2015 at 08:42:51 AM, Michal Suchanek wrote:
>> On 3 August 2015 at 23:46, Marek Vasut wrote:
>> > On Monday, August 03, 2015 at 08:39:01 PM, Michal Suchanek wrote:
>> >> Change the retur
On 4 August 2015 at 18:42, Marek Vasut ma...@denx.de wrote:
On Tuesday, August 04, 2015 at 08:42:51 AM, Michal Suchanek wrote:
On 3 August 2015 at 23:46, Marek Vasut ma...@denx.de wrote:
On Monday, August 03, 2015 at 08:39:01 PM, Michal Suchanek wrote:
Change the return value of spi-nor
On 5 August 2015 at 13:50, Mark Brown broo...@kernel.org wrote:
On Tue, Aug 04, 2015 at 11:29:52PM +0530, R, Vignesh wrote:
On 8/4/2015 9:21 PM, Mark Brown wrote:
On Mon, Aug 03, 2015 at 10:27:19AM +0530, Vignesh R wrote:
I still can't tell from the above what this interface is supposed to
On 5 August 2015 at 14:44, Mark Brown broo...@kernel.org wrote:
On Wed, Aug 05, 2015 at 02:40:01PM +0200, Michal Suchanek wrote:
On 5 August 2015 at 13:50, Mark Brown broo...@kernel.org wrote:
As far as I can tell you want to set a per spi_message flag saying that
the message is a flash
On 5 August 2015 at 07:35, Vignesh R wrote:
>
>
> On 08/05/2015 10:51 AM, Michal Suchanek wrote:
>> Hello,
>>
>> On 4 August 2015 at 19:59, R, Vignesh wrote:
>>>
>>>
>>> On 8/4/2015 9:21 PM, Mark Brown wrote:
>>>> On Mon, Aug 03
Hello,
On 4 August 2015 at 19:59, R, Vignesh wrote:
>
>
> On 8/4/2015 9:21 PM, Mark Brown wrote:
>> On Mon, Aug 03, 2015 at 10:27:19AM +0530, Vignesh R wrote:
>>
>>> @use_mmap_mode: Some SPI controller chips are optimized for interacting
>>> with serial flash memories. These chips have memory
On 3 August 2015 at 23:46, Marek Vasut wrote:
> On Monday, August 03, 2015 at 08:39:01 PM, Michal Suchanek wrote:
>> Change the return value of spi-nor device read and write methods to
>> allow returning amount of data transferred and errors as
>> read(2)/write(2) d
On 3 August 2015 at 23:46, Marek Vasut ma...@denx.de wrote:
On Monday, August 03, 2015 at 08:39:01 PM, Michal Suchanek wrote:
Change the return value of spi-nor device read and write methods to
allow returning amount of data transferred and errors as
read(2)/write(2) does.
Signed-off
Hello,
On 4 August 2015 at 19:59, R, Vignesh vigne...@ti.com wrote:
On 8/4/2015 9:21 PM, Mark Brown wrote:
On Mon, Aug 03, 2015 at 10:27:19AM +0530, Vignesh R wrote:
@use_mmap_mode: Some SPI controller chips are optimized for interacting
with serial flash memories. These chips have memory
On 5 August 2015 at 07:35, Vignesh R vigne...@ti.com wrote:
On 08/05/2015 10:51 AM, Michal Suchanek wrote:
Hello,
On 4 August 2015 at 19:59, R, Vignesh vigne...@ti.com wrote:
On 8/4/2015 9:21 PM, Mark Brown wrote:
On Mon, Aug 03, 2015 at 10:27:19AM +0530, Vignesh R wrote:
TI QSPI
On 31 July 2015 at 19:24, Boris Brezillon
wrote:
> On Fri, 31 Jul 2015 18:52:01 +0200
> Michal Suchanek wrote:
>
>
>> >
>> >> (*pparts)[i].offset = of_read_number(reg, a_cells);
>> >> (*pparts)[i].size = of_read_number(r
On 31 July 2015 at 18:06, Boris Brezillon
wrote:
> Hi Michal,
>
> On Thu, 30 Jul 2015 12:10:42 +0200
> Michal Suchanek wrote:
>
>> Parsing direct subnodes of a mtd device as partitions is unreliable
>> since the mtd device is also part of its bus subsystem and can cont
On 31 July 2015 at 18:06, Boris Brezillon
boris.brezil...@free-electrons.com wrote:
Hi Michal,
On Thu, 30 Jul 2015 12:10:42 +0200
Michal Suchanek hramr...@gmail.com wrote:
Parsing direct subnodes of a mtd device as partitions is unreliable
since the mtd device is also part of its bus
On 31 July 2015 at 19:24, Boris Brezillon
boris.brezil...@free-electrons.com wrote:
On Fri, 31 Jul 2015 18:52:01 +0200
Michal Suchanek hramr...@gmail.com wrote:
(*pparts)[i].offset = of_read_number(reg, a_cells);
(*pparts)[i].size = of_read_number(reg
On 30 July 2015 at 13:24, Marek Vasut wrote:
> On Monday, July 27, 2015 at 10:43:05 PM, Michal Suchanek wrote:
>> On 27 July 2015 at 19:43, Marek Vasut wrote:
>> > On Monday, July 27, 2015 at 11:46:25 AM, Michal Suchanek wrote:
>> >> On 24 July 201
On 29 July 2015 at 20:40, Mark Brown wrote:
> On Wed, Jul 29, 2015 at 08:21:34PM +0200, Michal Suchanek wrote:
>> On 29 July 2015 at 19:16, Mark Brown wrote:
>
>> >> It will not break anything. It will just spam dmesg.
>
>> > I'm confused - if all this chan
On 30 July 2015 at 13:24, Marek Vasut ma...@denx.de wrote:
On Monday, July 27, 2015 at 10:43:05 PM, Michal Suchanek wrote:
On 27 July 2015 at 19:43, Marek Vasut ma...@denx.de wrote:
On Monday, July 27, 2015 at 11:46:25 AM, Michal Suchanek wrote:
On 24 July 2015 at 10:34, Marek Vasut ma
On 29 July 2015 at 20:40, Mark Brown broo...@kernel.org wrote:
On Wed, Jul 29, 2015 at 08:21:34PM +0200, Michal Suchanek wrote:
On 29 July 2015 at 19:16, Mark Brown broo...@kernel.org wrote:
It will not break anything. It will just spam dmesg.
I'm confused - if all this change does
On 29 July 2015 at 19:16, Mark Brown wrote:
> On Wed, Jul 29, 2015 at 06:19:24PM +0200, Michal Suchanek wrote:
>> On 29 July 2015 at 16:00, Mark Brown wrote:
>
>> > I can't tell from this commit message what the issue you're trying to
>> > fix is, sorry. No
On 29 July 2015 at 16:00, Mark Brown wrote:
> On Wed, Jul 29, 2015 at 12:19:57PM +0200, Michal Suchanek wrote:
>
> Please use subject lines matching the style for the subsytsem so people
> can spot that the patch is in some way relevant.
>
>> The controller-data subn
On 29 July 2015 at 16:00, Mark Brown broo...@kernel.org wrote:
On Wed, Jul 29, 2015 at 12:19:57PM +0200, Michal Suchanek wrote:
Please use subject lines matching the style for the subsytsem so people
can spot that the patch is in some way relevant.
The controller-data subnode has
On 29 July 2015 at 19:16, Mark Brown broo...@kernel.org wrote:
On Wed, Jul 29, 2015 at 06:19:24PM +0200, Michal Suchanek wrote:
On 29 July 2015 at 16:00, Mark Brown broo...@kernel.org wrote:
I can't tell from this commit message what the issue you're trying to
fix is, sorry. Nodes without
On 28 July 2015 at 20:15, Marek Vasut wrote:
> On Tuesday, July 28, 2015 at 11:23:02 AM, Michal Suchanek wrote:
>> The spi_nor read and write functions pass thru the mtd retlen to the
>> chip-specific read and write function. This makes it difficult to check
>> for err
On 28 July 2015 at 16:38, Marek Vasut wrote:
> On Tuesday, July 28, 2015 at 04:36:29 PM, Michal Suchanek wrote:
>> On 28 July 2015 at 16:33, Marek Vasut wrote:
>> > On Tuesday, July 28, 2015 at 11:07:57 AM, Michal Suchanek wrote:
>> >> This 1.8V SPI NOR flash is
On 28 July 2015 at 16:33, Marek Vasut wrote:
> On Tuesday, July 28, 2015 at 11:07:57 AM, Michal Suchanek wrote:
>> This 1.8V SPI NOR flash is found on ARM Chromebook XE303C and reads
>> something like 25LQ32VIG in the middle.
>>
>> Signed-off-by: Michal Suchanek
>
On 27 July 2015 at 22:39, Brian Norris wrote:
> On Mon, Jul 27, 2015 at 08:30:43PM -0000, Michal Suchanek wrote:
> ...
>> The controller-data node contains no partition information and no other
>> subnodes with partition information exist.
>>
>> The ofp
On 27 July 2015 at 22:39, Brian Norris computersforpe...@gmail.com wrote:
On Mon, Jul 27, 2015 at 08:30:43PM -, Michal Suchanek wrote:
...
The controller-data node contains no partition information and no other
subnodes with partition information exist.
The ofpart code returns an error
On 28 July 2015 at 16:33, Marek Vasut ma...@denx.de wrote:
On Tuesday, July 28, 2015 at 11:07:57 AM, Michal Suchanek wrote:
This 1.8V SPI NOR flash is found on ARM Chromebook XE303C and reads
something like 25LQ32VIG in the middle.
Signed-off-by: Michal Suchanek hramr...@gmail.com
On 28 July 2015 at 16:38, Marek Vasut ma...@denx.de wrote:
On Tuesday, July 28, 2015 at 04:36:29 PM, Michal Suchanek wrote:
On 28 July 2015 at 16:33, Marek Vasut ma...@denx.de wrote:
On Tuesday, July 28, 2015 at 11:07:57 AM, Michal Suchanek wrote:
This 1.8V SPI NOR flash is found on ARM
On 28 July 2015 at 20:15, Marek Vasut ma...@denx.de wrote:
On Tuesday, July 28, 2015 at 11:23:02 AM, Michal Suchanek wrote:
The spi_nor read and write functions pass thru the mtd retlen to the
chip-specific read and write function. This makes it difficult to check
for errors in read and write
On 27 July 2015 at 19:43, Marek Vasut wrote:
> On Monday, July 27, 2015 at 11:46:25 AM, Michal Suchanek wrote:
>> On 24 July 2015 at 10:34, Marek Vasut wrote:
>> > On Thursday, July 23, 2015 at 07:03:47 PM, Michal Suchanek wrote:
>> >
>> Ok, so here is some
On 24 July 2015 at 10:34, Marek Vasut wrote:
> On Thursday, July 23, 2015 at 07:03:47 PM, Michal Suchanek wrote:
>
> Hi!
>
> [...]
>
>> >>> It's probably slower to set up DMA for 2-byte commands but it might
>> >>> work nonetheless.
>> >&
On 27 July 2015 at 19:43, Marek Vasut ma...@denx.de wrote:
On Monday, July 27, 2015 at 11:46:25 AM, Michal Suchanek wrote:
On 24 July 2015 at 10:34, Marek Vasut ma...@denx.de wrote:
On Thursday, July 23, 2015 at 07:03:47 PM, Michal Suchanek wrote:
Ok, so here is some summary.
I have a NOR
On 24 July 2015 at 10:34, Marek Vasut ma...@denx.de wrote:
On Thursday, July 23, 2015 at 07:03:47 PM, Michal Suchanek wrote:
Hi!
[...]
It's probably slower to set up DMA for 2-byte commands but it might
work nonetheless.
It is, the overhead will be considerable. It might help
On 24 July 2015 at 10:34, Marek Vasut wrote:
> On Thursday, July 23, 2015 at 07:03:47 PM, Michal Suchanek wrote:
>
> Hi!
>
> [...]
>
>> >>> It's probably slower to set up DMA for 2-byte commands but it might
>> >>> work nonetheless.
>> >&
On 24 July 2015 at 10:34, Marek Vasut ma...@denx.de wrote:
On Thursday, July 23, 2015 at 07:03:47 PM, Michal Suchanek wrote:
Hi!
[...]
It's probably slower to set up DMA for 2-byte commands but it might
work nonetheless.
It is, the overhead will be considerable. It might help
On 23 July 2015 at 18:46, Michal Suchanek wrote:
> On 22 July 2015 at 11:01, Marek Vasut wrote:
>> On Wednesday, July 22, 2015 at 10:38:14 AM, Michal Suchanek wrote:
>>> On 22 July 2015 at 10:24, Marek Vasut wrote:
>>> > On Wednesday, July 22, 2015 at 10:1
On 22 July 2015 at 11:01, Marek Vasut wrote:
> On Wednesday, July 22, 2015 at 10:38:14 AM, Michal Suchanek wrote:
>> On 22 July 2015 at 10:24, Marek Vasut wrote:
>> > On Wednesday, July 22, 2015 at 10:18:04 AM, Michal Suchanek wrote:
>> >> On 22 July 201
On 22 July 2015 at 11:01, Marek Vasut ma...@denx.de wrote:
On Wednesday, July 22, 2015 at 10:38:14 AM, Michal Suchanek wrote:
On 22 July 2015 at 10:24, Marek Vasut ma...@denx.de wrote:
On Wednesday, July 22, 2015 at 10:18:04 AM, Michal Suchanek wrote:
On 22 July 2015 at 09:58, Marek Vasut ma
On 23 July 2015 at 18:46, Michal Suchanek hramr...@gmail.com wrote:
On 22 July 2015 at 11:01, Marek Vasut ma...@denx.de wrote:
On Wednesday, July 22, 2015 at 10:38:14 AM, Michal Suchanek wrote:
On 22 July 2015 at 10:24, Marek Vasut ma...@denx.de wrote:
On Wednesday, July 22, 2015 at 10:18:04
On 22 July 2015 at 10:24, Marek Vasut wrote:
> On Wednesday, July 22, 2015 at 10:18:04 AM, Michal Suchanek wrote:
>> On 22 July 2015 at 09:58, Marek Vasut wrote:
>> > On Wednesday, July 22, 2015 at 09:45:27 AM, Michal Suchanek wrote:
>> >> On 22 July 201
On 22 July 2015 at 09:58, Marek Vasut wrote:
> On Wednesday, July 22, 2015 at 09:45:27 AM, Michal Suchanek wrote:
>> On 22 July 2015 at 09:33, Marek Vasut wrote:
>> > On Wednesday, July 22, 2015 at 09:30:54 AM, Michal Suchanek wrote:
>> >> On 22 July 20
On 22 July 2015 at 09:33, Marek Vasut wrote:
> On Wednesday, July 22, 2015 at 09:30:54 AM, Michal Suchanek wrote:
>> On 22 July 2015 at 06:49, Vinod Koul wrote:
>> > On Tue, Jul 21, 2015 at 10:14:11AM +0200, Michal Suchanek wrote:
>> >> > Or alternatively
On 22 July 2015 at 06:49, Vinod Koul wrote:
> On Tue, Jul 21, 2015 at 10:14:11AM +0200, Michal Suchanek wrote:
>> > Or alternatively we could publish the limitations of the channel using
>> > capabilities so SPI knows I have a dmaengine channel and it can transfer
&
On 22 July 2015 at 06:49, Vinod Koul vinod.k...@intel.com wrote:
On Tue, Jul 21, 2015 at 10:14:11AM +0200, Michal Suchanek wrote:
Or alternatively we could publish the limitations of the channel using
capabilities so SPI knows I have a dmaengine channel and it can transfer
max N
length
On 22 July 2015 at 09:58, Marek Vasut ma...@denx.de wrote:
On Wednesday, July 22, 2015 at 09:45:27 AM, Michal Suchanek wrote:
On 22 July 2015 at 09:33, Marek Vasut ma...@denx.de wrote:
On Wednesday, July 22, 2015 at 09:30:54 AM, Michal Suchanek wrote:
On 22 July 2015 at 06:49, Vinod Koul
On 22 July 2015 at 09:33, Marek Vasut ma...@denx.de wrote:
On Wednesday, July 22, 2015 at 09:30:54 AM, Michal Suchanek wrote:
On 22 July 2015 at 06:49, Vinod Koul vinod.k...@intel.com wrote:
On Tue, Jul 21, 2015 at 10:14:11AM +0200, Michal Suchanek wrote:
Or alternatively we could publish
On 22 July 2015 at 10:24, Marek Vasut ma...@denx.de wrote:
On Wednesday, July 22, 2015 at 10:18:04 AM, Michal Suchanek wrote:
On 22 July 2015 at 09:58, Marek Vasut ma...@denx.de wrote:
On Wednesday, July 22, 2015 at 09:45:27 AM, Michal Suchanek wrote:
On 22 July 2015 at 09:33, Marek Vasut ma
Hello,
On 21 July 2015 at 06:29, Vinod Koul wrote:
> On Sun, Jul 19, 2015 at 09:01:34PM +0200, Michal Suchanek wrote:
>> Hello,
>>
>> On 15 July 2015 at 17:59, Brian Norris wrote:
>> > Hi Michal,
>> >
>> > On Wed, Jul 15, 2015 at 01:52:27PM +0200,
Hello,
On 21 July 2015 at 06:29, Vinod Koul vinod.k...@intel.com wrote:
On Sun, Jul 19, 2015 at 09:01:34PM +0200, Michal Suchanek wrote:
Hello,
On 15 July 2015 at 17:59, Brian Norris computersforpe...@gmail.com wrote:
Hi Michal,
On Wed, Jul 15, 2015 at 01:52:27PM +0200, Marek Vasut
Hello,
On 15 July 2015 at 17:59, Brian Norris wrote:
> Hi Michal,
>
> On Wed, Jul 15, 2015 at 01:52:27PM +0200, Marek Vasut wrote:
>> The problem is, if you add a new DT binding, you'd have to support it
>> forever, no matter how bad idea that binding turned out to be.
>
> Agreed, and a solid
Hello,
On 15 July 2015 at 17:59, Brian Norris computersforpe...@gmail.com wrote:
Hi Michal,
On Wed, Jul 15, 2015 at 01:52:27PM +0200, Marek Vasut wrote:
The problem is, if you add a new DT binding, you'd have to support it
forever, no matter how bad idea that binding turned out to be.
On 4 June 2015 at 19:15, Richard Cochran wrote:
> On Thu, Jun 04, 2015 at 10:31:45AM +0200, Michal Suchanek wrote:
>> You might want to try to run the bus at 60MHz or 80MHz and then the
>> values would probably again be different.
>>
>> The first two values are set
On 4 June 2015 at 19:15, Richard Cochran richardcoch...@gmail.com wrote:
On Thu, Jun 04, 2015 at 10:31:45AM +0200, Michal Suchanek wrote:
You might want to try to run the bus at 60MHz or 80MHz and then the
values would probably again be different.
The first two values are set in DT so
H
On 2 June 2015 at 16:17, Michal Suchanek wrote:
> On 2 June 2015 at 15:08, Vinod Koul wrote:
>> On Sat, May 30, 2015 at 09:37:07PM +0200, Michal Suchanek wrote:
>>> Hello,
>>>
>>> I was trying to read the SPI NOR flash and found that the pl330
&
H
On 2 June 2015 at 16:17, Michal Suchanek hramr...@gmail.com wrote:
On 2 June 2015 at 15:08, Vinod Koul vinod.k...@intel.com wrote:
On Sat, May 30, 2015 at 09:37:07PM +0200, Michal Suchanek wrote:
Hello,
I was trying to read the SPI NOR flash and found that the pl330
controller dma
On 4 June 2015 at 17:28, Marek Vasut wrote:
> On Thursday, June 04, 2015 at 06:54:00 AM, Michal Suchanek wrote:
>> On 4 June 2015 at 00:58, Marek Vasut wrote:
>> > On Wednesday, June 03, 2015 at 11:26:40 PM, Michal Suchanek wrote:
>> >> On Exynos it is necessary to
On 4 June 2015 at 12:26, Mark Brown wrote:
> On Thu, Jun 04, 2015 at 11:33:37AM +0200, Michal Suchanek wrote:
>> On 4 June 2015 at 11:16, Mark Brown wrote:
>
>> > Also for this patch (which just adds some trace) there isn't any clear
>> > reason for it to be sen
Hello,
On 4 June 2015 at 11:16, Mark Brown wrote:
> On Wed, Jun 03, 2015 at 09:26:42PM -0000, Michal Suchanek wrote:
>> The SPI NOR transfers mysteriously fail so add more debug prints about
>> SPI transactions.
>
> Please try to only send patches to relevant people - the
On 4 June 2015 at 08:42, Geert Uytterhoeven wrote:
> On Wed, Jun 3, 2015 at 11:26 PM, Michal Suchanek wrote:
>> On sunxi the SPI controller currently does not have DMA support and fails
>> any transfer larger than 63 bytes.
>
> This is a driver limitation, not
On 4 June 2015 at 17:28, Marek Vasut ma...@denx.de wrote:
On Thursday, June 04, 2015 at 06:54:00 AM, Michal Suchanek wrote:
On 4 June 2015 at 00:58, Marek Vasut ma...@denx.de wrote:
On Wednesday, June 03, 2015 at 11:26:40 PM, Michal Suchanek wrote:
On Exynos it is necessary to set SPI
On 4 June 2015 at 12:26, Mark Brown broo...@kernel.org wrote:
On Thu, Jun 04, 2015 at 11:33:37AM +0200, Michal Suchanek wrote:
On 4 June 2015 at 11:16, Mark Brown broo...@kernel.org wrote:
Also for this patch (which just adds some trace) there isn't any clear
reason for it to be sent
On 4 June 2015 at 08:42, Geert Uytterhoeven ge...@linux-m68k.org wrote:
On Wed, Jun 3, 2015 at 11:26 PM, Michal Suchanek hramr...@gmail.com wrote:
On sunxi the SPI controller currently does not have DMA support and fails
any transfer larger than 63 bytes.
This is a driver limitation
Hello,
On 4 June 2015 at 11:16, Mark Brown broo...@kernel.org wrote:
On Wed, Jun 03, 2015 at 09:26:42PM -, Michal Suchanek wrote:
The SPI NOR transfers mysteriously fail so add more debug prints about
SPI transactions.
Please try to only send patches to relevant people - the list
On 4 June 2015 at 00:58, Marek Vasut wrote:
> On Wednesday, June 03, 2015 at 11:26:40 PM, Michal Suchanek wrote:
>> On Exynos it is necessary to set SPI controller parameters that apply to
>> a SPI slave in a DT subnode of the slave device. The ofpart code returns
&
On 4 June 2015 at 01:03, Marek Vasut wrote:
> On Wednesday, June 03, 2015 at 11:26:41 PM, Michal Suchanek wrote:
>> On sunxi the SPI controller currently does not have DMA support and fails
>> any transfer larger than 63 bytes.
>>
>> On Exynos the pl330 DMA controlle
On 4 June 2015 at 00:53, Marek Vasut wrote:
> On Wednesday, June 03, 2015 at 11:26:39 PM, Michal Suchanek wrote:
>> Hello,
>
> Hi,
>
>> this patch series makes it possible to access the SPI NOR flash in the
>> Samsung XE303 'Snow' Chromebook.
>>
>>
On 4 June 2015 at 00:58, Marek Vasut ma...@denx.de wrote:
On Wednesday, June 03, 2015 at 11:26:40 PM, Michal Suchanek wrote:
On Exynos it is necessary to set SPI controller parameters that apply to
a SPI slave in a DT subnode of the slave device. The ofpart code returns
an error when
On 4 June 2015 at 01:03, Marek Vasut ma...@denx.de wrote:
On Wednesday, June 03, 2015 at 11:26:41 PM, Michal Suchanek wrote:
On sunxi the SPI controller currently does not have DMA support and fails
any transfer larger than 63 bytes.
On Exynos the pl330 DMA controller fails any transfer
On 4 June 2015 at 00:53, Marek Vasut ma...@denx.de wrote:
On Wednesday, June 03, 2015 at 11:26:39 PM, Michal Suchanek wrote:
Hello,
Hi,
this patch series makes it possible to access the SPI NOR flash in the
Samsung XE303 'Snow' Chromebook.
Unfortunately not all issues are resolved
On 2 June 2015 at 15:08, Vinod Koul wrote:
> On Sat, May 30, 2015 at 09:37:07PM +0200, Michal Suchanek wrote:
>> Hello,
>>
>> I was trying to read the SPI NOR flash and found that the pl330
>> controller dma mysteriously fails.
>
> Adding Robert,
>
>>
On 2 June 2015 at 15:08, Vinod Koul vinod.k...@intel.com wrote:
On Sat, May 30, 2015 at 09:37:07PM +0200, Michal Suchanek wrote:
Hello,
I was trying to read the SPI NOR flash and found that the pl330
controller dma mysteriously fails.
Adding Robert,
There is the problem that the 256
Hello,
I was trying to read the SPI NOR flash and found that the pl330
controller dma mysteriously fails.
There is the problem that the 256 bytes of dma program buffer does not
suffice for the whole of 4M of the flash memory so all of it cannot be
possibly transferred in one go with the pl330
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