Quoting Alex Elder (2014-05-30 13:53:02)
> Use a counter rather than a Boolean to track whether write access to
> a CCU has been enabled or not. This will allow more than one of
> these requests to be nested.
>
> Note that __ccu_write_enable() and __ccu_write_disable() calls all
> come in pairs,
Quoting Alex Elder (2014-05-30 13:53:02)
Use a counter rather than a Boolean to track whether write access to
a CCU has been enabled or not. This will allow more than one of
these requests to be nested.
Note that __ccu_write_enable() and __ccu_write_disable() calls all
come in pairs, and
Quoting Alex Elder (2014-05-30 13:53:04)
+static int kona_clk_prepare(struct clk_hw *hw)
{
+ struct kona_clk *bcm_clk = to_kona_clk(hw);
+ struct ccu_data *ccu = bcm_clk-ccu;
+ unsigned long flags;
+ int ret = 0;
+
+ flags = ccu_lock(ccu);
+
Quoting Colin King (2014-04-12 10:59:14)
From: Colin Ian King colin.k...@canonical.com
commit a183da63 introduced a new error return path that does
not kfree icst if the kmemdup of desc-params fails.
Signed-off-by: Colin Ian King colin.k...@canonical.com
Applied to clk-next.
Thanks,
Mike
Quoting Nishanth Menon (2014-05-29 16:22:45)
> On 05/26/2014 08:07 AM, Thierry Reding wrote:
> > On Wed, May 14, 2014 at 12:35:18PM -0700, Mike Turquette wrote:
> >> Quoting Thierry Reding (2014-05-14 07:27:40)
> > [...]
> >>> As for shared clocks I'm only aware
Quoting Doug Anderson (2014-05-29 14:21:36)
> Right now if you've got earlyprintk enabled on exynos5420-peach-pit
> then you'll get a hang on boot. Here's why:
>
> 1. The i2c-s3c2410 driver will probe at subsys_initcall. It will
>enable its clock and disable it. This is the clock "i2c2".
>
Quoting Alex Elder (2014-05-29 09:53:50)
> On 05/29/2014 11:35 AM, Mike Turquette wrote:
> > Quoting Alex Elder (2014-05-29 06:26:15)
> >> On 05/23/2014 07:53 PM, Mike Turquette wrote:
> >>> The above seems like a lot effort to go to. Why not skip all of
Quoting Alex Elder (2014-05-29 06:26:15)
> On 05/23/2014 07:53 PM, Mike Turquette wrote:
> > The above seems like a lot effort to go to. Why not skip all of this and
> > just implement the prerequisite logic in the .enable & .disable
> > callbacks? E.g. your kona clk .e
.
Maxime COQUELIN (1):
clk: divider: Fix table round up function
Mike Turquette (1):
Merge tag 'clk-tegra-fixes-3.15' of
git://nv-tegra.nvidia.com/user/pdeschrijver/linux into clk-fixes
Thierry Reding (3):
clk: tegra: Fix PLLE programming
clk: tegra: Introduce divider
.
Maxime COQUELIN (1):
clk: divider: Fix table round up function
Mike Turquette (1):
Merge tag 'clk-tegra-fixes-3.15' of
git://nv-tegra.nvidia.com/user/pdeschrijver/linux into clk-fixes
Thierry Reding (3):
clk: tegra: Fix PLLE programming
clk: tegra: Introduce divider
Quoting Alex Elder (2014-05-29 06:26:15)
On 05/23/2014 07:53 PM, Mike Turquette wrote:
The above seems like a lot effort to go to. Why not skip all of this and
just implement the prerequisite logic in the .enable .disable
callbacks? E.g. your kona clk .enable callback would look like:
I
Quoting Alex Elder (2014-05-29 09:53:50)
On 05/29/2014 11:35 AM, Mike Turquette wrote:
Quoting Alex Elder (2014-05-29 06:26:15)
On 05/23/2014 07:53 PM, Mike Turquette wrote:
The above seems like a lot effort to go to. Why not skip all of this and
just implement the prerequisite logic
Quoting Doug Anderson (2014-05-29 14:21:36)
Right now if you've got earlyprintk enabled on exynos5420-peach-pit
then you'll get a hang on boot. Here's why:
1. The i2c-s3c2410 driver will probe at subsys_initcall. It will
enable its clock and disable it. This is the clock i2c2.
2. The
Quoting Nishanth Menon (2014-05-29 16:22:45)
On 05/26/2014 08:07 AM, Thierry Reding wrote:
On Wed, May 14, 2014 at 12:35:18PM -0700, Mike Turquette wrote:
Quoting Thierry Reding (2014-05-14 07:27:40)
[...]
As for shared clocks I'm only aware of one use-case, namely EMC scaling.
Using
vers/clk/berlin/berlin2-pll.c
> create mode 100644 drivers/clk/berlin/berlin2-pll.h
> create mode 100644 drivers/clk/berlin/bg2.c
> create mode 100644 drivers/clk/berlin/bg2q.c
> create mode 100644 drivers/clk/berlin/common.h
> create mode 100644 include/dt-bindings/clock/ber
Quoting Tero Kristo (2014-05-19 05:23:10)
> On 05/19/2014 02:25 PM, Julia Lawall wrote:
> > From: Julia Lawall
> >
> > Add a returned error code in the MAX_APLL_WAIT_TRIES case. Remove the
> > updating of the return variable r to 0 if MAX_APLL_WAIT_TRIES is not yet
> > reached, because r is
Quoting Saravana Kannan (2014-05-28 10:47:46)
> On 05/26/2014 04:14 AM, Peter De Schrijver wrote:
> > On Sat, May 24, 2014 at 12:24:32AM +0200, Saravana Kannan wrote:
> >> On 05/23/2014 03:59 AM, Peter De Schrijver wrote:
> >>> This patch flattens the clk tree in CCF debugfs. Instead of
Quoting Kukjin Kim (2014-05-27 21:49:49)
> Mike Turquette wrote:
> >
> > Quoting Tarek Dakhran (2014-05-25 20:23:32)
> > > The EXYNOS5410 clocks are statically listed and registered
> > > using the Samsung specific common clock helper functions.
> &g
Quoting Tero Kristo (2014-05-19 05:23:10)
On 05/19/2014 02:25 PM, Julia Lawall wrote:
From: Julia Lawall julia.law...@lip6.fr
Add a returned error code in the MAX_APLL_WAIT_TRIES case. Remove the
updating of the return variable r to 0 if MAX_APLL_WAIT_TRIES is not yet
reached, because
...@infradead.org
Cc: Mike Turquette mturque...@linaro.org
Cc: Alexandre Belloni alexandre.bell...@free-electrons.com
Cc: Jisheng Zhang jszh...@marvell.com
Cc: devicet...@vger.kernel.org
Cc: linux-...@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
--
1.9.1
Quoting Kukjin Kim (2014-05-27 21:49:49)
Mike Turquette wrote:
Quoting Tarek Dakhran (2014-05-25 20:23:32)
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Quoting Saravana Kannan (2014-05-28 10:47:46)
On 05/26/2014 04:14 AM, Peter De Schrijver wrote:
On Sat, May 24, 2014 at 12:24:32AM +0200, Saravana Kannan wrote:
On 05/23/2014 03:59 AM, Peter De Schrijver wrote:
This patch flattens the clk tree in CCF debugfs. Instead of representing
the
Quoting Tomasz Figa (2014-05-07 09:24:10)
> Commit c686078 ("clk: divider: Add round to closest divider") introduced
> a helper function to check whether given divisor is the best one instead
> of direct check. However due to int type used instead of unsigned long
> for passing calculated rates to
Quoting Rafael J. Wysocki (2014-05-26 04:22:32)
> On Monday, May 26, 2014 11:59:09 AM Viresh Kumar wrote:
> > On 23 May 2014 21:44, Sören Brinkmann wrote:
> > > Viresh: Could you imagine something similar for cpufreq? You suggested
> > > migrating to Hz resolution. I guess that would ideally mean
Quoting Nishanth Menon (2014-05-15 05:33:13)
> On 05/15/2014 07:18 AM, Kishon Vijay Abraham I wrote:
> > Hi,
> >
> > On Thursday 15 May 2014 05:42 PM, Nishanth Menon wrote:
> >> On Thu, May 15, 2014 at 6:59 AM, Kishon Vijay Abraham I
> >> wrote:
> >>> Hi Nishant,
> >>>
> >>> On Thursday 15 May
Quoting Boris BREZILLON (2014-05-27 04:39:28)
> Signed-off-by: Boris BREZILLON
Applied to clk-next.
Regards,
Mike
> ---
> MAINTAINERS | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 1066264..40c5580 100644
> --- a/MAINTAINERS
> +++
Quoting Alex Elder (2014-05-27 09:56:56)
> Implement the clk->determine_rate method for Broadcom Kona peripheral
> clocks. This allows a peripheral clock to be re-parented in order to
> satisfy a rate change request. This takes the place of the previous
> kona_peri_clk_round_rate()
Quoting Tarek Dakhran (2014-05-25 20:23:32)
> The EXYNOS5410 clocks are statically listed and registered
> using the Samsung specific common clock helper functions.
>
> Signed-off-by: Tarek Dakhran
> Signed-off-by: Vyacheslav Tyrtov
> ---
> .../devicetree/bindings/clock/exynos5410-clock.txt |
Quoting Tarek Dakhran (2014-05-25 20:23:32)
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
Quoting Alex Elder (2014-05-27 09:56:56)
Implement the clk-determine_rate method for Broadcom Kona peripheral
clocks. This allows a peripheral clock to be re-parented in order to
satisfy a rate change request. This takes the place of the previous
kona_peri_clk_round_rate() functionality,
Quoting Boris BREZILLON (2014-05-27 04:39:28)
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
Applied to clk-next.
Regards,
Mike
---
MAINTAINERS | 5 +
1 file changed, 5 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 1066264..40c5580 100644
---
Quoting Nishanth Menon (2014-05-15 05:33:13)
On 05/15/2014 07:18 AM, Kishon Vijay Abraham I wrote:
Hi,
On Thursday 15 May 2014 05:42 PM, Nishanth Menon wrote:
On Thu, May 15, 2014 at 6:59 AM, Kishon Vijay Abraham I kis...@ti.com
wrote:
Hi Nishant,
On Thursday 15 May 2014 05:16
Quoting Rafael J. Wysocki (2014-05-26 04:22:32)
On Monday, May 26, 2014 11:59:09 AM Viresh Kumar wrote:
On 23 May 2014 21:44, Sören Brinkmann soren.brinkm...@xilinx.com wrote:
Viresh: Could you imagine something similar for cpufreq? You suggested
migrating to Hz resolution. I guess that
Quoting Tomasz Figa (2014-05-07 09:24:10)
Commit c686078 (clk: divider: Add round to closest divider) introduced
a helper function to check whether given divisor is the best one instead
of direct check. However due to int type used instead of unsigned long
for passing calculated rates to this
Quoting Alex Elder (2014-05-23 16:24:31)
> On 05/23/2014 06:18 PM, Mike Turquette wrote:
> > Quoting Alex Elder (2014-05-20 06:24:57)
> >> Implement the clk->determine_rate method for Broadcom Kona peripheral
> >> clocks. This allows a peripheral clock to be re-par
Quoting Alex Elder (2014-05-20 05:52:39)
> @@ -743,11 +746,16 @@ struct clk *kona_clk_setup(struct kona_clk *bcm_clk)
> clk = clk_register(NULL, _clk->hw);
> if (IS_ERR(clk)) {
> pr_err("%s: error registering clock %s (%ld)\n", __func__,
> -
Quoting Alex Elder (2014-05-20 05:52:38)
> Add a flag that tracks whether a clock has already been initialized.
> This will be used by the next patch to avoid initializing a clock
> more than once when it's listed as a prerequisite.
>
> Signed-off-by: Alex Elder
> ---
>
Quoting Alex Elder (2014-05-20 06:24:57)
> Implement the clk->determine_rate method for Broadcom Kona peripheral
> clocks. This allows a peripheral clock to be re-parented in order to
> satisfy a rate change request. This takes the place of the previous
> kona_peri_clk_round_rate()
Quoting Georgi Djakov (2014-05-20 09:50:54)
> The address of the blsp2_ahb_clk register is incorrect. Fix it.
>
> Signed-off-by: Georgi Djakov
Applied to clk-next.
Regards,
Mike
> ---
> drivers/clk/qcom/gcc-msm8974.c |2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
Quoting Krzysztof Kozlowski (2014-05-21 04:22:58)
> Hi,
>
>
> This is actually a resend of previous patches, rebased on latest
> 3.15-rc5. There are no changes, beside rebasing.
>
> The first two fixes were posted previously as separate patches and they
> didn't get review [1]. I am attaching
Quoting Valentin Ilie (2014-04-22 06:15:54)
> When it fails to allocate div, gate should be free'd before return
>
> Signed-off-by: Valentin Ilie
Taken into clk-fixes.
Regards,
Mike
> ---
> drivers/clk/st/clkgen-pll.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git
_MAX.
>
> Reported-by: Fabio Estevam
> Reported-by: Shawn Guo
> Tested-by: Fabio Estevam
> Cc: Mike Turquette
> Signed-off-by: Maxime Coquelin
Pulled into clk-fixes for -rc7.
Regards,
Mike
> ---
> drivers/clk/clk-divider.c | 2 +-
> 1 file changed, 1 insertion
Quoting Nishanth Menon (2014-05-16 03:45:57)
> Hi,
>
> This patch series has been carried over in vendor kernel for quiet
> few years now.
>
> Unfortunately, it was very recently re-discovered and upstream kernel
> is noticed to be broken for OMAP5 1.5GHz - at least we are operating
> DPLL at
ions, gating, and synchronization.
>
> Reviewed-by: Arnd Bergmann
> Signed-off-by: Ivan Khoronzhuk
Acked-by: Mike Turquette
Regards,
Mike
> ---
> .../bindings/clock/ti-keystone-pllctrl.txt | 20
>
> 1 file changed, 20 insertions(+)
>
Quoting Tarek Dakhran (2014-05-23 03:35:42)
> The EXYNOS5410 clocks are statically listed and registered
> using the Samsung specific common clock helper functions.
>
> Signed-off-by: Tarek Dakhran
> Signed-off-by: Vyacheslav Tyrtov
Quick glance over it. Looks good to me.
Regards,
Mike
> ---
Quoting Tarek Dakhran (2014-05-23 03:35:42)
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
Quick glance over it.
, and synchronization.
Reviewed-by: Arnd Bergmann a...@arndb.de
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
Acked-by: Mike Turquette mturque...@linaro.org
Regards,
Mike
---
.../bindings/clock/ti-keystone-pllctrl.txt | 20
1 file changed, 20 insertions
Quoting Nishanth Menon (2014-05-16 03:45:57)
Hi,
This patch series has been carried over in vendor kernel for quiet
few years now.
Unfortunately, it was very recently re-discovered and upstream kernel
is noticed to be broken for OMAP5 1.5GHz - at least we are operating
DPLL at frequency
...@gmail.com
Reported-by: Shawn Guo shawn@freescale.com
Tested-by: Fabio Estevam feste...@gmail.com
Cc: Mike Turquette mike.turque...@linaro.org
Signed-off-by: Maxime Coquelin maxime.coque...@st.com
Pulled into clk-fixes for -rc7.
Regards,
Mike
---
drivers/clk/clk-divider.c | 2 +-
1 file
Quoting Valentin Ilie (2014-04-22 06:15:54)
When it fails to allocate div, gate should be free'd before return
Signed-off-by: Valentin Ilie valentin.i...@gmail.com
Taken into clk-fixes.
Regards,
Mike
---
drivers/clk/st/clkgen-pll.c | 4 +++-
1 file changed, 3 insertions(+), 1
Quoting Krzysztof Kozlowski (2014-05-21 04:22:58)
Hi,
This is actually a resend of previous patches, rebased on latest
3.15-rc5. There are no changes, beside rebasing.
The first two fixes were posted previously as separate patches and they
didn't get review [1]. I am attaching them
Quoting Georgi Djakov (2014-05-20 09:50:54)
The address of the blsp2_ahb_clk register is incorrect. Fix it.
Signed-off-by: Georgi Djakov gdja...@mm-sol.com
Applied to clk-next.
Regards,
Mike
---
drivers/clk/qcom/gcc-msm8974.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Quoting Alex Elder (2014-05-20 06:24:57)
Implement the clk-determine_rate method for Broadcom Kona peripheral
clocks. This allows a peripheral clock to be re-parented in order to
satisfy a rate change request. This takes the place of the previous
kona_peri_clk_round_rate() functionality,
Quoting Alex Elder (2014-05-20 05:52:38)
Add a flag that tracks whether a clock has already been initialized.
This will be used by the next patch to avoid initializing a clock
more than once when it's listed as a prerequisite.
Signed-off-by: Alex Elder el...@linaro.org
---
Quoting Alex Elder (2014-05-20 05:52:39)
@@ -743,11 +746,16 @@ struct clk *kona_clk_setup(struct kona_clk *bcm_clk)
clk = clk_register(NULL, bcm_clk-hw);
if (IS_ERR(clk)) {
pr_err(%s: error registering clock %s (%ld)\n, __func__,
-
Quoting Alex Elder (2014-05-23 16:24:31)
On 05/23/2014 06:18 PM, Mike Turquette wrote:
Quoting Alex Elder (2014-05-20 06:24:57)
Implement the clk-determine_rate method for Broadcom Kona peripheral
clocks. This allows a peripheral clock to be re-parented in order to
satisfy a rate change
Quoting Sylwester Nawrocki (2014-05-19 10:22:51)
> diff --git a/Documentation/devicetree/bindings/clock/clock-bindings.txt
> b/Documentation/devicetree/bindings/clock/clock-bindings.txt
> index 700e7aa..bee649b 100644
> --- a/Documentation/devicetree/bindings/clock/clock-bindings.txt
> +++
Quoting Sylwester Nawrocki (2014-04-11 05:25:49)
> >> +==Assigned clock parents and rates==
> >> +
> >> +Some platforms require static initial configuration of parts of the clocks
> >> +controller. Such a configuration can be specified in a clock consumer node
> >> +through clock-parents and
Quoting Sören Brinkmann (2014-05-22 13:32:09)
> On Thu, 2014-05-22 at 08:20PM +0200, Uwe Kleine-König wrote:
> > Hello Sören,
> >
> > On Thu, May 22, 2014 at 11:03:00AM -0700, Sören Brinkmann wrote:
> > > On Wed, 2014-05-21 at 01:33PM -0700, Mike Turquette wrote:
&g
Quoting Linus Walleij (2014-04-15 01:29:45)
> The IM-PD1 PrimeCells all have pclk assignments though this clock
> cannot be controlled, and we need to provide this as a dummy
> clock for the PL061 GPIO driver to probe, so let's assign it to
> all the cells on the board.
>
>
Quoting Linus Walleij (2014-04-15 01:29:45)
The IM-PD1 PrimeCells all have pclk assignments though this clock
cannot be controlled, and we need to provide this as a dummy
clock for the PL061 GPIO driver to probe, so let's assign it to
all the cells on the board.
Cc: Mike Turquette mturque
Quoting Sören Brinkmann (2014-05-22 13:32:09)
On Thu, 2014-05-22 at 08:20PM +0200, Uwe Kleine-König wrote:
Hello Sören,
On Thu, May 22, 2014 at 11:03:00AM -0700, Sören Brinkmann wrote:
On Wed, 2014-05-21 at 01:33PM -0700, Mike Turquette wrote:
Quoting Uwe Kleine-König (2014-05-21 11
Quoting Sylwester Nawrocki (2014-04-11 05:25:49)
+==Assigned clock parents and rates==
+
+Some platforms require static initial configuration of parts of the clocks
+controller. Such a configuration can be specified in a clock consumer node
+through clock-parents and clock-rates DT
Quoting Sylwester Nawrocki (2014-05-19 10:22:51)
diff --git a/Documentation/devicetree/bindings/clock/clock-bindings.txt
b/Documentation/devicetree/bindings/clock/clock-bindings.txt
index 700e7aa..bee649b 100644
--- a/Documentation/devicetree/bindings/clock/clock-bindings.txt
+++
Quoting Uwe Kleine-König (2014-05-21 11:23:08)
> Hello Sören,
>
> On Wed, May 21, 2014 at 08:58:10AM -0700, Sören Brinkmann wrote:
> > On Wed, 2014-05-21 at 09:34AM +0200, Uwe Kleine-König wrote:
> > > On Tue, May 20, 2014 at 02:48:20PM -0700, Sören Brinkmann wrote:
> > > > On Tue, 2014-05-20 at
Quoting Uwe Kleine-König (2014-05-21 11:23:08)
Hello Sören,
On Wed, May 21, 2014 at 08:58:10AM -0700, Sören Brinkmann wrote:
On Wed, 2014-05-21 at 09:34AM +0200, Uwe Kleine-König wrote:
On Tue, May 20, 2014 at 02:48:20PM -0700, Sören Brinkmann wrote:
On Tue, 2014-05-20 at 10:48AM
Quoting Peter Ujfalusi (2014-05-07 03:20:47)
> Audio Tracking Logic is designed to be used by HD Radio applications to
> synchronize the audio output clocks to the baseband clock. ATL can be also
> used to track errors between two reference clocks (BWS, AWS) and generate a
> modulated
> clock
Quoting Peter Ujfalusi (2014-05-07 03:20:47)
Audio Tracking Logic is designed to be used by HD Radio applications to
synchronize the audio output clocks to the baseband clock. ATL can be also
used to track errors between two reference clocks (BWS, AWS) and generate a
modulated
clock output
-mstp: change to using clock-indices
Dinh Nguyen (1):
clk: socfpga: fix clock driver for 3.15
Maxime COQUELIN (1):
clk: divider: Fix best div calculation for power-of-two and table dividers
Mike Turquette (1):
Merge tag 'socfpga-clk-fix-for-3.15' of
git://git.rocketboards.org
-mstp: change to using clock-indices
Dinh Nguyen (1):
clk: socfpga: fix clock driver for 3.15
Maxime COQUELIN (1):
clk: divider: Fix best div calculation for power-of-two and table dividers
Mike Turquette (1):
Merge tag 'socfpga-clk-fix-for-3.15' of
git://git.rocketboards.org
Quoting Tomasz Figa (2014-05-15 10:32:30)
> This patch introduces a driver that handles configuration of CLKOUT pin
> of Exynos SoCs that can be used to output certain clocks from inside of
> the SoC to a dedicated output pin.
>
> Signed-off-by: Tomasz Figa
Overall implementation looks good to
Quoting Stephen Warren (2014-05-15 13:20:21)
> On 05/15/2014 04:52 AM, Peter De Schrijver wrote:
> > On Wed, May 14, 2014 at 04:27:40PM +0200, Thierry Reding wrote:
> >> * PGP Signed by an unknown key
> >>
> >> On Tue, May 13, 2014 at 12:09:49PM -0600, Stephen Warren wrote:
> >>> On 05/13/2014
separate matter from the management of said
> clocks in any given driver.
>
> If you want a helpful abstraction for combining clocks for management
> purposes you'd be better off talking to Mike Turquette (CC'd), as he's
> in charge of the common clock framework.
Jim emailed me privately.
be better off talking to Mike Turquette (CC'd), as he's
in charge of the common clock framework.
Jim emailed me privately. Here is my response for posterity:
On Wed, May 7, 2014 at 8:59 AM, Jim Quinlan jquin...@broadcom.com wrote:
Hi Mike,
Hi Jim,
snip
In most examples of .dtsi files I have
Quoting Stephen Warren (2014-05-15 13:20:21)
On 05/15/2014 04:52 AM, Peter De Schrijver wrote:
On Wed, May 14, 2014 at 04:27:40PM +0200, Thierry Reding wrote:
* PGP Signed by an unknown key
On Tue, May 13, 2014 at 12:09:49PM -0600, Stephen Warren wrote:
On 05/13/2014 08:06 AM, Peter De
Quoting Tomasz Figa (2014-05-15 10:32:30)
This patch introduces a driver that handles configuration of CLKOUT pin
of Exynos SoCs that can be used to output certain clocks from inside of
the SoC to a dedicated output pin.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Overall implementation
Quoting Heikki Krogerus (2014-05-15 06:40:25)
> Fractional divider clocks are fairly common. This adds basic
> type for them.
>
> Signed-off-by: Heikki Krogerus
Taken into clk-next.
Just FYI, there was some talk at Embedded Linux Conference on providing
a better abstraction layer for some of
Quoting Fabio Estevam (2014-05-08 20:01:50)
> From: Fabio Estevam
>
> Remove the 'gpios' property from the documentation as this is something that
> the
> current fixed clock driver does not handle.
>
> Signed-off-by: Fabio Estevam
Good catch. Taken into clk-next.
Regards,
Mike
> ---
>
Quoting Arnd Bergmann (2014-05-08 07:56:16)
> The impd1 code on mach-integrator can be a loadable module,
> so we have to export icst_clk_register, integrator_impd1_clk_init
> and integrator_impd1_clk_exit.
>
> Signed-off-by: Arnd Bergmann
> Cc: Mike Turquette
> Cc:
Quoting Stephen Rothwell (2014-05-14 23:11:21)
> Hi Mike,
>
> Today's linux-next merge of the clk tree got a conflict in
> Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
> between commit b557deadc5cc ("ARM: shmobile: r7s72100: document MSTP
> clock support") from the renesas
Quoting Stephen Rothwell (2014-05-14 23:11:21)
Hi Mike,
Today's linux-next merge of the clk tree got a conflict in
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
between commit b557deadc5cc (ARM: shmobile: r7s72100: document MSTP
clock support) from the renesas tree and
Quoting Arnd Bergmann (2014-05-08 07:56:16)
The impd1 code on mach-integrator can be a loadable module,
so we have to export icst_clk_register, integrator_impd1_clk_init
and integrator_impd1_clk_exit.
Signed-off-by: Arnd Bergmann a...@arndb.de
Cc: Mike Turquette mturque...@linaro.org
Cc
Quoting Fabio Estevam (2014-05-08 20:01:50)
From: Fabio Estevam fabio.este...@freescale.com
Remove the 'gpios' property from the documentation as this is something that
the
current fixed clock driver does not handle.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
Good catch.
Quoting Heikki Krogerus (2014-05-15 06:40:25)
Fractional divider clocks are fairly common. This adds basic
type for them.
Signed-off-by: Heikki Krogerus heikki.kroge...@linux.intel.com
Taken into clk-next.
Just FYI, there was some talk at Embedded Linux Conference on providing
a better
Quoting Boris BREZILLON (2014-05-14 00:30:59)
> Hello Mike,
>
> On 14/05/2014 02:51, Mike Turquette wrote:
> > Quoting Boris BREZILLON (2014-05-09 04:11:49)
> >> +struct clk_ops ar100_ops = {
> >> + .recalc_rate = ar100_recalc_rate,
> >> +
Quoting Sebastian Hesselbarth (2014-05-11 13:24:35)
> This adds mandatory device tree binding documentation for the clock related
> IP found on Marvell Berlin2 (BG2, BG2CD, and BG2Q) SoCs.
>
> Signed-off-by: Sebastian Hesselbarth
> ---
> Cc: Mike Turquette
> Cc: Rob Herr
Quoting Anders Berg (2014-05-14 11:37:57)
> +Example:
> +
> + clk_ref0: clk_ref0 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <12500>;
> + };
Hi Anders,
The driver looks good. As for the DT binding, I am
Quoting Thierry Reding (2014-05-14 07:27:40)
> On Tue, May 13, 2014 at 12:09:49PM -0600, Stephen Warren wrote:
> > On 05/13/2014 08:06 AM, Peter De Schrijver wrote:
> > > Add shared and cbus clocks to the Tegra124 clock implementation.
> >
> > > diff --git
Quoting Thierry Reding (2014-05-14 07:27:40)
On Tue, May 13, 2014 at 12:09:49PM -0600, Stephen Warren wrote:
On 05/13/2014 08:06 AM, Peter De Schrijver wrote:
Add shared and cbus clocks to the Tegra124 clock implementation.
diff --git a/include/dt-bindings/clock/tegra124-car.h
Quoting Anders Berg (2014-05-14 11:37:57)
+Example:
+
+ clk_ref0: clk_ref0 {
+ compatible = fixed-clock;
+ #clock-cells = 0;
+ clock-frequency = 12500;
+ };
Hi Anders,
The driver looks good. As for the DT binding, I am starting to
Quoting Sebastian Hesselbarth (2014-05-11 13:24:35)
This adds mandatory device tree binding documentation for the clock related
IP found on Marvell Berlin2 (BG2, BG2CD, and BG2Q) SoCs.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Mike Turquette mturque
Quoting Boris BREZILLON (2014-05-14 00:30:59)
Hello Mike,
On 14/05/2014 02:51, Mike Turquette wrote:
Quoting Boris BREZILLON (2014-05-09 04:11:49)
+struct clk_ops ar100_ops = {
+ .recalc_rate = ar100_recalc_rate,
+ .determine_rate = ar100_determine_rate
Quoting Boris BREZILLON (2014-05-09 04:11:49)
> +struct clk_ops ar100_ops = {
> + .recalc_rate = ar100_recalc_rate,
> + .determine_rate = ar100_determine_rate,
> + .set_parent = ar100_set_parent,
> + .get_parent = ar100_get_parent,
> + .set_rate = ar100_set_rate,
>
Quoting Sebastian Hesselbarth (2014-05-13 08:11:55)
> On 05/13/2014 02:20 PM, Mark Rutland wrote:
> > On Tue, May 13, 2014 at 12:57:32PM +0100, Gabriel FERNANDEZ wrote:
> >> The patch provides a helper to get flags properties of
> >> a clock node.
> >>
> >> Signed-off-by: Gabriel Fernandez
> >>
reg property or a magic number instead. This is basically the same
> we already do for proper devices and may vanish as soon as there is some
> (early) device support for clocks available.
>
> Signed-off-by: Sebastian Hesselbarth
> ---
> Cc: Mike Turquette
> Cc: Grant Likely
&
or a magic number instead. This is basically the same
we already do for proper devices and may vanish as soon as there is some
(early) device support for clocks available.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Mike Turquette mturque...@linaro.org
Cc: Grant
Quoting Sebastian Hesselbarth (2014-05-13 08:11:55)
On 05/13/2014 02:20 PM, Mark Rutland wrote:
On Tue, May 13, 2014 at 12:57:32PM +0100, Gabriel FERNANDEZ wrote:
The patch provides a helper to get flags properties of
a clock node.
Signed-off-by: Gabriel Fernandez
Quoting Boris BREZILLON (2014-05-09 04:11:49)
+struct clk_ops ar100_ops = {
+ .recalc_rate = ar100_recalc_rate,
+ .determine_rate = ar100_determine_rate,
+ .set_parent = ar100_set_parent,
+ .get_parent = ar100_get_parent,
+ .set_rate = ar100_set_rate,
+};
I
Hans de Goede
Acked-by: Mike Turquette
> ---
> drivers/clk/sunxi/clk-sunxi.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> index bd7dc733c1ca..d9bab75f128b 100644
> --- a/drivers/clk/sunxi
Quoting Arnd Bergmann (2014-04-23 06:31:06)
> On Wednesday 23 April 2014 15:17:20 Maxime Ripard wrote:
> > > > +#include
> > > > #include
> > > > #include
> > > >
> > > > @@ -19,9 +20,17 @@
> > > >
> > > > static void __init sun4i_dt_init(void)
> > > > {
> > > > + struct clk *clk;
501 - 600 of 1380 matches
Mail list logo
