Quoting Tomasz Figa (2013-07-23 01:09:06)
> On Monday 22 of July 2013 10:21:38 Mark Rutland wrote:
> > On Fri, Jul 19, 2013 at 09:17:17AM +0100, Jonas Jensen wrote:
> > > This patch adds MOXA ART SoCs clock driver support.
> > >
> > > Signed-off-by: Jonas Jensen
> > > ---
> > >
> > > Notes:
> >
Quoting Cho KyongHo (2013-07-26 04:27:54)
> This adds gate clocks of all System MMUs and their master IPs
> that are not apeared in clk-exynos5250.c
>
> Signed-off-by: Cho KyongHo
Change looks good to me. Are you OK if I take it into the clk tree or do
you want to keep this series together?
Quoting Cho KyongHo (2013-07-26 04:27:54)
This adds gate clocks of all System MMUs and their master IPs
that are not apeared in clk-exynos5250.c
Signed-off-by: Cho KyongHo pullip@samsung.com
Change looks good to me. Are you OK if I take it into the clk tree or do
you want to keep this
Quoting Tomasz Figa (2013-07-23 01:09:06)
On Monday 22 of July 2013 10:21:38 Mark Rutland wrote:
On Fri, Jul 19, 2013 at 09:17:17AM +0100, Jonas Jensen wrote:
This patch adds MOXA ART SoCs clock driver support.
Signed-off-by: Jonas Jensen jonas.jen...@gmail.com
---
Notes:
reparented in
> >> response to set_rate please let me know and I'll drop the relevant
> >> portion of the patch.
> >
> > Why is this better to change current behaviour of the clock core
> > and modify all drivers instead of having, e.g. CLK_SET_RATE_RE
of the clock core
and modify all drivers instead of having, e.g. CLK_SET_RATE_REPARENT
set in drivers of hardware that supports clock re-parenting while
setting clock rate ?
See this message from Mike Turquette which first suggested it:
http://marc.info/?l=linux-kernelm=136847508109344w=2
was proposed in
February[1].
[1] http://patches.linaro.org/15128/
Signed-off-by: Mike Turquette
---
drivers/clk/Makefile | 1 +
drivers/clk/clk-voltage-notifier.c | 135 +
include/linux/clk.h| 7 +-
3 files changed, 142 insertions
otifiers this series hopes to consolidate code across drivers
and encourage vendors to upstream their DVFS bits.
Mike Turquette (3):
clk: notifier handler for dynamic voltage scaling
clk: cpufreq helper for voltage scaling
cpufreq: cpufreq-cpu0: clk rate-change notifiers
drivers/clk/
Removes direct handling of OPP tables and voltage regulators by calling
of_clk_cpufreq_notifier_handler, introduced by commit "clk: cpufreq
helper for voltage scaling".
In the future this can help consolidate code found across similar
CPUfreq drivers.
Signed-off-by: Mike Turquette
--
ency_table and also calculate the voltage scaling latency,
both of which are returned to the caller for use in the CPUfreq driver.
Signed-off-by: Mike Turquette
---
drivers/clk/clk-voltage-notifier.c | 71 ++
include/linux/clk.h| 6
2 fil
and also calculate the voltage scaling latency,
both of which are returned to the caller for use in the CPUfreq driver.
Signed-off-by: Mike Turquette mturque...@linaro.org
---
drivers/clk/clk-voltage-notifier.c | 71 ++
include/linux/clk.h| 6
Removes direct handling of OPP tables and voltage regulators by calling
of_clk_cpufreq_notifier_handler, introduced by commit clk: cpufreq
helper for voltage scaling.
In the future this can help consolidate code found across similar
CPUfreq drivers.
Signed-off-by: Mike Turquette mturque
this series hopes to consolidate code across drivers
and encourage vendors to upstream their DVFS bits.
Mike Turquette (3):
clk: notifier handler for dynamic voltage scaling
clk: cpufreq helper for voltage scaling
cpufreq: cpufreq-cpu0: clk rate-change notifiers
drivers/clk/Makefile
was proposed in
February[1].
[1] http://patches.linaro.org/15128/
Signed-off-by: Mike Turquette mturque...@linaro.org
---
drivers/clk/Makefile | 1 +
drivers/clk/clk-voltage-notifier.c | 135 +
include/linux/clk.h| 7 +-
3 files changed
The following changes since commit e4aa937ec75df0eea0bee03bffa3303ad36c986b:
Linux 3.10-rc3 (2013-05-26 16:00:47 -0700)
are available in the git repository at:
git://git.linaro.org/people/mturquette/linux.git tags/clk-for-linus-3.11
for you to fetch changes up to
The following changes since commit e4aa937ec75df0eea0bee03bffa3303ad36c986b:
Linux 3.10-rc3 (2013-05-26 16:00:47 -0700)
are available in the git repository at:
git://git.linaro.org/people/mturquette/linux.git tags/clk-for-linus-3.11
for you to fetch changes up to
Quoting Haojian Zhuang (2013-06-25 01:27:58)
> On 21 June 2013 14:14, Mike Turquette wrote:
> > Device Tree binding for the basic clock multiplexer, plus the setup
> > function to register the clock. Based on the existing fixed-clock
> > binding.
> >
> > Inc
Quoting Haojian Zhuang (2013-06-25 01:27:58)
On 21 June 2013 14:14, Mike Turquette mturque...@linaro.org wrote:
Device Tree binding for the basic clock multiplexer, plus the setup
function to register the clock. Based on the existing fixed-clock
binding.
Includes minor beautification
Quoting Tushar Behera (2013-06-20 03:47:16)
> cpufreq driver for EXYNOS4 based SoCs are not platform drivers, hence
> we cannot currently pass the clock names through a device tree node.
> Instead, we need to make them available through global alias.
>
> The patches are based on next-20130618.
>
Quoting James Hogan (2013-06-13 09:05:57)
> This patchset adds support for automatic selection of the best parent
> for a clock mux, i.e. the one which can provide the closest clock rate
> to that requested. It can be disabled by a new CLK_SET_RATE_NO_REPARENT
> flag (which is set for all uses of
r tree.
Hi Prashant. I merged this one a long time ago:
Refs: v3.10-rc3-22-g061cec9
Author: Prashant Gaikwad
AuthorDate: Mon May 27 13:10:09 2013 +0530
Commit: Mike Turquette
CommitDate: Fri May 31 12:57:25 2013 -0700
Regards,
Mike
>
> Thanks,
>
Devicetree binding for the basic clock divider, plus the setup function
to register the clock. Based on the existing fixed-clock binding.
Tero Kristo contributed helpful bug fixes to this patch.
Signed-off-by: Mike Turquette
---
Changes since v2:
* added hiword-mask property to the binding
style.
Tero Kristo contributed helpful bug fixes to this patch.
Signed-off-by: Mike Turquette
---
Changes since v2:
* added hiword-mask property to the binding
* changed bit-shift property from u8 to u32 in the dt binding
Changes since v1:
* pass shift value into clk_register_mux_table
* s
Walks the "clocks" array of parent clock phandles and returns the
number.
Signed-off-by: Mike Turquette
---
No change since v2
drivers/clk/clk.c| 6 ++
include/linux/clk-provider.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/clk/clk.c b/drivers/clk/c
definitions closely model the hardware register
layout.
This version fixes bugs and incorporates support for the hiword-mask
property needed on Hisilicon and Rockchip platforms.
Tested on OMAP4460 Panda ES.
Mike Turquette (5):
clk: divider: replace bitfield width with mask
clk: of: helper
://article.gmane.org/gmane.linux.documentation/5679
[2]
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-December/137878.html
Tero Kristo contributed helpful bug fixes to this patch.
Signed-off-by: Mike Turquette
---
Changes since v2:
* added hiword-mask property to the binding
* changed bit
Guo
Signed-off-by: Mike Turquette
---
No change since v2
arch/arm/mach-imx/clk-busy.c | 2 +-
drivers/clk/clk-divider.c| 31 +++
drivers/clk/mxs/clk-div.c| 2 +-
include/linux/clk-private.h | 2 +-
include/linux/clk-provider.h | 2 +-
5 files changed, 19
...@pengutronix.de
Tested-by: Shawn Guo shawn@linaro.org
Signed-off-by: Mike Turquette mturque...@linaro.org
---
No change since v2
arch/arm/mach-imx/clk-busy.c | 2 +-
drivers/clk/clk-divider.c| 31 +++
drivers/clk/mxs/clk-div.c| 2 +-
include/linux/clk-private.h | 2
definitions closely model the hardware register
layout.
This version fixes bugs and incorporates support for the hiword-mask
property needed on Hisilicon and Rockchip platforms.
Tested on OMAP4460 Panda ES.
Mike Turquette (5):
clk: divider: replace bitfield width with mask
clk: of: helper
://article.gmane.org/gmane.linux.documentation/5679
[2]
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-December/137878.html
Tero Kristo contributed helpful bug fixes to this patch.
Signed-off-by: Mike Turquette mturque...@linaro.org
---
Changes since v2:
* added hiword-mask property
style.
Tero Kristo contributed helpful bug fixes to this patch.
Signed-off-by: Mike Turquette mturque...@linaro.org
---
Changes since v2:
* added hiword-mask property to the binding
* changed bit-shift property from u8 to u32 in the dt binding
Changes since v1:
* pass shift value
Walks the clocks array of parent clock phandles and returns the
number.
Signed-off-by: Mike Turquette mturque...@linaro.org
---
No change since v2
drivers/clk/clk.c| 6 ++
include/linux/clk-provider.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/clk/clk.c b
Devicetree binding for the basic clock divider, plus the setup function
to register the clock. Based on the existing fixed-clock binding.
Tero Kristo contributed helpful bug fixes to this patch.
Signed-off-by: Mike Turquette mturque...@linaro.org
---
Changes since v2:
* added hiword-mask
a long time ago:
Refs: v3.10-rc3-22-g061cec9
Author: Prashant Gaikwad pgaik...@nvidia.com
AuthorDate: Mon May 27 13:10:09 2013 +0530
Commit: Mike Turquette mturque...@linaro.org
CommitDate: Fri May 31 12:57:25 2013 -0700
Regards,
Mike
Thanks,
PrashantG
Acked-by: Stephen Warren swar
Quoting James Hogan (2013-06-13 09:05:57)
This patchset adds support for automatic selection of the best parent
for a clock mux, i.e. the one which can provide the closest clock rate
to that requested. It can be disabled by a new CLK_SET_RATE_NO_REPARENT
flag (which is set for all uses of
Quoting Tushar Behera (2013-06-20 03:47:16)
cpufreq driver for EXYNOS4 based SoCs are not platform drivers, hence
we cannot currently pass the clock names through a device tree node.
Instead, we need to make them available through global alias.
The patches are based on next-20130618.
Quoting Boris BREZILLON (2013-06-07 08:11:03)
> +static struct clk_lookup pioA_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "pioA_clk", NULL),
> + CLKDEV_INIT(NULL, "pioA", NULL),
> +};
It would be great to get rid of this clkdev data from the kernel as
well. Have you looked into encoding
Quoting Boris BREZILLON (2013-06-07 08:11:03)
+static struct clk_lookup pioA_clk_lookup[] = {
+ CLKDEV_INIT(NULL, pioA_clk, NULL),
+ CLKDEV_INIT(NULL, pioA, NULL),
+};
It would be great to get rid of this clkdev data from the kernel as
well. Have you looked into encoding the
Quoting Arnd Bergmann (2013-06-12 07:46:30)
> On Tuesday 11 June 2013, Lee Jones wrote:
> > This patch enables clocks to be specified from Device Tree via phandles
> > to the "prcc-kernel-clock" node.
> >
> > Cc: Mike Turquette
> > Cc: Ulf Hansson
>
Quoting Paul Walmsley (2013-06-17 13:22:48)
> Hi,
>
> On Sat, 15 Jun 2013, Mike Turquette wrote:
>
> > These patches appear fine to me but I did not see any Acks, nor could I
> > tell if a v2 was necessary based on the comments. Will there be another
> > versio
Quoting Paul Walmsley (2013-06-17 13:22:48)
Hi,
On Sat, 15 Jun 2013, Mike Turquette wrote:
These patches appear fine to me but I did not see any Acks, nor could I
tell if a v2 was necessary based on the comments. Will there be another
version?
I'm not planning to do another version
Quoting Arnd Bergmann (2013-06-12 07:46:30)
On Tuesday 11 June 2013, Lee Jones wrote:
This patch enables clocks to be specified from Device Tree via phandles
to the prcc-kernel-clock node.
Cc: Mike Turquette mturque...@linaro.org
Cc: Ulf Hansson ulf.hans...@linaro.org
Signed-off
posted recently.
Heiko, enough changed here such that I did not keep your Acked-by's and
Tested-by's. But I am happy to take them again :-)
Mike Turquette (5):
clk: divider: replace bitfield width with mask
clk: of: helper for determining number of parent clocks
clk: dt: binding for basic
://article.gmane.org/gmane.linux.documentation/5679
[2]
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-December/137878.html
Signed-off-by: Mike Turquette
---
No change since v1, new patch
.../devicetree/bindings/clock/gate-clock.txt | 34 ++
drivers/clk/clk-gate.c
Walks the "clocks" array of parent clock phandles and returns the
number.
Signed-off-by: Mike Turquette
---
No change since v1
drivers/clk/clk.c| 6 ++
include/linux/clk-provider.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/clk/clk.c b/drivers/clk/c
Signed-off-by: Mike Turquette
---
No change since v1, new patch
arch/arm/mach-imx/clk-busy.c | 2 +-
drivers/clk/clk-divider.c| 31 +++
drivers/clk/mxs/clk-div.c| 2 +-
include/linux/clk-private.h | 2 +-
include/linux/clk-provider.h | 2 +-
5 files changed
style.
Signed-off-by: Mike Turquette
---
Changes since v1:
* pass shift value into clk_register_mux_table
* s/multiplexor/multiplexer/
* removed debug prints
* mask is u32, shift is u8
* DT property names use dashes instead of underscores
* DT property names are more verbose
* shift property
Devicetree binding for the basic clock divider, plus the setup function
to register the clock. Based on the existing fixed-clock binding.
Signed-off-by: Mike Turquette
---
Changes since v1:
* mask is u32, shift is u8
* use bit mask instead of bitfield width
* DT property names use dashes
The following changes since commit d683b96b072dc4680fc74964eca77e6a23d1fa6e:
Linux 3.10-rc4 (2013-06-02 17:11:17 +0900)
are available in the git repository at:
git://git.linaro.org/people/mturquette/linux.git tags/clk-fixes-for-linus
for you to fetch changes up to
Quoting Stephen Warren (2013-06-12 08:36:11)
> On 06/12/2013 01:13 AM, Jay Agarwal wrote:
> > Registering pciex as peripheral clock instead of fixed clock
> > as tegra_perih_reset_assert(deassert) api of this clock api
> > gives warning and ultimately does not succeed to assert(deassert)
> >
> >
Quoting Stephen Warren (2013-06-12 08:36:11)
On 06/12/2013 01:13 AM, Jay Agarwal wrote:
Registering pciex as peripheral clock instead of fixed clock
as tegra_perih_reset_assert(deassert) api of this clock api
gives warning and ultimately does not succeed to assert(deassert)
The following changes since commit d683b96b072dc4680fc74964eca77e6a23d1fa6e:
Linux 3.10-rc4 (2013-06-02 17:11:17 +0900)
are available in the git repository at:
git://git.linaro.org/people/mturquette/linux.git tags/clk-fixes-for-linus
for you to fetch changes up to
Devicetree binding for the basic clock divider, plus the setup function
to register the clock. Based on the existing fixed-clock binding.
Signed-off-by: Mike Turquette mturque...@linaro.org
---
Changes since v1:
* mask is u32, shift is u8
* use bit mask instead of bitfield width
* DT property
...@pengutronix.de
Cc: Shawn Guo shawn@linaro.org
Signed-off-by: Mike Turquette mturque...@linaro.org
---
No change since v1, new patch
arch/arm/mach-imx/clk-busy.c | 2 +-
drivers/clk/clk-divider.c| 31 +++
drivers/clk/mxs/clk-div.c| 2 +-
include/linux/clk-private.h
style.
Signed-off-by: Mike Turquette mturque...@linaro.org
---
Changes since v1:
* pass shift value into clk_register_mux_table
* s/multiplexor/multiplexer/
* removed debug prints
* mask is u32, shift is u8
* DT property names use dashes instead of underscores
* DT property names are more verbose
://article.gmane.org/gmane.linux.documentation/5679
[2]
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-December/137878.html
Signed-off-by: Mike Turquette mturque...@linaro.org
---
No change since v1, new patch
.../devicetree/bindings/clock/gate-clock.txt | 34 ++
drivers
Walks the clocks array of parent clock phandles and returns the
number.
Signed-off-by: Mike Turquette mturque...@linaro.org
---
No change since v1
drivers/clk/clk.c| 6 ++
include/linux/clk-provider.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/clk/clk.c b
posted recently.
Heiko, enough changed here such that I did not keep your Acked-by's and
Tested-by's. But I am happy to take them again :-)
Mike Turquette (5):
clk: divider: replace bitfield width with mask
clk: of: helper for determining number of parent clocks
clk: dt: binding for basic
Quoting Paul Walmsley (2013-06-11 02:47:13)
> On Tue, 11 Jun 2013, Prashant Gaikwad wrote:
>
> > Why not implement these APIs in DFLL clock driver itself and pass RST
> > address
> > register to driver?
>
> The DFLL DVCO reset registers are CAR registers, not DFLL registers.
> Functions that
Quoting Paul Walmsley (2013-06-11 02:47:13)
On Tue, 11 Jun 2013, Prashant Gaikwad wrote:
Why not implement these APIs in DFLL clock driver itself and pass RST
address
register to driver?
The DFLL DVCO reset registers are CAR registers, not DFLL registers.
Functions that operate on
Quoting Heiko Stübner (2013-06-03 15:18:32)
> Am Montag, 3. Juni 2013, 19:53:10 schrieb Mike Turquette:
> > Devicetree binding for the basic clock divider, plus the setup function
> > to register the clock. Based on the existing fixed-clock binding.
> >
> > Si
On Wed, Jun 12, 2013 at 10:55 AM, Doug Anderson wrote:
> Mike,
>
> On Wed, Jun 12, 2013 at 10:45 AM, Mike Turquette
> wrote:
>
>>> * It seems like we can't make muxing decisions on the SoC level.
>>> * Your automatic muxing patches don't hurt me and could be us
Quoting Doug Anderson (2013-06-11 18:01:01)
> Hi,
>
> Mike pointed me at this series since I'm running into parenting
> problems at the moment as well...
>
> On Mon, May 20, 2013 at 9:44 PM, Saravana Kannan
> wrote:
> > While writing a similar code for our internal tree, I quickly came to the
Quoting Doug Anderson (2013-06-11 18:01:01)
Hi,
Mike pointed me at this series since I'm running into parenting
problems at the moment as well...
On Mon, May 20, 2013 at 9:44 PM, Saravana Kannan skan...@codeaurora.org
wrote:
While writing a similar code for our internal tree, I quickly
On Wed, Jun 12, 2013 at 10:55 AM, Doug Anderson diand...@chromium.org wrote:
Mike,
On Wed, Jun 12, 2013 at 10:45 AM, Mike Turquette mturque...@linaro.org
wrote:
* It seems like we can't make muxing decisions on the SoC level.
* Your automatic muxing patches don't hurt me and could
Quoting Heiko Stübner (2013-06-03 15:18:32)
Am Montag, 3. Juni 2013, 19:53:10 schrieb Mike Turquette:
Devicetree binding for the basic clock divider, plus the setup function
to register the clock. Based on the existing fixed-clock binding.
Signed-off-by: Mike Turquette mturque
Quoting Tushar Behera (2013-06-06 01:28:18)
> Currently 'pmu' clock is not handled by any of the drivers.
> Also before the introduction of CCF, this clock was not defined,
> hence was left enabled always.
>
> When this clock is disabled, software reset register becomes
> inaccessible and system
Quoting Peter De Schrijver (2013-06-05 08:06:34)
> Using clk->rate directly does not take the CLK_GET_RATE_NOCACHE flag into
> account. This can cause wrong results if the flag is set.
>
> Peter De Schrijver (2):
> clk: use clk_get_rate() for debugfs
> clk: honor CLK_GET_RATE_NOCACHE in
Quoting Peter De Schrijver (2013-06-06 03:47:27)
> PLLM has override bits on Tegra30 and Tegra114. This patchset implements
> support for them for both Tegra30 and Tegra114.
>
> Changes since v1:
> * Remove some stray lines from 'clk: tegra: override bits for Tegra114 PLLM'
Pulled into
Quoting Peter De Schrijver (2013-06-05 07:29:28)
> Use the correct parents for sclk according to the TRM.
>
> Signed-off-by: Peter De Schrijver
Taken into clk-next.
Regards,
Mike
> ---
> drivers/clk/tegra/clk-tegra114.c |2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff
Quoting Peter De Schrijver (2013-06-05 07:21:46)
> The PLLRE flags weren't set correctly. Fixed in this patch.
>
> Signed-off-by: Peter De Schrijver
Taken into clk-next.
Thanks,
Mike
> ---
> drivers/clk/tegra/clk-pll.c |3 +--
> 1 files changed, 1 insertions(+), 2 deletions(-)
>
> diff
Quoting Peter De Schrijver (2013-06-05 06:51:24)
> The m,n,p fields don't have the same bit offset and width across all PLLs.
> This patchset allows SoC specific files to indicate the offset and width.
> It also provides the data for Tegra114.
>
Taken into clk-next.
Thanks,
Mike
> Peter De
Quoting Peter De Schrijver (2013-06-05 06:37:17)
> The pllp_out2 should be integer only, the fractional bit should always be 0.
>
> Signed-off-by: Peter De Schrijver
Taken into clk-next.
Thanks,
Mike
> ---
> drivers/clk/tegra/clk-tegra114.c |4 ++--
> 1 files changed, 2 insertions(+), 2
Quoting Peter De Schrijver (2013-06-05 05:56:41)
> The pllc and pllxc code weren't always using the correct pdiv_map to
> map between the post divider value and the hw p field. This could result
> in illegal values being programmed in the hw.
>
> Signed-off-by: Peter De Schrijver
Taken into
able.
>
> Cc: Saravana Kannan
> Cc: Mike Turquette
> Signed-off-by: Stephen Boyd
I just went through this quickly and nothing popped out at me. Nice
diffstat btw! Do you have any plans to move this to drivers/clk/msm ?
Acked-by: Mike Turquette
> ---
> arch/arm/Kconfig
Quoting Stephen Warren (2013-06-04 12:08:08)
> On 06/04/2013 12:57 PM, Jay Agarwal wrote:
> > Registering pciex as peripheral clock instead of fixed clock
> > as tegra_perih_reset_assert(deassert) api of this clock api
> > gives warning and ultimately does not succeed to assert(deassert).
> >
> >
Quoting Arnd Bergmann (2013-06-04 13:52:03)
> On Tuesday 04 June 2013, Linus Walleij wrote:
> > The whole thing is very different from other DT clock things
> > I've seen, usually you add a compatible node for each
> > clock type, and a node for each physical gate. But there
> > may be several
Quoting Heiko Stübner (2013-06-11 04:31:31)
> This adds basic support for clocks on Rockchip rk3066 SoCs.
> The clock handling thru small dt nodes is heavily inspired by the
> sunxi clk code.
>
> The plls are currently read-only, as their setting needs more
> investigation. This also results in
Quoting Heiko Stübner (2013-06-11 04:29:32)
> SoCs like the Rockchip Cortex-A9 ones contain divider some clocks
> that use the regular mechanisms for storage but allow only even
> dividers and 1 to be used.
>
> Therefore add a flag that lets _is_valid_div limit the valid dividers
> to these
Quoting Heiko Stübner (2013-06-11 04:29:32)
SoCs like the Rockchip Cortex-A9 ones contain divider some clocks
that use the regular mechanisms for storage but allow only even
dividers and 1 to be used.
Therefore add a flag that lets _is_valid_div limit the valid dividers
to these values.
Quoting Heiko Stübner (2013-06-11 04:31:31)
This adds basic support for clocks on Rockchip rk3066 SoCs.
The clock handling thru small dt nodes is heavily inspired by the
sunxi clk code.
The plls are currently read-only, as their setting needs more
investigation. This also results in slow
Quoting Arnd Bergmann (2013-06-04 13:52:03)
On Tuesday 04 June 2013, Linus Walleij wrote:
The whole thing is very different from other DT clock things
I've seen, usually you add a compatible node for each
clock type, and a node for each physical gate. But there
may be several ways to skin
Quoting Stephen Warren (2013-06-04 12:08:08)
On 06/04/2013 12:57 PM, Jay Agarwal wrote:
Registering pciex as peripheral clock instead of fixed clock
as tegra_perih_reset_assert(deassert) api of this clock api
gives warning and ultimately does not succeed to assert(deassert).
...@codeaurora.org
Cc: Mike Turquette mturque...@linaro.org
Signed-off-by: Stephen Boyd sb...@codeaurora.org
I just went through this quickly and nothing popped out at me. Nice
diffstat btw! Do you have any plans to move this to drivers/clk/msm ?
Acked-by: Mike Turquette mturque...@linaro.org
Quoting Peter De Schrijver (2013-06-05 05:56:41)
The pllc and pllxc code weren't always using the correct pdiv_map to
map between the post divider value and the hw p field. This could result
in illegal values being programmed in the hw.
Signed-off-by: Peter De Schrijver
Quoting Peter De Schrijver (2013-06-05 06:37:17)
The pllp_out2 should be integer only, the fractional bit should always be 0.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
Taken into clk-next.
Thanks,
Mike
---
drivers/clk/tegra/clk-tegra114.c |4 ++--
1 files changed, 2
Quoting Peter De Schrijver (2013-06-05 06:51:24)
The m,n,p fields don't have the same bit offset and width across all PLLs.
This patchset allows SoC specific files to indicate the offset and width.
It also provides the data for Tegra114.
Taken into clk-next.
Thanks,
Mike
Peter De
Quoting Peter De Schrijver (2013-06-05 07:21:46)
The PLLRE flags weren't set correctly. Fixed in this patch.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
Taken into clk-next.
Thanks,
Mike
---
drivers/clk/tegra/clk-pll.c |3 +--
1 files changed, 1 insertions(+), 2
Quoting Peter De Schrijver (2013-06-05 07:29:28)
Use the correct parents for sclk according to the TRM.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
Taken into clk-next.
Regards,
Mike
---
drivers/clk/tegra/clk-tegra114.c |2 +-
1 files changed, 1 insertions(+), 1
Quoting Peter De Schrijver (2013-06-06 03:47:27)
PLLM has override bits on Tegra30 and Tegra114. This patchset implements
support for them for both Tegra30 and Tegra114.
Changes since v1:
* Remove some stray lines from 'clk: tegra: override bits for Tegra114 PLLM'
Pulled into clk-next.
Quoting Peter De Schrijver (2013-06-05 08:06:34)
Using clk-rate directly does not take the CLK_GET_RATE_NOCACHE flag into
account. This can cause wrong results if the flag is set.
Peter De Schrijver (2):
clk: use clk_get_rate() for debugfs
clk: honor CLK_GET_RATE_NOCACHE in clk_set_rate
Quoting Tushar Behera (2013-06-06 01:28:18)
Currently 'pmu' clock is not handled by any of the drivers.
Also before the introduction of CCF, this clock was not defined,
hence was left enabled always.
When this clock is disabled, software reset register becomes
inaccessible and system reboot
Quoting Kukjin Kim (2013-06-05 04:51:29)
> Doug Anderson wrote:
> >
> > The KDIV value is often listed as unsigned but it needs to be treated
> > as a 16-bit signed value when using it in calculations. Fix our rate
> > recalculation to do this correctly.
> >
> > Before doing this, I tried
Quoting Kukjin Kim (2013-06-05 04:51:29)
Doug Anderson wrote:
The KDIV value is often listed as unsigned but it needs to be treated
as a 16-bit signed value when using it in calculations. Fix our rate
recalculation to do this correctly.
Before doing this, I tried setting EPLL on
Quoting Lai Jiangshan (2013-06-03 02:17:15)
> The @cn is stay in @clk_notifier_list after it is freed, it cause
> memory corruption.
>
> Example, if @clk is registered(first), unregistered(first),
> registered(second), unregistered(second).
>
> The freed @cn will be used when @clk is
Quoting Lai Jiangshan (2013-06-03 02:17:15)
The @cn is stay in @clk_notifier_list after it is freed, it cause
memory corruption.
Example, if @clk is registered(first), unregistered(first),
registered(second), unregistered(second).
The freed @cn will be used when @clk is
Quoting Matt Sealey (2013-06-04 10:39:53)
> On Tue, Jun 4, 2013 at 12:11 PM, Stephen Boyd wrote:
> > On 06/03/13 10:53, Mike Turquette wrote:
> >> +Required properties:
> >> +- compatible : shall be "divider-clock".
> >> +- #clock-cells
On Mon, Jun 3, 2013 at 11:27 PM, Ambresh K wrote:
>
>>
>> clksel is an omap-centric term. How about:
>>
>> "clk_mux_get_parent should return an error if the value read from the
>> register is erroneous."
>>
>
> Make sense, will fix it.
>
>> The general approach looks good to me. Can you submit
On Mon, Jun 3, 2013 at 2:39 PM, Heiko Stübner wrote:
> Am Montag, 3. Juni 2013, 22:15:45 schrieb Heiko Stübner:
>> Am Montag, 3. Juni 2013, 22:07:22 schrieb Mike Turquette:
>> > Quoting Heiko Stübner (2013-06-03 12:33:19)
>> >
>> > > Hi Mike,
>>
On Mon, Jun 3, 2013 at 2:39 PM, Heiko Stübner he...@sntech.de wrote:
Am Montag, 3. Juni 2013, 22:15:45 schrieb Heiko Stübner:
Am Montag, 3. Juni 2013, 22:07:22 schrieb Mike Turquette:
Quoting Heiko Stübner (2013-06-03 12:33:19)
Hi Mike,
I think it's a multiplexEr clock in the patch
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