> -Original Message-
> From: Radim Krčmář <rkrc...@redhat.com>
> Sent: Wednesday, March 14, 2018 8:26 AM
> To: Moger, Babu <babu.mo...@amd.com>
> Cc: j...@8bytes.org; t...@linutronix.de; mi...@redhat.com;
> h...@zytor.com; x...@kernel.org; pbonz...@redh
Radim,
Thanks for the comments. Taken care of most of the comments.
I have few questions/comments. Please see inline.
> -Original Message-
> From: Radim Krčmář <rkrc...@redhat.com>
> Sent: Friday, March 9, 2018 12:13 PM
> To: Moger, Babu <babu.mo...@amd.com>
> -Original Message-
> From: Radim Krčmář <rkrc...@redhat.com>
> Sent: Wednesday, March 28, 2018 3:27 PM
> To: Moger, Babu <babu.mo...@amd.com>
> Cc: j...@8bytes.org; t...@linutronix.de; mi...@redhat.com;
> h...@zytor.com; x...@kernel.org; pbonz...@redh
> -Original Message-
> From: Radim Krčmář <rkrc...@redhat.com>
> Sent: Wednesday, March 28, 2018 3:31 PM
> To: Moger, Babu <babu.mo...@amd.com>
> Cc: j...@8bytes.org; t...@linutronix.de; mi...@redhat.com;
> h...@zytor.com; x...@kernel.org; pbonz...@redh
Hi James,
On 10/05/2018 11:18 AM, James Morse wrote:
> Hi Babu,
>
> (Thanks for looping me in!)
>
> On 28/09/18 02:57, Moger, Babu wrote:
>>> On Mon, 24 Sep 2018, Moger, Babu wrote:
>>>
>>>> This series adds support for AMD64 architectural ex
Hi James,
On 10/05/2018 11:20 AM, James Morse wrote:
> Hi Babu,
>
> On 24/09/18 20:19, Moger, Babu wrote:
>> Enables QOS feature on AMD.
>> Following QoS sub-features are supported in AMD if the underlying
>> hardware supports it.
>> - L3 Cache allocation enf
> -Original Message-
> From: Borislav Petkov
> Sent: Friday, October 5, 2018 4:31 PM
> To: Moger, Babu
> Cc: t...@linutronix.de; mi...@redhat.com; h...@zytor.com;
> reinette.cha...@intel.com; fenghua...@intel.com; james.mo...@arm.com;
> vikas.shiva...@li
Hi Fenghua,
> -Original Message-
> From: Fenghua Yu
> Sent: Friday, October 5, 2018 6:39 PM
> To: Moger, Babu
> Cc: t...@linutronix.de; mi...@redhat.com; h...@zytor.com;
> reinette.cha...@intel.com; fenghua...@intel.com; james.mo...@arm.com;
> vikas.shiva...@li
This series adds support for AMD64 architectural extensions for Platform
Quality of Service. These extensions are intended to provide for the
monitoring of the usage of certain system resources by one or more
processors and for the separate allocation and enforcement of limits on
the use of
Bring all the macros to rdt.h and rename for consistency.
Signed-off-by: Babu Moger
---
arch/x86/kernel/cpu/rdt.c | 3 ---
arch/x86/kernel/cpu/rdt.h | 5 +
arch/x86/kernel/cpu/rdt_monitor.c | 7 ++-
3 files changed, 7 insertions(+), 8 deletions(-)
diff --git
Use newly added config parameter PLATFORM_QOS to compile sources.
This is common parameter across both Intel and AMD.
Signed-off-by: Babu Moger
---
arch/x86/include/asm/rdt_sched.h | 4 ++--
arch/x86/kernel/cpu/Makefile | 4 ++--
include/linux/sched.h| 2 +-
3 files changed, 5
Introduces a new config parameter PLATFORM_QOS.
This will be used as a common config parameter for both Intel and AMD.
Each vendor will have their own config parameter to enable RDT feature.
One for Intel(INTEL_RDT) and one for AMD(AMD_QOS). It can be enabled or
disabled separately. The new
Initialize the resource functions that are different between the
vendors. Some features are initialized differently between the vendors.
Add _intel suffix to Intel specific functions.
For example, MBA feature varies significantly between Intel and AMD.
Separate the initialization of these
From: Sherry Hurwitz
The feature bit X86_FEATURE_MBA is detected via CPUID leaf 0x8008
EBX Bit 06. This bit indicates the support of AMD's MBA feature.
This feature is supported by both Intel and AMD. But they are detected
different CPUID leaves.
Signed-off-by: Babu Moger
Signed-off-by:
Enables QOS feature on AMD.
Following QoS sub-features are supported in AMD if the underlying
hardware supports it.
- L3 Cache allocation enforcement
- L3 Cache occupancy monitoring
- L3 Code-Data Prioritization support
- Memory Bandwidth Enforcement(Allocation)
There are differences in the
Separate the call sequence for rdt_quirks and MBA feature.
This is in preparation to handle vendor differences in these
call sequences.
Signed-off-by: Babu Moger
---
arch/x86/kernel/cpu/rdt.c | 29 +++--
1 file changed, 23 insertions(+), 6 deletions(-)
diff --git
Bring all resource functions that are different between the vendors
into resource structure and initialize them dynamically.
Add _intel suffix to Intel specific functions.
Implement these functions separately for each vendors.
update_mba_bw : Feedback loop bandwidth update functionality is not
As AMD is starting to support RDT(or QOS) features, rename
the RDT functions and definitions to more generic names.
Signed-off-by: Babu Moger
---
arch/x86/include/asm/rdt_sched.h | 22 +++---
arch/x86/kernel/cpu/rdt.c | 24
Introduces the new config parameter AMD_QOS. This parameter will be
used to enable cache and memory bandwidth allocation and monitoring
features on AMD processors. This will enable common config parameter
PLATFORM_QOS if selected.
Signed-off-by: Babu Moger
---
arch/x86/Kconfig | 17
New generation of AMD processors start support RDT(or QOS) features.
With more than one vendors supporting these features, it seems more
appropriate to rename these files.
Signed-off-by: Babu Moger
---
arch/x86/include/asm/{intel_rdt_sched.h => rdt_sched.h} | 0
arch/x86/kernel/cpu/Makefile
As AMD is starting to support RDT(or QOS) features, rename
the RDT functions and definitions to more generic names.
Replace intel_rdt to resctrl where applicable.
Signed-off-by: Babu Moger
---
arch/x86/include/asm/resctrl_sched.h | 24
arch/x86/kernel/cpu/resctrl.c
This series adds support for AMD64 architectural extensions for Platform
Quality of Service. These extensions are intended to provide for the
monitoring of the usage of certain system resources by one or more
processors and for the separate allocation and enforcement of limits on
the use of
Initialize the resource functions that are different between the
vendors. Some features are initialized differently between the vendors.
Add _intel suffix to Intel specific functions.
For example, MBA feature varies significantly between Intel and AMD.
Separate the initialization of these
Bring all resource functions that are different between the vendors
into resource structure and initialize them dynamically.
Add _intel suffix to Intel specific functions.
Implement these functions separately for each vendors.
update_mba_bw : Feedback loop bandwidth update functionality is not
Introduces a new config parameter RESCTRL.
This will be used as a common config parameter for both Intel and AMD.
Each vendor will have their own config parameter to enable RDT feature.
One for Intel(INTEL_RDT) and one for AMD(AMD_QOS). It can be enabled or
disabled separately. The new parameter
From: Sherry Hurwitz
The feature bit X86_FEATURE_MBA is detected via CPUID leaf 0x8008
EBX Bit 06. This bit indicates the support of AMD's MBA feature.
This feature is supported by both Intel and AMD. But they are detected
different CPUID leaves.
Signed-off-by: Sherry Hurwitz
Enables QOS feature on AMD.
Following QoS sub-features are supported in AMD if the underlying
hardware supports it.
- L3 Cache allocation enforcement
- L3 Cache occupancy monitoring
- L3 Code-Data Prioritization support
- Memory Bandwidth Enforcement(Allocation)
The specification for this
Use newly added config parameter RESCTRL to compile sources.
This is common parameter across both Intel and AMD.
Signed-off-by: Babu Moger
---
arch/x86/include/asm/resctrl_sched.h | 4 ++--
arch/x86/kernel/cpu/Makefile | 4 ++--
include/linux/sched.h| 2 +-
3 files
Bring all the macros to resctrl.h and rename for consistency.
Signed-off-by: Babu Moger
---
arch/x86/kernel/cpu/resctrl.c | 3 ---
arch/x86/kernel/cpu/resctrl.h | 5 +
arch/x86/kernel/cpu/resctrl_monitor.c | 7 ++-
3 files changed, 7 insertions(+), 8 deletions(-)
diff
Introduces the new config parameter AMD_QOS. This parameter will be
used to enable cache and memory bandwidth allocation and monitoring
features on AMD processors. This will enable common config parameter
RESCTRL if selected.
Signed-off-by: Babu Moger
---
arch/x86/Kconfig | 17 -
New generation of AMD processors start supporting RDT(or QOS) features.
With more than one vendors supporting these features, it seems more
appropriate to rename these files.
Changed intel_rdt to resctrl where applicable.
Signed-off-by: Babu Moger
---
arch/x86/include/asm/{intel_rdt_sched.h =>
Separate the call sequence for rdt_quirks and MBA feature.
This is in preparation to handle vendor differences in these
call sequences.
Signed-off-by: Babu Moger
---
arch/x86/kernel/cpu/resctrl.c | 29 +++--
1 file changed, 23 insertions(+), 6 deletions(-)
diff --git
Boris,
On 10/11/2018 05:02 PM, Borislav Petkov wrote:
> On Thu, Oct 11, 2018 at 08:33:35PM +0000, Moger, Babu wrote:
>> Introduces the new config parameter AMD_QOS. This parameter will be
>> used to enable cache and memory bandwidth allocation and monitoring
>> featu
Hi Reinette,
On 10/12/2018 02:07 PM, Reinette Chatre wrote:
> Hi Babu,
>
> On 10/11/2018 1:33 PM, Moger, Babu wrote:
>> New generation of AMD processors start supporting RDT(or QOS) features.
>> With more than one vendors supporting these features, it seems more
>
On 10/12/2018 09:43 AM, Borislav Petkov wrote:
> On Fri, Oct 12, 2018 at 02:40:50PM +0000, Moger, Babu wrote:
>> That is correct. CPU_SUP_AMD implicitly means x86.
>> To be more specific, I will change it to
>> "depends on X86_64 && CPU_SUP_AMD" as this fe
On 10/12/2018 02:40 PM, Reinette Chatre wrote:
> Hi Babu,
>
> On 10/11/2018 1:33 PM, Moger, Babu wrote:
>> @@ -883,20 +883,20 @@ static int __init intel_rdt_late_init(void)
>> rdt_online = state;
>>
>> for_each_alloc_capable_rdt_resource(r)
>
This series adds support for AMD64 architectural extensions for Platform
Quality of Service. These extensions are intended to provide for the
monitoring of the usage of certain system resources by one or more
processors and for the separate allocation and enforcement of limits on
the use of
Enables QOS feature on AMD.
Following QoS sub-features are supported in AMD if the underlying
hardware supports it.
- L3 Cache allocation enforcement
- L3 Cache occupancy monitoring
- L3 Code-Data Prioritization support
- Memory Bandwidth Enforcement(Allocation)
The specification for this
Update the MAINTAINERS to reflect the changed file(and documentation)
names in arch/x86/kernel/cpu. The file names have changed from
intel_rdt* to resctrl*.
Signed-off-by: Babu Moger
---
MAINTAINERS | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/MAINTAINERS
Separate the call sequence for rdt_quirks and MBA feature.
This is in preparation to handle vendor differences in these
call sequences.
Signed-off-by: Babu Moger
---
arch/x86/kernel/cpu/resctrl.c | 29 +++--
1 file changed, 23 insertions(+), 6 deletions(-)
diff --git
From: Sherry Hurwitz
The feature bit X86_FEATURE_MBA is detected via CPUID leaf 0x8008
EBX Bit 06. This bit indicates the support of AMD's MBA feature.
This feature is supported by both Intel and AMD. But they are detected
different CPUID leaves.
Signed-off-by: Sherry Hurwitz
Initialize the resource functions that are different between the
vendors. Some features are initialized differently between the vendors.
Add _intel suffix to Intel specific functions.
For example, MBA feature varies significantly between Intel and AMD.
Separate the initialization of these
Introduces the new config parameter AMD_QOS. This parameter will be
used to enable cache and memory bandwidth allocation and monitoring
features on AMD processors. This will enable common config parameter
RESCTRL if selected.
Signed-off-by: Babu Moger
---
arch/x86/Kconfig | 17 -
Use newly added config parameter RESCTRL to compile sources.
This is common parameter across both Intel and AMD.
Signed-off-by: Babu Moger
---
arch/x86/include/asm/resctrl_sched.h | 4 ++--
arch/x86/kernel/cpu/Makefile | 4 ++--
include/linux/sched.h| 2 +-
3 files
Bring all resource functions that are different between the vendors
into resource structure and initialize them dynamically.
Add _intel suffix to Intel specific functions.
Implement these functions separately for each vendors.
update_mba_bw : Feedback loop bandwidth update functionality is not
New generation of AMD processors start supporting RDT(or QOS) features.
With more than one vendors supporting these features, it seems more
appropriate to rename these files.
Changed intel_rdt to resctrl where applicable.
Signed-off-by: Babu Moger
---
arch/x86/include/asm/{intel_rdt_sched.h =>
Bring all the macros to resctrl.h and rename for consistency.
Signed-off-by: Babu Moger
---
arch/x86/kernel/cpu/resctrl.c | 3 ---
arch/x86/kernel/cpu/resctrl.h | 5 +
arch/x86/kernel/cpu/resctrl_monitor.c | 7 ++-
3 files changed, 7 insertions(+), 8 deletions(-)
diff
Rename intel_rdt_ui.txt to generic resctrl_ui.txt and update the
documentation for AMD.
Signed-off-by: Babu Moger
---
Documentation/x86/{intel_rdt_ui.txt => resctrl_ui.txt} | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
rename Documentation/x86/{intel_rdt_ui.txt =>
As AMD is starting to support RDT(or QOS) features, rename
the RDT functions and definitions to more generic names.
Replace intel_rdt to resctrl where applicable.
Signed-off-by: Babu Moger
---
arch/x86/include/asm/resctrl_sched.h | 24
arch/x86/kernel/cpu/resctrl.c
Introduces a new config parameter RESCTRL.
This will be used as a common config parameter for both Intel and AMD.
Each vendor will have their own config parameter to enable RDT feature.
One for Intel(INTEL_RDT) and one for AMD(AMD_QOS). It can be enabled or
disabled separately. The new parameter
Hi Fenghua,
My few comments.
On 10/17/2018 09:40 AM, Moger, Babu wrote:
>
>
> On 10/16/2018 03:32 PM, Fenghua Yu wrote:
>>> From: Moger, Babu [mailto:babu.mo...@amd.com]
>>> On 10/16/2018 11:56 AM, Fenghua Yu wrote:
>>>> With more and more resctrl
On 10/17/2018 01:03 PM, Moger, Babu wrote:
> Hi Fenghua,
> My few comments.
>
> On 10/17/2018 09:40 AM, Moger, Babu wrote:
>>
>>
>> On 10/16/2018 03:32 PM, Fenghua Yu wrote:
>>>> From: Moger, Babu [mailto:babu.mo...@amd.com]
>>>> On
On 10/17/2018 12:28 PM, Prakhya, Sai Praneeth wrote:
>>> No, the selftest in this patch set will not replace intel-cmt-cat or
>>> vice versa.
>>>
>>> The selftest in this patch set has a different purpose from intel-cmt-cat:
>>> the selftest is a test tool which validates resctrl functionalities
Hi Fenghua,
On 10/16/2018 11:56 AM, Fenghua Yu wrote:
> With more and more resctrl features are being added by Intel, AMD
> and ARM, a test tool is becoming more and more useful to validate
> that both hardware and software functionalities work as expected.
I like the initiative here. It is
On 10/16/2018 03:32 PM, Fenghua Yu wrote:
>> From: Moger, Babu [mailto:babu.mo...@amd.com]
>> On 10/16/2018 11:56 AM, Fenghua Yu wrote:
>>> With more and more resctrl features are being added by Intel, AMD and
>>> ARM, a test tool is becoming more and more use
On 10/16/2018 06:48 PM, Fenghua Yu wrote:
> On Mon, Oct 15, 2018 at 08:55:54PM +0000, Moger, Babu wrote:
>> From: Sherry Hurwitz
>>
>> The feature bit X86_FEATURE_MBA is detected via CPUID leaf 0x8008
>> EBX Bit 06. This bit indicates the support of AMD's MBA
Hi Fenghua,
On 10/16/2018 06:45 PM, Fenghua Yu wrote:
> On Mon, Oct 15, 2018 at 08:55:49PM +0000, Moger, Babu wrote:
>> update_mba_bw : Feedback loop bandwidth update functionality is not
>> needed for AMD.
>
> Will you implement update_mba_b
Hi Fenghua, Sai,
> -Original Message-
> From: Fenghua Yu
> Sent: Thursday, October 25, 2018 6:07 PM
> To: Thomas Gleixner ; Ingo Molnar
> ; H Peter Anvin ; Tony Luck
> ; Peter Zijlstra ; Reinette
> Chatre ; Moger, Babu
> ; James Morse ; Ravi V
> Shankar ; Sai P
Hi Fenghua/Sai,
> -Original Message-
> From: Fenghua Yu
> Sent: Thursday, October 25, 2018 6:07 PM
> To: Thomas Gleixner ; Ingo Molnar
> ; H Peter Anvin ; Tony Luck
> ; Peter Zijlstra ; Reinette
> Chatre ; Moger, Babu
> ; James Morse ; Ravi V
> Shankar ; Sai P
Fenghua/Sai,
> -Original Message-
> From: Fenghua Yu
> Sent: Thursday, October 25, 2018 6:07 PM
> To: Thomas Gleixner ; Ingo Molnar
> ; H Peter Anvin ; Tony Luck
> ; Peter Zijlstra ; Reinette
> Chatre ; Moger, Babu
> ; James Morse ; Ravi V
> Shankar ; Sai P
Fenghua, Sai
> -Original Message-
> From: Fenghua Yu
> Sent: Thursday, October 25, 2018 6:07 PM
> To: Thomas Gleixner ; Ingo Molnar
> ; H Peter Anvin ; Tony Luck
> ; Peter Zijlstra ; Reinette
> Chatre ; Moger, Babu
> ; James Morse ; Ravi V
> Shankar ; Sai P
Hi Fenghua,
> -Original Message-
> From: linux-kernel-ow...@vger.kernel.org ow...@vger.kernel.org> On Behalf Of Fenghua Yu
> Sent: Thursday, October 25, 2018 6:07 PM
> To: Thomas Gleixner ; Ingo Molnar
> ; H Peter Anvin ; Tony Luck
> ; Peter Zijlstra ; Reinette
&
Fenghua,
> -Original Message-
> From: Fenghua Yu
> Sent: Tuesday, October 30, 2018 1:36 PM
> To: Moger, Babu ; Fenghua Yu
>
> Cc: Thomas Gleixner ; Ingo Molnar
> ; H Peter Anvin ; Tony Luck
> ; Peter Zijlstra ; Reinette
> Chatre ; James Morse
> ; Ravi V Sh
Jon,
> -Original Message-
> From: linux-kernel-ow...@vger.kernel.org ow...@vger.kernel.org> On Behalf Of Jon Masters
> Sent: Friday, November 2, 2018 1:43 AM
> To: Moger, Babu ; t...@linutronix.de;
> mi...@redhat.com; h...@zytor.com; reinette.cha...@intel.com;
>
Initialize the resource functions that are different between the
vendors. Some features are initialized differently between the vendors.
Add _intel suffix to Intel specific functions.
For example, MBA feature varies significantly between Intel and AMD.
Separate the initialization of these
Idea is to bring all the functions that are different between the
vendors into resource structure and initialize them dynamically.
Add _intel suffix to Intel specific functions.
Following function is implemented separately for each vendors.
cbm_validate : Cache bitmask validate function. AMD
Boris,
On 11/12/18 11:56 AM, Borislav Petkov wrote:
> On Fri, Nov 09, 2018 at 08:52:27PM +0000, Moger, Babu wrote:
>> As AMD is starting to support RDT(or QOS) features, rename
>> the RDT functions and definitions to more generic names.
>>
>> Replace intel_rdt
On 10/31/18 4:02 PM, Fenghua Yu wrote:
> From: Sai Praneeth Prakhya
>
> The callback starts a child process and puts the child pid in created
> resctrl group with specified memory bandwidth in schemata. The child
> starts running benchmark.
>
> Signed-off-by: Sai Praneeth Prakhya
>
On 10/31/18 4:02 PM, Fenghua Yu wrote:
> From: Sai Praneeth Prakhya
>
> Total memory bandwidth can be monitored from perf IMC counter and from
> resctrl file system. Later the two will be compared to verify the total
> memory bandwidth read from resctrl is correct.
>
> Signed-off-by: Sai
Enables QOS feature on AMD.
Following QoS sub-features are supported in AMD if the underlying
hardware supports it.
- L3 Cache allocation enforcement
- L3 Cache occupancy monitoring
- L3 Code-Data Prioritization support
- Memory Bandwidth Enforcement(Allocation)
The specification for this
Update the MAINTAINERS to reflect the changed file(and documentation)
names in arch/x86/kernel/cpu. The file names have changed from
intel_rdt* to resctrl*.
Signed-off-by: Babu Moger
---
MAINTAINERS | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/MAINTAINERS
On 10/02/2018 01:27 PM, Fenghua Yu wrote:
> On Mon, Sep 24, 2018 at 07:19:16PM +0000, Moger, Babu wrote:
>> int parse_bw(void *_buf, struct rdt_resource *r, struct rdt_domain *d);
>> +int parse_bw_amd(void *_buf, struct rdt_resource *r, struct rdt_domain *d);
>
> Please
On 10/02/2018 05:07 PM, Reinette Chatre wrote:
> Hi Babu,
>
> On 9/24/2018 12:19 PM, Moger, Babu wrote:
>> Bring all resource functions that are different between the vendors
>> into resource structure and initialize them dynamically.
>>
>> Implement these func
On 10/02/2018 05:06 PM, Reinette Chatre wrote:
> Hi Babu,
>
> On 9/24/2018 12:19 PM, Moger, Babu wrote:
>> Initialize the resource functions that are different between the
>> vendors. Some features are initialized differently between the vendors.
>>
>>
Hi Reinette,
On 10/02/2018 05:13 PM, Reinette Chatre wrote:
> Hi Babu,
>
> On 9/24/2018 12:19 PM, Moger, Babu wrote:
>> +/*
>> + * Check whether a cache bit mask is valid. AMD allows
>> + * non-contiguous masks.
>> + */
>> +bool cbm_validate_amd(char
On 10/03/2018 01:54 PM, Reinette Chatre wrote:
> Hi Babu,
>
> On 10/2/2018 4:41 PM, Moger, Babu wrote:
>> On 10/02/2018 02:21 PM, Reinette Chatre wrote:
>>> On 9/24/2018 12:19 PM, Moger, Babu wrote:
>>>> static enum cpuhp_state rdt_online;
>>
On 10/03/2018 01:52 PM, Fenghua Yu wrote:
> On Tue, Oct 02, 2018 at 07:16:23PM +0000, Moger, Babu wrote:
>>
>>
>> On 10/02/2018 01:46 PM, Fenghua Yu wrote:
>>> On Tue, Oct 02, 2018 at 05:44:47PM +, Moger, Babu wrote:
>>>> Hi Fenghua,
>>>>
Hi Fenghua,
> -Original Message-
> From: Fenghua Yu
> Sent: Tuesday, October 2, 2018 12:07 PM
> To: Moger, Babu
> Cc: t...@linutronix.de; mi...@redhat.com; h...@zytor.com;
> fenghua...@intel.com; reinette.cha...@intel.com;
> vikas.shiva...@linux.intel.com; t
On 10/02/2018 01:46 PM, Fenghua Yu wrote:
> On Tue, Oct 02, 2018 at 05:44:47PM +0000, Moger, Babu wrote:
>> Hi Fenghua,
>>
>>> -Original Message-
>>> From: Fenghua Yu
>>> Sent: Tuesday, October 2, 2018 12:07 PM
>>> On Mon,
Hi Reinette,
Thanks for the review. My response below.
On 10/02/2018 02:21 PM, Reinette Chatre wrote:
> Hi Babu,
>
> On 9/24/2018 12:19 PM, Moger, Babu wrote:
>> Re-organize the RDT init code. Separate the call sequence for each
>> feature. That way, it is easy to ca
Thomas,
> -Original Message-
> From: Thomas Gleixner
> Sent: Thursday, September 27, 2018 3:14 PM
> To: Moger, Babu
> Cc: mi...@redhat.com; h...@zytor.com; fenghua...@intel.com;
> reinette.cha...@intel.com; vikas.shiva...@linux.intel.com;
> tony.l...@intel.com;
Thomas,
On 10/10/2018 09:16 AM, Thomas Gleixner wrote:
> Babu,
>
> On Wed, 10 Oct 2018, Moger, Babu wrote:
>> On 10/09/2018 05:01 PM, Reinette Chatre wrote:
>>> As far as all the code you touch is concerned it may be easier and cause
>>> less confusion for now
Hi Reinette,
On 10/09/2018 05:01 PM, Reinette Chatre wrote:
> Hi Babu,
>
> On 10/9/2018 2:17 PM, Moger, Babu wrote:
>> On 10/09/2018 11:39 AM, Reinette Chatre wrote:
>>> Hi Babu,
>>>
>>> On 10/5/2018 1:55 PM, Moger, Babu wrote:
>>>> New
On 10/10/2018 12:53 PM, Reinette Chatre wrote:
> Hi Babu,
>
> On 10/10/2018 7:11 AM, Moger, Babu wrote:
>> On 10/09/2018 05:01 PM, Reinette Chatre wrote:
>>> On 10/9/2018 2:17 PM, Moger, Babu wrote:
>>>> On 10/09/2018 11:39 AM, Reinette Chatre wrote:
>
On 10/09/2018 12:18 PM, Reinette Chatre wrote:
> Hi Babu,
>
> On 10/5/2018 1:55 PM, Moger, Babu wrote:
>> diff --git a/arch/x86/kernel/cpu/rdt_ctrlmondata.c
>> b/arch/x86/kernel/cpu/rdt_ctrlmondata.c
>> index 812cc5c5e39e..ee3e8389d8d2 100644
>> --- a/arch
Hi Reinette,
On 10/09/2018 11:39 AM, Reinette Chatre wrote:
> Hi Babu,
>
> On 10/5/2018 1:55 PM, Moger, Babu wrote:
>> New generation of AMD processors start support RDT(or QOS) features.
>> With more than one vendors supporting these features, it seems more
>> approp
Use newly added config parameter PLATFORM_QOS to compile sources.
This is common parameter across both Intel and AMD.
Signed-off-by: Babu Moger
---
arch/x86/include/asm/rdt_sched.h | 4 ++--
arch/x86/kernel/cpu/Makefile | 4 ++--
include/linux/sched.h| 2 +-
3 files changed, 5
Initialize the resource functions that are different between the
vendors. Some features are initialized differently between the vendors.
For example, MBA feature varies significantly between Intel and AMD.
Separate the initialization of these resource functions. That way we
can easily add AMD's
As AMD is starting to support RDT(or QOS) features, rename
the RDT functions and definitions to more generic names.
Signed-off-by: Babu Moger
---
arch/x86/include/asm/rdt_sched.h | 22 +++---
arch/x86/kernel/cpu/rdt.c | 24
Bring all resource functions that are different between the vendors
into resource structure and initialize them dynamically.
Implement these functions separately for each vendors.
update_mba_bw : Feedback loop bandwidth update functionality is not
needed for AMD.
cbm_validate :
Introduces the new config parameter AMD_QOS. This parameter will be
used to enable cache and memory bandwidth allocation and monitoring
features on AMD processors. This will enable common config parameter
PLATFORM_QOS if selected.
Signed-off-by: Babu Moger
---
arch/x86/Kconfig | 17
Re-organize the RDT init code. Separate the call sequence for each
feature. That way, it is easy to call quirks or features separately
for each vendor if there are differences.
Signed-off-by: Babu Moger
---
arch/x86/kernel/cpu/rdt.c | 44 ---
1 file changed,
Enables QOS feature on AMD.
Following QoS sub-features are supported in AMD if the underlying
hardware supports it.
- L3 Cache allocation enforcement
- L3 Cache occupancy monitoring
- L3 Code-Data Prioritization support
- Memory Bandwidth Enforcement(Allocation)
There are differences in the
From: Sherry Hurwitz
The feature bit X86_FEATURE_MBA is detected via CPUID leaf 0x8008
EBX Bit 06. This bit indicates the support of AMD's MBA feature.
Signed-off-by: Babu Moger
Signed-off-by: Sherry Hurwitz
---
arch/x86/kernel/cpu/scattered.c | 1 +
1 file changed, 1 insertion(+)
diff
This series adds support for AMD64 architectural extensions for Platform
Quality of Service. These extensions are intended to provide for the
monitoring of the usage of certain system resources by one or more
processors and for the separate allocation and enforcement of limits on
the use of
New generation of AMD processors start support RDT(or QOS) features.
With more than one vendors supporting these features, it seems more
appropriate to rename these files.
Signed-off-by: Babu Moger
---
arch/x86/include/asm/{intel_rdt_sched.h => rdt_sched.h} | 0
arch/x86/kernel/cpu/Makefile
Introduces a new config parameter PLATFORM_QOS.
This will be used as a common config parameter for both Intel and AMD.
Each vendor will have their own config parameter to enable RDT feature.
One for Intel(INTEL_RDT) and one for AMD(AMD_QOS). It can be enabled or
disabled separately. The new
My bad.. Sorry about this. I think this should also go to
sta...@vger.kernel.org
> -Original Message-
> From: Luiz Capitulino
> Sent: Friday, November 23, 2018 12:27 PM
> To: Liran Alon
> Cc: Paolo Bonzini ; Moger, Babu
> ; k...@vger.kernel.org; linux-
> ker...@vger
Fix the compiler warning caused by a recent change.
Fixes: a36c5ff560fb ("x86/resctrl: Bring cbm_validate() into the resource
structure")
Reported-by: Dan Carpenter
Signed-off-by: Babu Moger
---
arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Fix the following compiler warning caused by recent change.
arch/x86/kernel/cpu/resctrl/ctrlmondata.c:227 parse_cbm()
error: uninitialized symbol 'cbm_val'
Fixes: a36c5ff560fb ("x86/resctrl: Bring cbm_validate() into the resource
structure")
Reported-by: Dan Carpenter
Signed-off-by: Babu
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