Re: [patches] [PATCH 1/9] RISC-V: Init and Halt Code

2017-07-10 Thread Palmer Dabbelt
On Fri, 07 Jul 2017 05:58:55 PDT (-0700), j.neuschae...@gmx.net wrote: > On Thu, Jul 06, 2017 at 03:34:39PM -0700, Palmer Dabbelt wrote: >> On Tue, 04 Jul 2017 14:54:01 PDT (-0700), j.neuschae...@gmx.net wrote: > [...] >> >> +#define DO_ERROR_INF

Re: [PATCH 2/9] RISC-V: Atomic and Locking Code

2017-07-10 Thread Palmer Dabbelt
On Thu, 06 Jul 2017 19:14:25 PDT (-0700), boqun.f...@gmail.com wrote: > On Thu, Jul 06, 2017 at 06:04:13PM -0700, Palmer Dabbelt wrote: > [...] >> >> +#define __smp_load_acquire(p)

Re: [PATCH 2/9] RISC-V: Atomic and Locking Code

2017-07-10 Thread Palmer Dabbelt
On Fri, 07 Jul 2017 01:08:19 PDT (-0700), pet...@infradead.org wrote: > On Thu, Jul 06, 2017 at 06:04:13PM -0700, Palmer Dabbelt wrote: >> +/* >> + * TODO_RISCV_MEMORY_MODEL: I don't think RISC-V is allowed to perform a >> + * speculative load, but we're going to wa

Re: [patches] [PATCH 2/9] RISC-V: Atomic and Locking Code

2017-07-10 Thread Palmer Dabbelt
On Fri, 07 Jul 2017 06:16:07 PDT (-0700), j.neuschae...@gmx.net wrote: > On Tue, Jul 04, 2017 at 12:50:55PM -0700, Palmer Dabbelt wrote: > [...] >> +/* These barries need to enforce ordering on both devices or memory. */ > > Very minor nit: s/barries/barriers/ (in severa

Re: [PATCH 8/9] RISC-V: User-facing API

2017-07-11 Thread Palmer Dabbelt
On Tue, 11 Jul 2017 06:22:15 PDT (-0700), will.dea...@arm.com wrote: > On Mon, Jul 10, 2017 at 01:00:29PM -0700, Palmer Dabbelt wrote: >> On Thu, 06 Jul 2017 08:45:13 PDT (-0700), will.dea...@arm.com wrote: >> > On Thu, Jul 06, 2017 at 08:34:27AM -0700, Christoph Hellwig wrote:

Re: [PATCH 16/17] RISC-V: User-facing API

2017-07-12 Thread Palmer Dabbelt
On Wed, 12 Jul 2017 04:07:51 PDT (-0700), james.ho...@imgtec.com wrote: > On Tue, Jul 11, 2017 at 06:31:29PM -0700, Palmer Dabbelt wrote: >> diff --git a/arch/riscv/include/asm/unistd.h >> b/arch/riscv/include/asm/unistd.h >> new file mode 100644 >> index 000

Re: [PATCH 08/17] tty: New RISC-V SBI console driver

2017-07-12 Thread Palmer Dabbelt
On Wed, 12 Jul 2017 04:04:00 PDT (-0700), m...@ellerman.id.au wrote: > Palmer Dabbelt <pal...@dabbelt.com> writes: > >> On Mon, 10 Jul 2017 23:21:07 PDT (-0700), m...@ellerman.id.au wrote: >>> Palmer Dabbelt <pal...@dabbelt.com> writes: >>>> >>

Re: [PATCH 10/17] RISC-V: Atomic and Locking Code

2017-07-12 Thread Palmer Dabbelt
On Wed, 12 Jul 2017 05:40:49 PDT (-0700), boqun.f...@gmail.com wrote: > On Tue, Jul 11, 2017 at 06:31:23PM -0700, Palmer Dabbelt wrote: > [...] >> diff --git a/arch/riscv/include/asm/bitops.h >> b/arch/riscv/include/asm/bitops.h >> new file mode 100644 >> in

Re: [patches] [PATCH 17/17] RISC-V: Build Infastructure

2017-07-25 Thread Palmer Dabbelt
On Tue, 25 Jul 2017 19:57:17 PDT (-0700), j.neuschae...@gmx.net wrote: > On Tue, Jul 11, 2017 at 06:31:30PM -0700, Palmer Dabbelt wrote: >> This patch contains all the build infastructure that actually enables >> the RISC-V port. This includes Makefiles, linker scripts, and K

[PATCH 13/17] RISC-V: Task implementation

2017-07-11 Thread Palmer Dabbelt
This patch contains the implementation of tasks on RISC-V, most of which is involved in task switching. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- arch/riscv/include/asm/asm-offsets.h | 1 + arch/riscv/include/asm/current.h | 45 arch/riscv/include/asm/kprobes.h

[PATCH 16/17] RISC-V: User-facing API

2017-07-11 Thread Palmer Dabbelt
This patch contains code that is in some way visible to the user: including via system calls, the VDSO, module loading and signal handling. It also contains some generic code that is ABI visible. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- arch/riscv/include/asm

RISC-V Linux Port v6

2017-07-11 Thread Palmer Dabbelt
While it's only been a day since the last patch set (which might be a bit fast), I've generally been spinning new patch sets whenever I get through my inbox. For my other patch sets I've managed to get buried in a week's worth of email in a few hours, but for this one it appears there's been

[PATCH 03/17] pci: Add a generic, weakly-linked pcibios_fixup_bus

2017-07-11 Thread Palmer Dabbelt
pcibios_fixup_bus. None of the other architectures export this, so I just dropped it. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> Reviewed-by: Luis R. Rodriguez <mcg...@kernel.org> --- arch/cris/arch-v32/drivers/pci/bios.c | 4 arch/microblaze/pci/pci-common.c | 6 -- arch/s3

[PATCH 10/17] RISC-V: Atomic and Locking Code

2017-07-11 Thread Palmer Dabbelt
memory model by the end of the year, but my understanding is that the basic definitions we're relying on here won't change significantly. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- arch/riscv/include/asm/atomic.h | 328 arch/riscv/inclu

[PATCH 12/17] RISC-V: ELF and module implementation

2017-07-11 Thread Palmer Dabbelt
This patch contains the code that interfaces with ELF objects on RISC-V systems, the vast majority of which is present to load kernel modules. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- arch/riscv/include/asm/compat.h | 29 ++ arch/riscv/include/asm/elf.h

[PATCH 11/17] RISC-V: Generic library routines and assembly

2017-07-11 Thread Palmer Dabbelt
This patch contains code that is more specific to the RISC-V ISA than it is to Linux. It contains string and math operations, C wrappers for various assembly instructions, stack walking code, and uaccess. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- arch/riscv/include/asm

[PATCH 04/17] MAINTAINERS: Add RISC-V

2017-07-11 Thread Palmer Dabbelt
From: Jonathan Neuschäfer <j.neuschae...@gmx.net> RISC-V needs a MAINTAINERS entry. Let's add one. Signed-off-by: Jonathan Neuschäfer <j.neuschae...@gmx.net> Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- MAINTAINERS | 8 1 file changed, 8 inserti

[PATCH 09/17] RISC-V: Init and Halt Code

2017-07-11 Thread Palmer Dabbelt
This contains the various __init C functions, the initial assembly kernel entry point, and the code to reset the system. When a file was init-related this patch contains the entire file. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- arch/riscv/include/asm/bug.h

[PATCH 05/17] clocksource: New RISC-V SBI timer driver

2017-07-11 Thread Palmer Dabbelt
the hardware from the clocksource driver by taking a pair of function pointers to issue the actual RISC-V specific instructions. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- drivers/clocksource/Kconfig | 8 + drivers/clocksource/Makefile | 1 + drivers/clock

[PATCH 17/17] RISC-V: Build Infastructure

2017-07-11 Thread Palmer Dabbelt
building locally. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- Makefile | 3 +- arch/riscv/Kconfig| 283 ++ arch/riscv/Makefile | 64 +++ arch/riscv/configs/f

[PATCH 15/17] RISC-V: Paging and MMU

2017-07-11 Thread Palmer Dabbelt
This patch contains code to manage the RISC-V MMU, including definitions of the page tables and the page walking code. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- arch/riscv/include/asm/mmu_context.h | 69 ++ arch/riscv/include/asm/page.h | 134 +++ arch

[PATCH 14/17] RISC-V: Device, timer, IRQs, and the SBI

2017-07-11 Thread Palmer Dabbelt
This patch contains code that interfaces with devices that are mandated by the RISC-V supervisor specification and that don't have explicit drivers anywhere else in the tree. This includes the staticly defined interrupts, the CSR-mapped timer, and virtualized SBI devices. Signed-off-by: Palmer

[PATCH 02/17] pci: Add a generic, weakly-linked pcibios_align_resource

2017-07-11 Thread Palmer Dabbelt
pcibios_fixup_bus. Only some architectures export this, so I just dropped it. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- arch/arc/kernel/pcibios.c| 13 - arch/arm64/kernel/pci.c | 17 - arch/ia64/pci/pci.c | 7 ---

[PATCH 07/17] irqchip: New RISC-V PLIC Driver

2017-07-11 Thread Palmer Dabbelt
This patch adds a driver for the Platform Level Interrupt Controller (PLIC) specified as part of the RISC-V supervisor level ISA manual. The PLIC connocts global interrupt sources to the local interrupt controller on each hart. A PLIC is present on all RISC-V systems. Signed-off-by: Palmer

[PATCH 08/17] tty: New RISC-V SBI console driver

2017-07-11 Thread Palmer Dabbelt
The RISC-V ISA defines a simple console that is availiable via SBI calls on all systems. This patch adds a driver for this console interface that can act as both a target for early printk and as the system console. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- drivers/tty/hvc/K

[PATCH 06/17] irqchip: RISC-V Local Interrupt Controller Driver

2017-07-11 Thread Palmer Dabbelt
controller). Per-hart local interrupt controllers are found on all RISC-V systems. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- drivers/irqchip/Kconfig | 14 +++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-riscv-intc.c | 213

[PATCH 01/17] lib: Add shared copies of some GCC library routines

2017-07-11 Thread Palmer Dabbelt
are functionally identical to the various other copies. These are availiable via Kconfig as CONFIG_GENERIC_$ROUTINE, which currently isn't used anywhere. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> Reviewed-by: Geert Uytterhoeven <ge...@linux-m68k.org> --- include/lib/l

[PATCH 8/9] RISC-V: User-facing API

2017-06-28 Thread Palmer Dabbelt
This patch contains code that is in some way visible to the user: including via system calls, the VDSO, module loading and signal handling. It also contains some generic code that is ABI visible. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- arch/riscv/include/asm

[PATCH 1/9] RISC-V: Init and Halt Code

2017-06-28 Thread Palmer Dabbelt
This contains the various __init C functions, the initial assembly kernel entry point, and the code to reset the system. When a file was init-related, it contains Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- arch/riscv/include/asm/bug.h | 88 +++ arch/riscv/inclu

[PATCH 2/9] RISC-V: Atomic and Locking Code

2017-06-28 Thread Palmer Dabbelt
memory model by the end of the year, but my understanding is that the basic definitions we're relying on here won't change significantly. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- arch/riscv/include/asm/atomic.h | 330 arch/riscv/inclu

RISC-V Linux Port v3

2017-06-28 Thread Palmer Dabbelt
rivers that are required to build and boot a RISC-V system. A tree that contains this patch set merged with all our other patch sets lives at https://github.com/riscv/riscv-linux/tree/riscv-for-submission-v3 commit 319a127e0685ed294996e0e6b25b229f42ec1d6e Merge: a980edd4a4b7 e67734c51bc9 Author:

Re: [PATCH 9/9] RISC-V: Build Infastructure

2017-06-28 Thread Palmer Dabbelt
On Wed, 28 Jun 2017 14:05:14 PDT (-0700), mer...@debian.org wrote: > On Wed, Jun 28, 2017 at 11:55:38AM -0700, Palmer Dabbelt wrote: >> This patch contains all the build infastructure that actually enables >> the RISC-V port. This includes Makefiles, linker scripts, and Kconfig >

[PATCH 4/9] RISC-V: ELF and module implementation

2017-06-28 Thread Palmer Dabbelt
This patch contains the code that interfaces with ELF objects on RISC-V systems, the vast majority of which is present to load kernel modules. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- arch/riscv/include/asm/compat.h | 31 +++ arch/riscv/include/asm/elf.h

[PATCH 6/9] RISC-V: Device, timer, IRQs, and the SBI

2017-06-28 Thread Palmer Dabbelt
This patch contains code that interfaces with devices that are mandated by the RISC-V supervisor specification and that don't have explicit drivers anywhere else in the tree. This includes the staticly defined interrupts, the CSR-mapped timer, and virtualized SBI devices. Signed-off-by: Palmer

[PATCH 5/9] RISC-V: Task implementation

2017-06-28 Thread Palmer Dabbelt
This patch contains the implementation of tasks on RISC-V, most of which is involved in task switching. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- arch/riscv/include/asm/asm-offsets.h | 1 + arch/riscv/include/asm/current.h | 43 arch/riscv/include/asm/kprobes.h

[PATCH 3/9] RISC-V: Generic library routines and assembly

2017-06-28 Thread Palmer Dabbelt
This patch contains code that is more specific to the RISC-V ISA than it is to Linux. It contains string and math operations, C wrappers for various assembly instructions, stack walking code, and uaccess. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- arch/riscv/include/asm

[PATCH 9/9] RISC-V: Build Infastructure

2017-06-28 Thread Palmer Dabbelt
building locally. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- Makefile | 3 +- arch/riscv/Kconfig| 318 ++ arch/riscv/Makefile | 64 ++ arch/riscv/configs/freedom-u500_def

[PATCH 7/9] RISC-V: Paging and MMU

2017-06-28 Thread Palmer Dabbelt
This patch contains code to manage the RISC-V MMU, including definitions of the page tables and the page walking code. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- arch/riscv/include/asm/mmu_context.h | 69 ++ arch/riscv/include/asm/page.h | 138 +++ arch

Re: [PATCH 8/9] RISC-V: User-facing API

2017-06-29 Thread Palmer Dabbelt
On Wed, 28 Jun 2017 15:42:37 PDT (-0700), james.ho...@imgtec.com wrote: > Hi Palmer, > > On Wed, Jun 28, 2017 at 11:55:37AM -0700, Palmer Dabbelt wrote: >> diff --git a/arch/riscv/include/asm/syscalls.h >> b/arch/riscv/include/asm/syscalls.h >> new file mode 1

Re: [PATCH 7/9] RISC-V: Paging and MMU

2017-06-29 Thread Palmer Dabbelt
On Wed, 28 Jun 2017 16:09:59 PDT (-0700), james.ho...@imgtec.com wrote: > On Wed, Jun 28, 2017 at 11:55:36AM -0700, Palmer Dabbelt wrote: >> diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h >> new file mode 100644 >> index ..e1491c20

Re: [PATCH 5/9] RISC-V: Task implementation

2017-06-29 Thread Palmer Dabbelt
On Thu, 29 Jun 2017 01:22:23 PDT (-0700), tklau...@distanz.ch wrote: > On 2017-06-28 at 20:55:34 +0200, Palmer Dabbelt <pal...@dabbelt.com> wrote: > [...] >> diff --git a/arch/riscv/include/asm/kprobes.h >> b/arch/riscv/include/asm/kprobes.h >> new file mod

Re: [PATCH 1/3] dts: RISC-V vendor prefix

2017-06-29 Thread Palmer Dabbelt
On Thu, 29 Jun 2017 13:35:15 PDT (-0700), r...@kernel.org wrote: > On Mon, Jun 26, 2017 at 10:21:22PM -0700, Palmer Dabbelt wrote: >> RISC-V systems use device tree to specify the memory layout of the >> system. This patch reserves the "riscv" vendor prefix, which wi

Re: [PATCH 9/9] RISC-V: Build Infastructure

2017-06-29 Thread Palmer Dabbelt
On Wed, 28 Jun 2017 15:54:42 PDT (-0700), james.ho...@imgtec.com wrote: > On Wed, Jun 28, 2017 at 11:55:38AM -0700, Palmer Dabbelt wrote: >> diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile >> new file mode 100644 >> index ..7f58cd251ab8 >

Re: [PATCH 6/9] RISC-V: Device, timer, IRQs, and the SBI

2017-06-29 Thread Palmer Dabbelt
On Thu, 29 Jun 2017 01:39:25 PDT (-0700), tklau...@distanz.ch wrote: > On 2017-06-28 at 20:55:35 +0200, Palmer Dabbelt <pal...@dabbelt.com> wrote: > [...] >> diff --git a/arch/riscv/include/asm/device.h >> b/arch/riscv/include/asm/device.h >> new file mod

Re: [PATCH 1/9] RISC-V: Init and Halt Code

2017-06-29 Thread Palmer Dabbelt
On Thu, 29 Jun 2017 02:44:32 PDT (-0700), ge...@linux-m68k.org wrote: > Hi Palmer, > > On Wed, Jun 28, 2017 at 8:55 PM, Palmer Dabbelt <pal...@dabbelt.com> wrote: >> This contains the various __init C functions, the initial assembly >> kernel entry point, and the code

Re: [PATCH 5/9] RISC-V: Task implementation

2017-06-29 Thread Palmer Dabbelt
On Wed, 28 Jun 2017 16:32:55 PDT (-0700), james.ho...@imgtec.com wrote: > On Wed, Jun 28, 2017 at 11:55:34AM -0700, Palmer Dabbelt wrote: >> diff --git a/arch/riscv/include/asm/kprobes.h >> b/arch/riscv/include/asm/kprobes.h >> new file mode 100644 >> index 000

Re: [PATCH 9/9] RISC-V: Build Infastructure

2017-06-29 Thread Palmer Dabbelt
On Wed, 28 Jun 2017 14:25:00 PDT (-0700), james.ho...@imgtec.com wrote: > Hi Palmer, > > On Wed, Jun 28, 2017 at 11:55:38AM -0700, Palmer Dabbelt wrote: >> +select SYSRISCV_ATOMIC if !ISA_A > ... >> +config SYSRISCV_ATOMIC >> +bool "Include su

Re: [PATCH 1/2] irqchip: RISC-V Local Interrupt Controller Driver

2017-06-29 Thread Palmer Dabbelt
On Wed, 28 Jun 2017 13:47:40 PDT (-0700), t...@linutronix.de wrote: > On Mon, 26 Jun 2017, Palmer Dabbelt wrote: >> +DEFINE_PER_CPU(struct riscv_irq_data, riscv_irq_data); >> +DEFINE_PER_CPU(atomic_long_t, riscv_early_sie); >> + >> +static void riscv_software_inter

Re: [PATCH 8/9] RISC-V: User-facing API

2017-06-29 Thread Palmer Dabbelt
On Wed, 28 Jun 2017 14:49:44 PDT (-0700), t...@linutronix.de wrote: > On Wed, 28 Jun 2017, Palmer Dabbelt wrote: >> + >> +SYSCALL_DEFINE3(sysriscv_cmpxchg32, unsigned long, arg1, unsigned long, >> arg2, >> +unsigned long, arg3) >> +{ >> +uns

Re: [PATCH 1/2] irqchip: RISC-V Local Interrupt Controller Driver

2017-07-03 Thread Palmer Dabbelt
On Mon, 03 Jul 2017 04:13:34 PDT (-0700), t...@linutronix.de wrote: > On Thu, 29 Jun 2017, Palmer Dabbelt wrote: >> On Wed, 28 Jun 2017 13:47:40 PDT (-0700), t...@linutronix.de wrote: >> In this case the software interrupt is to handle IPIs, so it doesn't really >> make an

RISC-V Linux Port v4

2017-07-04 Thread Palmer Dabbelt
Thanks to everyone who has participated in the review process so far. There have only been a few changes since the v3 patch set: * The cmpxchg64 syscall is no longer enabled on 32-bit systems. It's not possible to provide this on SMP systems, and it's not necessary as glibc knows not to

[PATCH 5/9] RISC-V: Task implementation

2017-07-04 Thread Palmer Dabbelt
This patch contains the implementation of tasks on RISC-V, most of which is involved in task switching. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- arch/riscv/include/asm/asm-offsets.h | 1 + arch/riscv/include/asm/current.h | 44 arch/riscv/include/asm/kprobes.h

[PATCH 8/9] RISC-V: User-facing API

2017-07-04 Thread Palmer Dabbelt
This patch contains code that is in some way visible to the user: including via system calls, the VDSO, module loading and signal handling. It also contains some generic code that is ABI visible. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- arch/riscv/include/asm

[PATCH 6/9] RISC-V: Device, timer, IRQs, and the SBI

2017-07-04 Thread Palmer Dabbelt
This patch contains code that interfaces with devices that are mandated by the RISC-V supervisor specification and that don't have explicit drivers anywhere else in the tree. This includes the staticly defined interrupts, the CSR-mapped timer, and virtualized SBI devices. Signed-off-by: Palmer

[PATCH 7/9] RISC-V: Paging and MMU

2017-07-04 Thread Palmer Dabbelt
This patch contains code to manage the RISC-V MMU, including definitions of the page tables and the page walking code. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- arch/riscv/include/asm/mmu_context.h | 69 ++ arch/riscv/include/asm/page.h | 134 +++ arch

[PATCH 1/9] RISC-V: Init and Halt Code

2017-07-04 Thread Palmer Dabbelt
This contains the various __init C functions, the initial assembly kernel entry point, and the code to reset the system. When a file was init-related, it contains Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- arch/riscv/include/asm/bug.h | 88 +++ arch/riscv/inclu

[PATCH 3/9] RISC-V: Generic library routines and assembly

2017-07-04 Thread Palmer Dabbelt
This patch contains code that is more specific to the RISC-V ISA than it is to Linux. It contains string and math operations, C wrappers for various assembly instructions, stack walking code, and uaccess. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- arch/riscv/include/asm

[PATCH 2/9] RISC-V: Atomic and Locking Code

2017-07-04 Thread Palmer Dabbelt
memory model by the end of the year, but my understanding is that the basic definitions we're relying on here won't change significantly. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- arch/riscv/include/asm/atomic.h | 337 arch/riscv/inclu

[PATCH 4/9] RISC-V: ELF and module implementation

2017-07-04 Thread Palmer Dabbelt
This patch contains the code that interfaces with ELF objects on RISC-V systems, the vast majority of which is present to load kernel modules. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- arch/riscv/include/asm/compat.h | 29 ++ arch/riscv/include/asm/elf.h

[PATCH 9/9] RISC-V: Build Infastructure

2017-07-04 Thread Palmer Dabbelt
building locally. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- Makefile | 3 +- arch/riscv/Kconfig| 304 ++ arch/riscv/Makefile | 64 +++ arch/riscv/configs/f

Re: [PATCH 8/9] RISC-V: User-facing API

2017-07-05 Thread Palmer Dabbelt
On Mon, 03 Jul 2017 16:06:39 PDT (-0700), james.ho...@imgtec.com wrote: > On Thu, Jun 29, 2017 at 02:42:38PM -0700, Palmer Dabbelt wrote: >> On Wed, 28 Jun 2017 15:42:37 PDT (-0700), james.ho...@imgtec.com wrote: >> > On Wed, Jun 28, 2017 at 11:55:37AM -0700, Palmer Dabbelt wrote

Re: [PATCH 2/9] RISC-V: Atomic and Locking Code

2017-07-06 Thread Palmer Dabbelt
On Wed, 05 Jul 2017 01:43:21 PDT (-0700), pet...@infradead.org wrote: > On Tue, Jul 04, 2017 at 12:50:55PM -0700, Palmer Dabbelt wrote: >> +/* >> + * FIXME: I could only find documentation that atomic_{add,sub,inc,dec} are >> + * barrier-free. I'm assuming that and

Re: [patches] [PATCH 1/9] RISC-V: Init and Halt Code

2017-07-06 Thread Palmer Dabbelt
On Tue, 04 Jul 2017 14:54:01 PDT (-0700), j.neuschae...@gmx.net wrote: > Hi, below are some small comments. > > On Tue, Jul 04, 2017 at 12:50:54PM -0700, Palmer Dabbelt wrote: >> This contains the various __init C functions, the initial assembly >> kernel entry point,

[PATCH v7 10/15] RISC-V: ELF and module implementation

2017-07-31 Thread Palmer Dabbelt
This patch contains the code that interfaces with ELF objects on RISC-V systems, the vast majority of which is present to load kernel modules. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- arch/riscv/include/asm/compat.h | 29 ++ arch/riscv/include/asm/elf.h

[PATCH v7 09/15] RISC-V: Generic library routines and assembly

2017-07-31 Thread Palmer Dabbelt
This patch contains code that is more specific to the RISC-V ISA than it is to Linux. It contains string and math operations, C wrappers for various assembly instructions, stack walking code, and uaccess. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- arch/riscv/include/asm

[PATCH v7 07/15] RISC-V: Init and Halt Code

2017-07-31 Thread Palmer Dabbelt
This contains the various __init C functions, the initial assembly kernel entry point, and the code to reset the system. When a file was init-related this patch contains the entire file. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- arch/riscv/include/asm/bug.h

[PATCH v7 11/15] RISC-V: Task implementation

2017-07-31 Thread Palmer Dabbelt
This patch contains the implementation of tasks on RISC-V, most of which is involved in task switching. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- arch/riscv/include/asm/asm-offsets.h | 1 + arch/riscv/include/asm/current.h | 45 arch/riscv/include/asm/kprobes.h

[PATCH v7 12/15] RISC-V: Device, timer, IRQs, and the SBI

2017-07-31 Thread Palmer Dabbelt
This patch contains code that interfaces with devices that are mandated by the RISC-V supervisor specification and that don't have explicit drivers anywhere else in the tree. This includes the staticly defined interrupts, the CSR-mapped timer, and virtualized SBI devices. Signed-off-by: Palmer

[PATCH v7 03/15] clocksource: New RISC-V SBI timer driver

2017-07-31 Thread Palmer Dabbelt
the hardware from the clocksource driver by taking a pair of function pointers to issue the actual RISC-V specific instructions. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- drivers/clocksource/Kconfig | 8 + drivers/clocksource/Makefile | 1 + drivers/clock

[PATCH v7 05/15] irqchip: New RISC-V PLIC Driver

2017-07-31 Thread Palmer Dabbelt
This patch adds a driver for the Platform Level Interrupt Controller (PLIC) specified as part of the RISC-V supervisor level ISA manual. The PLIC connocts global interrupt sources to the local interrupt controller on each hart. A PLIC is present on all RISC-V systems. Signed-off-by: Palmer

[PATCH v7 04/15] irqchip: RISC-V Local Interrupt Controller Driver

2017-07-31 Thread Palmer Dabbelt
controller). Per-hart local interrupt controllers are found on all RISC-V systems. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- drivers/irqchip/Kconfig | 14 +++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-riscv-intc.c | 213

[PATCH v7 02/15] lib: Add shared copies of some GCC library routines

2017-07-31 Thread Palmer Dabbelt
are functionally identical to the various other copies. These are availiable via Kconfig as CONFIG_GENERIC_$ROUTINE, which currently isn't used anywhere. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> Reviewed-by: Geert Uytterhoeven <ge...@linux-m68k.org> Signed-off-by: Palmer Dabbelt <pal

Re: [PATCH 05/17] clocksource: New RISC-V SBI timer driver

2017-07-31 Thread Palmer Dabbelt
Sorry, I missed this before submitting our v7. I'll respond properly in a bit... On Mon, 31 Jul 2017 04:00:26 PDT (-0700), daniel.lezc...@linaro.org wrote: > On 11/07/2017 03:39, Palmer Dabbelt wrote: >> The RISC-V ISA defines a per-hart real-time clock and timer, which is >>

[PATCH v7 14/15] RISC-V: User-facing API

2017-07-31 Thread Palmer Dabbelt
This patch contains code that is in some way visible to the user: including via system calls, the VDSO, module loading and signal handling. It also contains some generic code that is ABI visible. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- arch/riscv/include/asm

[PATCH v7 08/15] RISC-V: Atomic and Locking Code

2017-07-31 Thread Palmer Dabbelt
memory model by the end of the year, but my understanding is that the basic definitions we're relying on here won't change significantly. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- arch/riscv/include/asm/atomic.h | 328 arch/riscv/inclu

[PATCH v7 06/15] tty: New RISC-V SBI console driver

2017-07-31 Thread Palmer Dabbelt
The RISC-V ISA defines a simple console that is availiable via SBI calls on all systems. This patch adds a driver for this console interface that can act as both a target for early printk and as the system console. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- drivers/tty/hvc/K

[PATCH v7 13/15] RISC-V: Paging and MMU

2017-07-31 Thread Palmer Dabbelt
This patch contains code to manage the RISC-V MMU, including definitions of the page tables and the page walking code. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- arch/riscv/include/asm/mmu_context.h | 69 ++ arch/riscv/include/asm/page.h | 134 +++ arch

[PATCH v7 01/15] MAINTAINERS: Add RISC-V

2017-07-31 Thread Palmer Dabbelt
From: Jonathan Neuschäfer <j.neuschae...@gmx.net> RISC-V needs a MAINTAINERS entry. Let's add one. Signed-off-by: Jonathan Neuschäfer <j.neuschae...@gmx.net> Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- MAINTAINERS | 9 + 1 file changed, 9 inserti

[PATCH v7 15/15] RISC-V: Build Infastructure

2017-07-31 Thread Palmer Dabbelt
building locally. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- Makefile | 3 +- arch/riscv/Kconfig| 275 ++ arch/riscv/Makefile | 64 +++ arch/riscv/configs/f

RISC-V Linux Port v7

2017-07-31 Thread Palmer Dabbelt
It's been a while since my last patch set, but the changes han been fairly minimal: * The PCI cleanup patches have been dropped, we'll do them as a separate patch set later. * We've the Kconfig entries from CONFIG_ISA_* to CONFIG_RISCV_ISA_*, to make grep easier. * There have been a

Re: [PATCH v7 02/15] lib: Add shared copies of some GCC library routines

2017-08-20 Thread Palmer Dabbelt
On Tue, 01 Aug 2017 06:06:20 PDT (-0700), andriy.shevche...@linux.intel.com wrote: > On Mon, 2017-07-31 at 17:59 -0700, Palmer Dabbelt wrote: >> Many ports (m32r, microblaze, mips, parisc, score, and sparc) use >> functionally identical copies of various GCC library routine files

Re: [PATCH 03/20] asm-generic: Drop getrlimit and setrlimit syscalls from default list

2017-06-20 Thread Palmer Dabbelt
On Tue, 20 Jun 2017 08:27:36 PDT (-0700), Arnd Bergmann wrote: > On Tue, Jun 20, 2017 at 4:54 PM, Yury Norov wrote: >> On Tue, Jun 20, 2017 at 04:20:43PM +0200, Arnd Bergmann wrote: >>> On Tue, Jun 20, 2017 at 3:37 PM, Yury Norov >>> wrote:

Re: [PATCH] Documentation: atomic_ops.txt is core-api/atomic_ops.rst

2017-06-23 Thread Palmer Dabbelt
On Fri, 23 Jun 2017 13:29:54 PDT (-0700), cor...@lwn.net wrote: > On Fri, 23 Jun 2017 13:25:22 -0700 > Palmer Dabbelt <pal...@dabbelt.com> wrote: > >> I was reading the memory barries documentation in order to make sure the >> RISC-V barries were correct, and I found

[PATCH] Documentation: atomic_ops.txt is core-api/atomic_ops.rst

2017-06-23 Thread Palmer Dabbelt
I was reading the memory barries documentation in order to make sure the RISC-V barries were correct, and I found a broken link to the atomic operations documentation. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> Acked-by: Will Deacon <will.dea...@arm.com> --- Document

Re: [PATCH] pci: Add and use PCI_GENERIC_SETUP Kconfig entry

2017-06-23 Thread Palmer Dabbelt
On Fri, 23 Jun 2017 15:01:04 PDT (-0700), james.ho...@imgtec.com wrote: > On Fri, Jun 23, 2017 at 02:45:38PM -0700, Palmer Dabbelt wrote: >> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig >> index 4c1a35f15838..86872246951c 100644 >> --- a/arch/arm/Kconfig >> +++ b/a

[PATCH] pci: Add and use PCI_GENERIC_SETUP Kconfig entry

2017-06-23 Thread Palmer Dabbelt
with the patch applied. The intention is that this patch doesn't change the behavior of any build. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- arch/alpha/Kconfig | 1 + arch/arc/Kconfig | 1 + arch/arm/Kconfig | 1 + arch/arm64/Kconfig | 1 + arch/m68k/K

Re: [patches] Re: [PATCH 01/17] drivers: support PCIe in RISCV

2017-06-23 Thread Palmer Dabbelt
On Wed, 07 Jun 2017 10:40:50 PDT (-0700), Olof Johansson wrote: > On Wed, Jun 7, 2017 at 10:09 AM, Wesley Terpstra <wes...@sifive.com> wrote: >> >> >> On Jun 7, 2017 7:26 AM, "Christoph Hellwig" <h...@infradead.org> wrote: >> >> On Tue,

[PATCH] pci: Add and use PCI_GENERIC_SETUP Kconfig entry

2017-06-23 Thread Palmer Dabbelt
with the patch applied. The intention is that this patch doesn't change the behavior of any build. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> Reviewed-by: James Hogan <james.ho...@imgtec.com> --- arch/alpha/Kconfig | 1 + arch/arc/Kconfig | 1 + arch/arm/Kconfi

[PATCH] pcie-xilinx: OF-PCIe numbers legacy interrupts from 1

2017-06-23 Thread Palmer Dabbelt
From: "Wesley W. Terpstra" <wes...@sifive.com> Without this patch we can't use the 4th legacy PCIe interrupt. This is a workaround: there are only 4 legacy interrupts, but since they're numbered starting from 1 instead of 0 this just adds a 5th interrupt. Signed-off-by: Pal

[PATCH] Documentation: atomic_ops.txt is core-api/atomic_ops.rst

2017-06-23 Thread Palmer Dabbelt
I was reading the memory barries documentation in order to make sure the RISC-V barries were correct, and I found a broken link to the atomic operations documentation. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> Acked-by: Will Deacon <will.dea...@arm.com> --- Document

Re: [PATCH 12/17] tty: New RISC-V SBI Console Driver

2017-06-23 Thread Palmer Dabbelt
On Wed, 07 Jun 2017 00:58:04 PDT (-0700), Arnd Bergmann wrote: > On Wed, Jun 7, 2017 at 9:15 AM, Geert Uytterhoeven <ge...@linux-m68k.org> > wrote: >> CC (hypervisor) console folks >> >> On Wed, Jun 7, 2017 at 1:00 AM, Palmer Dabbelt <pal...@dabbelt.com> wro

Re: [PATCH 10/17] irqchip: New RISC-V PLIC Driver

2017-06-23 Thread Palmer Dabbelt
On Wed, 07 Jun 2017 00:55:28 PDT (-0700), Arnd Bergmann wrote: > On Wed, Jun 7, 2017 at 9:13 AM, Geert Uytterhoeven > wrote: >>> +struct plic_enable_context { >>> + atomic_t mask[32]; // 32-bit * 32-entry >>> +}; > > You use many '//' style comments in this file,

Re: [PATCH 09/17] clocksource/timer-riscv: New RISC-V Clocksource

2017-06-23 Thread Palmer Dabbelt
On Wed, 07 Jun 2017 00:25:37 PDT (-0700), Arnd Bergmann wrote: > On Wed, Jun 7, 2017 at 9:12 AM, Geert Uytterhoeven <ge...@linux-m68k.org> > wrote: >> CC clocksource folks >> >> On Wed, Jun 7, 2017 at 12:59 AM, Palmer Dabbelt <pal...@dabbelt.com> wrote: >

Re: [PATCH 5/7] RISC-V: arch/riscv/lib

2017-06-23 Thread Palmer Dabbelt
On Wed, 07 Jun 2017 00:35:04 PDT (-0700), Arnd Bergmann wrote: > On Tue, Jun 6, 2017 at 10:53 PM, Palmer Dabbelt <pal...@dabbelt.com> wrote: >> On Tue, 06 Jun 2017 02:31:02 PDT (-0700), Arnd Bergmann wrote: >>> On Tue, Jun 6, 2017 at 6:56 AM, Palmer Dabbelt <pal...@dabb

Re: [PATCH 13/17] RISC-V: Add include subdirectory

2017-06-23 Thread Palmer Dabbelt
On Wed, 07 Jun 2017 01:12:00 PDT (-0700), Arnd Bergmann wrote: > On Wed, Jun 7, 2017 at 1:00 AM, Palmer Dabbelt <pal...@dabbelt.com> wrote: >> This patch adds the include files for the RISC-V port. These are mostly >> based on the score port, but there are a lot of arm64-b

Re: [PATCH 09/17] clocksource/timer-riscv: New RISC-V Clocksource

2017-06-23 Thread Palmer Dabbelt
On Wed, 07 Jun 2017 02:43:09 PDT (-0700), marc.zyng...@arm.com wrote: > On 06/06/17 23:59, Palmer Dabbelt wrote: >> The RISC-V ISA defines a single RTC as well as an SBI oneshot timer. >> This timer is present on all RISC-V systems. >> >> Signed-off-by: Palmer

[PATCH 2/3] pci: Add a generic, weakly-linked pcibios_align_resource

2017-06-23 Thread Palmer Dabbelt
pcibios_fixup_bus. Only some architectures export this, so I just dropped it. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- arch/arc/kernel/pcibios.c| 9 - arch/arm64/kernel/pci.c | 9 - arch/ia64/pci/pci.c | 7 --- arch/micr

Re: [PATCH 06/17] pci: Add generic pcibios_{fixup_bus,align_resource}

2017-06-23 Thread Palmer Dabbelt
On Wed, 07 Jun 2017 01:01:57 PDT (-0700), Arnd Bergmann wrote: > On Wed, Jun 7, 2017 at 9:19 AM, Geert Uytterhoeven <ge...@linux-m68k.org> > wrote: >> CC pci folks >> >> On Wed, Jun 7, 2017 at 12:59 AM, Palmer Dabbelt <pal...@dabbelt.com> wrote: &

[PATCH 1/3] pci: Add a generic, weakly-linked pcibios_fixup_bus

2017-06-23 Thread Palmer Dabbelt
pcibios_fixup_bus. None of the other architectures export this, so I just dropped it. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> --- arch/arc/kernel/pcibios.c | 4 arch/arm64/kernel/pci.c | 8 arch/cris/arch-v32/drivers/pci/bios.c | 4 arch/microbla

Re: [PATCH 06/17] pci: Add generic pcibios_{fixup_bus,align_resource}

2017-06-23 Thread Palmer Dabbelt
On Thu, 08 Jun 2017 01:35:29 PDT (-0700), Arnd Bergmann wrote: > On Thu, Jun 8, 2017 at 10:12 AM, Christoph Hellwig wrote: >> On Wed, Jun 07, 2017 at 09:19:49AM +0200, Geert Uytterhoeven wrote: >>> CC pci folks >> >> Ok, replying with pci folks in Cc then :) >> >> Weak symbols

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