On 02/02/21 19:57, Ben Gardon wrote:
The TDP MMU was implemented to simplify and improve the performance of
KVM's memory management on modern hardware with TDP (EPT / NPT). To build
on the existing performance improvements of the TDP MMU, add the ability
to handle vCPU page faults, enabling and d
On 02/02/21 19:57, Ben Gardon wrote:
Disabling dirty logging is much more intestesting from a testing
perspective if the vCPUs are still running. This also excercises the
code-path in which collapsible SPTEs must be faulted back in at a higher
level after disabling dirty logging.
To: linux-kself
On 02/02/21 19:57, Ben Gardon wrote:
There is a bug in the TDP MMU function to zap SPTEs which could be
replaced with a larger mapping which prevents the function from doing
anything. Fix this by correctly zapping the last level SPTEs.
Fixes: 14881998566d ("kvm: x86/mmu: Support disabling dirty
On 03/02/21 07:50, Like Xu wrote:
Before KVM exposes guest LBR_FMT perf capabilities, it needs to check
whether VMCS has GUEST_IA32_DEBUGCTL guest status field and vmx switch
support on IA32_DEBUGCTL MSR (including VM_EXIT_SAVE_DEBUG_CONTROLS
and VM_ENTRY_LOAD_DEBUG_CONTROLS). It helps nested LBR
On 02/02/21 19:17, Sean Christopherson wrote:
@@ -2617,19 +2618,18 @@ static int dr_interception(struct vcpu_svm *svm)
reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
+ if (!kvm_require_dr(&svm->vcpu, dr & 15)
On 02/02/21 19:34, Sean Christopherson wrote:
On Tue, Feb 02, 2021, Paolo Bonzini wrote:
If not in long mode, the low bits of CR3 are reserved but not enforced to
be zero, so remove those checks. If in long mode, however, the MBZ bits
extend down to the highest physical address bit of the
On 02/02/21 20:01, Michael Roth wrote:
Hi Sean, Paolo,
Following up from previous v3 discussion:
https://lore.kernel.org/kvm/x%2fsfw15owarse...@google.com/
I got bit in internal testing by a bug in v3 of this series that Sean had
already pointed out in v3 comments, so I thought it might be
On 03/02/21 01:38, Sean Christopherson wrote:
+static inline void vmload(hpa_t pa)
This needs to be 'unsigned long', using 'hpa_t' in vmsave() is wrong as the
instructions consume rAX based on effective address. I wrote the function
comment for the vmsave() fix so that it applies to both VMSA
On 02/02/21 23:34, Sean Christopherson wrote:
diff --git a/arch/x86/kvm/svm/svm_ops.h b/arch/x86/kvm/svm/svm_ops.h
index 0c8377aee52c..9f007bc8409a 100644
--- a/arch/x86/kvm/svm/svm_ops.h
+++ b/arch/x86/kvm/svm/svm_ops.h
@@ -51,7 +51,12 @@ static inline void invlpga(unsigned long addr, u32 asid)
On 02/02/21 22:20, Sean Christopherson wrote:
Don't let KVM load when running as an SEV guest, regardless of what
CPUID says. Memory is encrypted with a key that is not accessible to
the host (L0), thus it's impossible for L0 to emulate SVM, e.g. it'll
see garbage when reading the VMCB.
Technic
On 02/02/21 18:38, Sean Christopherson wrote:
IMO, this isn't an improvement. For flows that can't easily be
consolidated to x86.c, e.g. CRs (and DRs?), I agree it makes sense to
use kvm_complete_insn_gp(), but this feels forced. What about a pure
refactoring of kvm_handle_invpcid() to get a si
On 05/01/21 18:20, Sean Christopherson wrote:
This VMLOAD needs the "handle fault on reboot" goo. Seeing the code, I think
I'd prefer to handle this in C code, especially if Paolo takes the svm_ops.h
patch[*]. Actually, I think with that patch it'd make sense to move the
existing VMSAVE+VMLOAD
On 02/02/21 18:19, Sean Christopherson wrote:
On Tue, Feb 02, 2021, Paolo Bonzini wrote:
Push the injection of #GP up to the callers, so that they can just use
kvm_complete_insn_gp.
The SVM and VMX code is identical, IMO we should push all the code to x86.c
instead of shuffling it around
between
nested_vmcb_checks and KVM_SET_SREGS.
Signed-off-by: Paolo Bonzini
---
arch/x86/kvm/svm/nested.c | 12 ++--
arch/x86/kvm/svm/svm.h| 3 ---
arch/x86/kvm/x86.c| 2 ++
3 files changed, 4 insertions(+), 13 deletions(-)
diff --git a/arch/x86/kvm/svm/nested.c b/arch/x86
kvm_dr6_valid and kvm_dr7_valid check that bits 63:32 are zero. Using
them makes it easier to review the code for inconsistencies.
Signed-off-by: Paolo Bonzini
---
arch/x86/kvm/x86.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
Push the injection of #GP up to the callers, so that they can just use
kvm_complete_insn_gp.
Signed-off-by: Paolo Bonzini
---
arch/x86/kvm/svm/svm.c | 7 ++-
arch/x86/kvm/vmx/vmx.c | 5 ++---
arch/x86/kvm/x86.c | 10 --
3 files changed, 8 insertions(+), 14 deletions(-)
diff
kvm_complete_insn_gp is a nice little function that dates back to more
than 10 years ago but was almost never used.
This simple series continues what was done for RDMSR/WRMSR in preparation
for SEV-ES support, using it in XSETBV, INVPCID and MOV to DR intercepts.
Paolo
Paolo Bonzini (3):
KVM
Push the injection of #GP up to the callers, so that they can just use
kvm_complete_insn_gp.
Signed-off-by: Paolo Bonzini
---
arch/x86/kvm/svm/svm.c | 11 ++-
arch/x86/kvm/vmx/vmx.c | 11 ++-
arch/x86/kvm/x86.c | 9 +++--
3 files changed, 15 insertions(+), 16 deletions
use __kvm_set_dr, to
use the right function.
Signed-off-by: Paolo Bonzini
---
arch/x86/kvm/svm/svm.c | 14 +++---
arch/x86/kvm/vmx/vmx.c | 19 ++-
arch/x86/kvm/x86.c | 19 +--
3 files changed, 22 insertions(+), 30 deletions(-)
diff --git a/arch/x86
kvm_complete_insn_gp is a nice little function that dates back to more
than 10 years ago but was almost never used.
This simple series continues what was done for RDMSR/WRMSR in preparation
for SEV-ES support, using it in XSETBV, INVPCID and MOV to DR intercepts.
Paolo
Paolo Bonzini (3):
KVM
On 27/01/21 18:25, Joe Perches wrote:
On Wed, 2021-01-27 at 11:54 +0100, Paolo Bonzini wrote:
On 27/01/21 03:08, Stephen Zhang wrote:
Given the common pattern:
rmap_printk("%s:"..., __func__,...)
we could improve this by adding '__func__' in rmap_printk().
Currently, t
Now that KVM is using static calls, calling vmx_vcpu_run and
vmx_sync_pir_to_irr does not incur anymore the cost of a
retpoline.
Therefore there is no need anymore to handle EXIT_FASTPATH_REENTER_GUEST
in vendor code.
Signed-off-by: Paolo Bonzini
---
arch/x86/kvm/vmx/vmx.c | 19
On 02/02/21 16:02, Xiaoyao Li wrote:
On 2/2/2021 10:49 PM, Paolo Bonzini wrote:
On 02/02/21 10:04, Chenyi Qiang wrote:
#define DR6_FIXED_1 0xfffe0ff0
-#define DR6_INIT 0x0ff0
+/*
+ * DR6_ACTIVE_LOW is actual the result of DR6_FIXED_1 |
ACTIVE_LOW_BITS.
+ * We can regard all the
former reads too much like "true if
no vCPU has an APIC". - Paolo]
Signed-off-by: Paolo Bonzini
---
arch/x86/kvm/lapic.c | 25 +
arch/x86/kvm/lapic.h | 13 ++---
arch/x86/kvm/mmu/mmu_audit.c | 8
arch/x86/kvm/x86.c
On 01/02/21 07:01, Like Xu wrote:
+uint64_t rdmsr_on_cpu(uint32_t reg)
+{
+ uint64_t data;
+ int fd;
+ char msr_file[64];
+
+ sprintf(msr_file, "/dev/cpu/%d/msr", 0);
+ fd = open(msr_file, O_RDONLY);
+ if (fd < 0)
+ exit(KSFT_SKIP);
+
+ if
On 02/02/21 10:04, Chenyi Qiang wrote:
#define DR6_FIXED_10xfffe0ff0
-#define DR6_INIT 0x0ff0
+/*
+ * DR6_ACTIVE_LOW is actual the result of DR6_FIXED_1 | ACTIVE_LOW_BITS.
+ * We can regard all the current FIXED_1 bits as active_low bits even
+ * though in no case they will be tur
On 01/02/21 06:10, Like Xu wrote:
Hi geniuses,
Please help review this new version which enables the guest LBR.
We already upstreamed the guest LBR support in the host perf, please
check more details in each commit and feel free to test and comment.
QEMU part:
https://lore.kernel.org/qemu-dev
On 01/02/21 06:10, Like Xu wrote:
Usespace could set the bits [0, 5] of the IA32_PERF_CAPABILITIES
MSR which tells about the record format stored in the LBR records.
The LBR will be enabled on the guest if host perf supports LBR
(checked via x86_perf_get_lbr()) and the vcpu model is compatible
w
On 01/02/21 06:10, Like Xu wrote:
- if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM))
- vcpu->arch.perf_capabilities = vmx_get_perf_capabilities();
Why remove this "if"?
pmu->nr_arch_gp_counters = min_t(int, eax.split.num_counters, >
On 01/02/21 17:38, Sean Christopherson wrote:
/*
* On TAA affected systems:
* - nothing to do if TSX is disabled on the host.
* - we emulate TSX_CTRL if present on the host.
* This lets the guest use VERW to clear CPU buffers.
*/
it says "nothin
On 01/02/21 10:53, Chenyi Qiang wrote:
Is the guest expected to do a lot of reads/writes to the MSR (e.g. at
every context switch)?
Even if this is the case, the MSR intercepts and the entry/exit
controls should only be done if CR4.PKS=1. If the guest does not use
PKS, KVM should behave
On 01/02/21 09:46, Paolo Bonzini wrote:
This comment be updated to call out the new TSX_CTRL behavior.
/*
* On TAA affected systems:
* - nothing to do if TSX is disabled on the host.
* - we emulate TSX_CTRL if present on the host.
* This lets the guest
On 01/02/21 09:38, Jiapeng Chong wrote:
Fix the following coccicheck warning:
./arch/x86/kvm/debugfs.c:44:0-23: WARNING: vcpu_tsc_scaling_frac_fops
should be defined with DEFINE_DEBUGFS_ATTRIBUTE.
./arch/x86/kvm/debugfs.c:36:0-23: WARNING: vcpu_tsc_scaling_fops should
be defined with DEFINE_DEB
On 29/01/21 17:58, Sean Christopherson wrote:
On Fri, Jan 29, 2021, Paolo Bonzini wrote:
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 76bce832cade..15733013b266 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -1401,7 +1401,7 @@ static u64 kvm_get_arch_capabilities(void
On 01/02/21 09:13, Maciej S. Szmigiero wrote:
static int kvm_handle_hva_range(struct kvm *kvm,
unsigned long start,
unsigned long end,
@@ -1495,8 +1534,9 @@ static int kvm_handle_hva_range(struct kvm *kvm,
-static int kvm_tdp_m
a, we do not expect HLE and RTM to work in guests anyway).
Cc: sta...@vger.kernel.org
Fixes: cbbaa2727aa3 ("KVM: x86: fix presentation of TSX feature in
ARCH_CAPABILITIES")
Signed-off-by: Paolo Bonzini
---
arch/x86/kvm/vmx/vmx.c | 17 +
arch/x86/kvm/x86.c | 2 +-
On 28/01/21 18:54, Paolo Bonzini wrote:
On 06/11/20 02:16, Yang Weijiang wrote:
Pass through all CET MSRs when the associated CET component (kernel vs.
user) is enabled to improve guest performance. All CET MSRs are context
switched, either via dedicated VMCS fields or XSAVES.
Co-developed-by
On 28/01/21 19:04, Sean Christopherson wrote:
On Thu, Jan 28, 2021, Paolo Bonzini wrote:
On 06/11/20 02:16, Yang Weijiang wrote:
Control-flow Enforcement Technology (CET) provides protection against
Return/Jump-Oriented Programming (ROP/JOP) attack. There're two CET
sub-features: Shadow
On 06/11/20 02:16, Yang Weijiang wrote:
Control-flow Enforcement Technology (CET) provides protection against
Return/Jump-Oriented Programming (ROP/JOP) attack. There're two CET
sub-features: Shadow Stack (SHSTK) and Indirect Branch Tracking (IBT).
SHSTK is to prevent ROP programming and IBT is t
On 06/11/20 02:16, Yang Weijiang wrote:
Pass through all CET MSRs when the associated CET component (kernel vs.
user) is enabled to improve guest performance. All CET MSRs are context
switched, either via dedicated VMCS fields or XSAVES.
Co-developed-by: Zhang Yi Z
Signed-off-by: Zhang Yi Z
C
On 06/11/20 02:16, Yang Weijiang wrote:
+
+ if (((cr4 ^ old_cr4) & X86_CR4_CET) && kvm_cet_supported()) {
+ vmcs_writel(GUEST_SSP, 0);
+ vmcs_writel(GUEST_S_CET, 0);
+ vmcs_writel(GUEST_INTR_SSP_TABLE, 0);
+ }
+
Is this behavior documented
On 06/11/20 02:16, Yang Weijiang wrote:
Report all CET MSRs, including the synthetic GUEST_SSP MSR, as
to-be-saved, e.g. for migration, if CET is supported by KVM.
Co-developed-by: Sean Christopherson
Signed-off-by: Sean Christopherson
Signed-off-by: Yang Weijiang
---
arch/x86/kvm/x86.c | 9
On 06/11/20 02:16, Yang Weijiang wrote:
+static bool cet_is_ssp_msr_accessible(struct kvm_vcpu *vcpu,
+ struct msr_data *msr)
+{
+ u64 mask;
+
+ if (!kvm_cet_supported())
+ return false;
+
+ if (msr->host_initiated)
+
On 06/11/20 02:16, Yang Weijiang wrote:
Introduce a host-only synthetic MSR, MSR_KVM_GUEST_SSP so that the VMM
can read/write the guest's SSP, e.g. to migrate CET state. Use a
synthetic MSR, e.g. as opposed to a VCPU_REG_, as GUEST_SSP is subject
to the same consistency checks as the PL*_SSP MSR
On 06/11/20 02:16, Yang Weijiang wrote:
Introduce a host-only synthetic MSR, MSR_KVM_GUEST_SSP so that the VMM
can read/write the guest's SSP, e.g. to migrate CET state. Use a
synthetic MSR, e.g. as opposed to a VCPU_REG_, as GUEST_SSP is subject
to the same consistency checks as the PL*_SSP MSR
On 28/01/21 18:09, Sean Christopherson wrote:
On Thu, Jan 28, 2021, Paolo Bonzini wrote:
On 14/01/21 01:36, Sean Christopherson wrote:
Add a reverse-CPUID entry for the memory encryption word, 0x801F.EAX,
and use it to override the supported CPUID flags reported to userspace.
Masking the
t;KVM: x86: fix presentation of TSX feature in
ARCH_CAPABILITIES")
Signed-off-by: Paolo Bonzini
---
arch/x86/kvm/vmx/vmx.c | 12 +++-
arch/x86/kvm/x86.c | 2 +-
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/v
On 28/01/21 17:29, Sean Christopherson wrote:
On Thu, Jan 28, 2021, Paolo Bonzini wrote:
I can't find 00/14 in my inbox, so: queued 1-3 and 6-14, thanks.
If it's not too late, v3 has a few tweaks that would be nice to have, as well as
a new patch to
On 14/01/21 01:37, Sean Christopherson wrote:
Skip SEV's expensive WBINVD and DF_FLUSH if there are no SEV ASIDs
waiting to be reclaimed, e.g. if SEV was never used. This "fixes" an
issue where the DF_FLUSH fails during hardware teardown if the original
SEV_INIT failed. Ideally, SEV wouldn't be
On 14/01/21 18:16, Borislav Petkov wrote:
On Thu, Jan 14, 2021 at 09:09:28AM -0800, Sean Christopherson wrote:
Hmm, patch 05/14 depends on the existence of the new word. That's a non-issue
if you're planning on taking this for 5.11. If it's destined for 5.12, maybe
get an ack from Paolo on pat
On 14/01/21 01:36, Sean Christopherson wrote:
Add a reverse-CPUID entry for the memory encryption word, 0x801F.EAX,
and use it to override the supported CPUID flags reported to userspace.
Masking the reported CPUID flags avoids over-reporting KVM support, e.g.
without the mask a SEV-SNP capab
On 28/01/21 07:05, David Stevens wrote:
These patches reduce how often mmu_notifier updates block guest page
faults. The primary benefit of this is the reduction in the likelihood
of extreme latency when handling a page fault due to another thread
having been preempted while modifying host virtua
future regressions.
Cc: Thomas Gleixner
Cc: Ingo Molnar
Cc: "H. Peter Anvin"
Cc: Paolo Bonzini
Cc: Joerg Roedel
Cc: Tom Lendacky
Cc: Brijesh Singh
Cc: Sean Christopherson
Cc: x...@kernel.org
Cc: k...@vger.kernel.org
Cc: sta...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Fixes: 1e80fdc
On 28/01/21 09:36, Vitaly Kuznetsov wrote:
This is embarrassing but I have a (possible) excuse: copy_to_user's
argument is 'void *' so no warning was produced. Surprisingly, no test
caught the breakage. Thanks for debugging and fixing!
So who writes the test:
- the author of the buggy patch
-
On 27/01/21 19:28, Joe Perches wrote:
It's not enabled unless DEBUG is defined (and it's not enabled by default)
or CONFIG_DYNAMIC_DEBUG is enabled and then dynamic_debug jump points are
used when not enabled so I think any slowdown, even when dynamic_debug is
enabled is trivial.
Ah, I confused
On 27/01/21 22:20, Ben Gardon wrote:
On Wed, Jan 27, 2021 at 12:55 PM Paolo Bonzini wrote:
On 27/01/21 21:08, Ben Gardon wrote:
I'm not entirely sure I understand this suggestion. Are you suggesting
we'd have the spinlock and rwlock in a union in struct kvm but then
use a static
On 28/01/21 16:47, Yu Zhang wrote:
Nested VMX was enabled by default in commit <1e58e5e59148> ("KVM:
VMX: enable nested virtualization by default"), which was merged
in Linux 4.20. This patch is to fix the documentation accordingly.
Signed-off-by: Yu Zhang
---
Documentation/virt/kvm/nested-vm
On 28/01/21 03:44, Michael Roth wrote:
Recent commit 255cbecfe0 modified struct kvm_vcpu_arch to make
'cpuid_entries' a pointer to an array of kvm_cpuid_entry2 entries
rather than embedding the array in the struct. KVM_SET_CPUID and
KVM_SET_CPUID2 were updated accordingly, but KVM_GET_CPUID2 was
On 28/01/21 08:17, Xiaoyao Li wrote:
"Active low" means that the bit is usually 1 and goes to 0 when the
condition (such as RTM or bus lock) happens. For almost all those DR6
bits the value is in fact always 1, but if they are defined in the
future it will require no code change.
Why not k
On 27/01/21 21:08, Ben Gardon wrote:
I'm not entirely sure I understand this suggestion. Are you suggesting
we'd have the spinlock and rwlock in a union in struct kvm but then
use a static define to choose which one is used by other functions? It
seems like if we're using static defines the union
On 27/01/21 18:25, Joe Perches wrote:
-#ifdef MMU_DEBUG
-bool dbg = 0;
-module_param(dbg, bool, 0644);
-#endif
-
#define PTE_PREFETCH_NUM 8
#define PT32_LEVEL_BITS 10
@@ -844,17 +839,17 @@ static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
int i, count = 0;
On 27/10/20 22:23, Sean Christopherson wrote:
Clean up KVM's PV TLB flushing when running with EPT on Hyper-V, i.e. as
a nested VMM. No real goal in mind other than the sole patch in v1, which
is a minor change to avoid a future mixup when TDX also wants to define
.remote_flush_tlb. Everything
On 31/12/20 01:26, Sean Christopherson wrote:
This series is a conglomeration of three previous series/patches and a bit
of new code. None of the previous series are directly related, but they
are all needed to achieve the overarching goal of nuking
__kvm_handle_fault_on_reboot(), which is a rat
On 27/10/20 22:23, Sean Christopherson wrote:
+static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, hpa_t root_hpa,
int root_level)
{
struct vcpu_svm *svm = to_svm(vcpu);
unsigned long cr3;
- cr3 = __sme_set(root);
+ cr3 = __sme_set(root_hpa)
On 27/01/21 11:22, Paolo Bonzini wrote:
Linus,
I sent this yesterday but I cannot find it in the archives (weird),
so I am resending it.
Nevermind, I now see that you've pulled it already, though I've gotten
no pr-tracker-bot reply either. Sorry about the noise.
Paolo
The
On 26/01/21 23:02, Sean Christopherson wrote:
You can do the deferred freeing with a short write-side critical section to
ensure all readers have terminated.
Hmm, the most obvious downside I see is that the zap_collapsible_sptes() case
will not scale as well as the RCU approach. E.g. the lock
On 27/01/21 01:57, Chenyi Qiang wrote:
What is the status of the patch to introduce
X86_FEATURE_BUS_LOCK_DETECT (I saw
https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg2389369.html)?
Paolo
Fenghua sent the v4 patch and pinged x86 maintainers, but still no
feedback.
https://
On 25/01/21 22:01, Sean Christopherson wrote:
I 100% think that VMX and SVM should share the bulk of the
code. Improvements to VMX almost always apply in some way to SVM, and vice
versa.
I agree.
IMO, after debugging a few times, associating
error_code with the event being injected is second
On 27/01/21 03:08, Stephen Zhang wrote:
Given the common pattern:
rmap_printk("%s:"..., __func__,...)
we could improve this by adding '__func__' in rmap_printk().
Signed-off-by: Stephen Zhang
---
arch/x86/kvm/mmu/mmu.c | 20 ++--
arch/x86/kvm/mmu/mmu_internal.h |
r memslots
Maxim Levitsky (1):
KVM: nVMX: Sync unsync'd vmcs02 state to vmcs12 on migration
Paolo Bonzini (2):
Merge tag 'kvmarm-fixes-5.11-2' of git://git.kernel.org/.../kvmarm/kvmarm
into HEAD
KVM: x86: allow KVM_REQ_GET_NESTED_STATE_PAGES outside guest mode f
On 27/01/21 04:41, Xiaoyao Li wrote:
On 1/27/2021 12:31 AM, Paolo Bonzini wrote:
On 08/01/21 07:49, Chenyi Qiang wrote:
To avoid breaking the CPUs without bus lock detection, activate the
DR6_BUS_LOCK bit (bit 11) conditionally in DR6_FIXED_1 bits.
The set/clear of DR6_BUS_LOCK is similar to
On 27/01/21 06:45, Xu, Like wrote:
On 2021/1/26 17:30, Paolo Bonzini wrote:
On 08/01/21 02:37, Like Xu wrote:
Userspace could enable guest LBR feature when the exactly supported
LBR format value is initialized to the MSR_IA32_PERF_CAPABILITIES
and the LBR is also compatible with vPMU version
On 27/01/21 07:04, Like Xu wrote:
On 2021/1/26 17:42, Paolo Bonzini wrote:
On 08/01/21 02:36, Like Xu wrote:
@@ -401,6 +398,9 @@ static void intel_pmu_init(struct kvm_vcpu *vcpu)
pmu->fixed_counters[i].idx = i + INTEL_PMC_IDX_FIXED;
pmu->fixed_counters[i].current_conf
On 19/01/21 08:41, Chenyi Qiang wrote:
Hi Paolo,
Thank you for your time. I was just thinking about resending this patch
series to ping you although no changes will be added. I really hope to
get the comments from you.
Do you want me to resend a new non-RFC version as well as the QEMU
im
On 27/01/21 04:00, Chenyi Qiang wrote:
if (pte_access & PT_USER_MASK)
pkr_bits = (vcpu->arch.pkru >> (pte_pkey * 2)) & 3;
+ else if (!kvm_get_msr(vcpu, MSR_IA32_PKRS, &pkrs))
+ pkr_bits = (pkrs >> (pte_pkey * 2)) & 3;
You should be able to always use v
userspace when not available
KVM: arm64: Simplify handling of absent PMU system registers
KVM: arm64: Filter out v8.1+ events on v8.0 HW
KVM: Forbid the use of tagged userspace addresses for memslots
Maxim Levitsky (1):
KVM: nVMX: Sync unsync'd vmcs02 state to vmcs12 on m
On 07/08/20 10:48, Chenyi Qiang wrote:
+{
+ struct vcpu_vmx *vmx = to_vmx(vcpu);
+ unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
+ bool pks_supported = guest_cpuid_has(vcpu, X86_FEATURE_PKS);
+
+ /*
+* set intercept for PKRS when the guest doesn't support pks
On 26/01/21 19:11, Ben Gardon wrote:
When I did a strict replacement I found ~10% worse memory population
performance.
Running dirty_log_perf_test -v 96 -b 3g -i 5 with the TDP MMU
disabled, I got 119 sec to populate memory as the baseline and 134 sec
with an earlier version of this series which
On 26/01/21 20:56, Sean Christopherson wrote:
It does belong in the mmu_role_bits though;-)
Does it? We don't support PKU/PKS for shadow paging, and it's always zero
for EPT. We only support enough PKU/PKS for emulation.
As proposed, yes. The PKU/PKS mask is tracked on a per-mmu basis, e.g.
On 30/09/20 06:36, Sean Christopherson wrote:
CR4.PKS is not in the list of CR4 bits that result in a PDPTE load.
Since it has no effect on PAE paging, I would be surprised if it did
result in a PDPTE load.
It does belong in the mmu_role_bits though;-)
Does it? We don't support PKU/PKS for s
On 07/08/20 10:48, Chenyi Qiang wrote:
if (pte_access & PT_USER_MASK)
pkr_bits = (vcpu->arch.pkru >> (pte_pkey * 2)) & 3;
+ else if (!kvm_get_msr(vcpu, MSR_IA32_PKRS, &pkrs))
+ pkr_bits = (pkrs >> (pte_pkey * 2)) & 3;
reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
@@ -5103,7 +5103,7 @@ static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
}
update_permission_bitmask(vcpu, g_context, false);
- update_pkru_bitmask(vcpu, g_context, false);
+ update_pkr_bitmask(vcpu, g_context, false);
update_last_nonleaf_level(vcpu, g_context);
}
Reviewed-by: Paolo Bonzini
On 26/01/21 02:28, Wanpeng Li wrote:
ping，
On Mon, 18 Jan 2021 at 17:08, Wanpeng Li wrote:
From: Wanpeng Li
The per-cpu vsyscall pvclock data pointer assigns either an element of the
static array hv_clock_boot (#vCPU <= 64) or dynamically allocated memory
hvclock_mem (vCPU > 64), the dynamic
On 15/01/21 04:27, Jason Baron wrote:
Hi,
Convert kvm_x86_ops to use static_call. Shows good performance
gains for cpuid loop micro-benchmark (results in patch 3/3).
Queued, thanks.
Paolo
Thanks,
-Jason
Changes from v1:
-Introduce kvm-x86-ops header with eye towards using this to define
On 07/08/20 10:48, Chenyi Qiang wrote:
* index of the protection domain, so pte_pkey * 2 is
* is the index of the first bit for the domain.
*/
- pkr_bits = (vcpu->arch.pkru >> (pte_pkey * 2)) & 3;
+ if (pte_access & PT_U
On 11/01/21 18:15, Vitaly Kuznetsov wrote:
kvm_no_apic_vcpu is different, we actually need to increase it with
every vCPU which doesn't have LAPIC but maybe we can at least switch to
static_branch_inc()/static_branch_dec(). It is still weird we initialize
it to 'false'
"kvm_no_apic_vcpu" is bad
On 26/01/21 18:47, Ben Gardon wrote:
Enough that it motivated me to implement this more complex union
scheme. While the difference was pronounced in the dirty log perf test
microbenchmark, it's an open question as to whether it would matter in
practice.
I'll look at getting some numbers if it's
On 08/01/21 19:16, kernel test robot wrote:
Hi Chenyi,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on kvm/linux-next]
[also build test ERROR on v5.11-rc2 next-20210108]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patc
On 08/01/21 07:49, Chenyi Qiang wrote:
To avoid breaking the CPUs without bus lock detection, activate the
DR6_BUS_LOCK bit (bit 11) conditionally in DR6_FIXED_1 bits.
The set/clear of DR6_BUS_LOCK is similar to the DR6_RTM in DR6
register. The processor clears DR6_BUS_LOCK when bus lock debug
e
On 08/01/21 02:36, Like Xu wrote:
SVM already has specific handlers of MSR_IA32_DEBUGCTLMSR in the
svm_get/set_msr, so the x86 common part can be safely moved to VMX.
Add vmx_supported_debugctl() to refactor the throwing logic of #GP.
Signed-off-by: Like Xu
Reviewed-by: Andi Kleen
---
arch/
On 08/01/21 02:37, Like Xu wrote:
+
+ /* A flag to reduce the overhead of LBR pass-through or cancellation. */
+ bool already_passthrough;
/* True if LBRs are marked as not intercepted in the MSR bitmap */
bool msr_passthrough;
};
/*
On 08/01/21 02:37, Like Xu wrote:
The vPMU uses GUEST_LBR_IN_USE_IDX (bit 58) in 'pmu->pmc_in_use' to
indicate whether a guest LBR event is still needed by the vcpu. If the
vcpu no longer accesses LBR related registers within a scheduling time
slice, and the enable bit of LBR has been unset, vPMU
On 21/01/21 01:19, Sean Christopherson wrote:
What if we simply make the common mmu_lock a union? The rwlock_t is
probably a bit bigger, but that's a few bytes for an entire VM. And
maybe this would entice/inspire other architectures to move to a similar
MMU model.
Looking more at this, there
On 12/01/21 19:10, Ben Gardon wrote:
Wrap assertions and warnings checking the MMU lock state in a function
which uses lockdep_assert_held. While the existing checks use a few
different functions to check the lock state, they are all better off
using lockdep_assert_held. This will support a refac
On 21/01/21 22:32, Sean Christopherson wrote:
Coming back to this series, I wonder if the RCU approach is truly necessary to
get the desired scalability. If both zap_collapsible_sptes() and NX huge page
recovery zap_only_ leaf SPTEs, then the only path that can actually unlink a
shadow page whi
On 12/01/21 19:10, Ben Gardon wrote:
__tdp_mmu_set_spte is a very important function in the TDP MMU which
already accepts several arguments and will take more in future commits.
To offset this complexity, add a comment to the function describing each
of the arguemnts.
No functional change intend
On 12/01/21 19:10, Ben Gardon wrote:
static void handle_changed_spte(struct kvm *kvm, int as_id, gfn_t gfn,
- u64 old_spte, u64 new_spte, int level);
+ u64 old_spte, u64 new_spte, int level,
+ bool atomic);
On 12/01/21 19:10, Ben Gardon wrote:
Factor out the code to handle a disconnected subtree of the TDP paging
structure from the code to handle the change to an individual SPTE.
Future commits will build on this to allow asynchronous page freeing.
No functional change intended.
Reviewed-by: Peter
On 12/01/21 19:10, Ben Gardon wrote:
The KVM MMU caches already guarantee that shadow page table memory will
be zeroed, so there is no reason to re-zero the page in the TDP MMU page
fault handler.
No functional change intended.
Reviewed-by: Peter Feiner
Signed-off-by: Ben Gardon
---
arch/x
On 12/01/21 19:10, Ben Gardon wrote:
Add lockdep to __tdp_mmu_set_spte to ensure that SPTEs are only modified
under the MMU lock. This lockdep will be updated in future commits to
reflect and validate changes to the TDP MMU's synchronization strategy.
No functional change intended.
Reviewed-by:
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