The dcs/generic dsi read feature is not yet implemented so it
is important to warn the host_transfer() caller in case of
read operation requests.
Signed-off-by: Philippe Cornu
---
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu
Add a fix & a warning in the dsi_host_transfer().
Version 2:
- Simplify the 2 patches following comments from Brian Norris.
- Swap the 2 patches as the return value is only on tx and
in case of rx requests the warning is there.
Version 1:
- Initial commit
Philippe Cornu (2):
drm/br
Add a fix & a warning in the dsi_host_transfer().
Version 2:
- Simplify the 2 patches following comments from Brian Norris.
- Swap the 2 patches as the return value is only on tx and
in case of rx requests the warning is there.
Version 1:
- Initial commit
Philippe Cornu (2):
drm/br
Hi Brian,
And many thanks for your review.
On 01/23/2018 10:38 PM, Brian Norris wrote:
> Hi Philippe,
>
> On Tue, Jan 23, 2018 at 6:26 AM, Philippe Cornu <philippe.co...@st.com> wrote:
>> The dw_mipi_dsi_host_transfer() must return the number of
>> bytes transmitted/
Hi Brian,
And many thanks for your review.
On 01/23/2018 10:38 PM, Brian Norris wrote:
> Hi Philippe,
>
> On Tue, Jan 23, 2018 at 6:26 AM, Philippe Cornu wrote:
>> The dw_mipi_dsi_host_transfer() must return the number of
>> bytes transmitted/received on success instead of
maybe the read feature), sorry to have not wait a single
day more.
> On Tue, Jan 23, 2018 at 6:26 AM, Philippe Cornu <philippe.co...@st.com> wrote:
>> The DCS/GENERIC DSI read feature is not yet implemented so it
>> is important to warn the host_transfer() caller i
maybe the read feature), sorry to have not wait a single
day more.
> On Tue, Jan 23, 2018 at 6:26 AM, Philippe Cornu wrote:
>> The DCS/GENERIC DSI read feature is not yet implemented so it
>> is important to warn the host_transfer() caller in case of
>> read operation req
Hi Brian,
On 01/23/2018 10:15 PM, Brian Norris wrote:
> Hi Philippe,
>
> On Thu, Jan 18, 2018 at 11:40:48AM +, Philippe CORNU wrote:
>> On 01/11/2018 12:16 PM, Philippe CORNU wrote:
>>> To be honest, I do not really like the memcpy here too and I agree with
>&g
Hi Brian,
On 01/23/2018 10:15 PM, Brian Norris wrote:
> Hi Philippe,
>
> On Thu, Jan 18, 2018 at 11:40:48AM +, Philippe CORNU wrote:
>> On 01/11/2018 12:16 PM, Philippe CORNU wrote:
>>> To be honest, I do not really like the memcpy here too and I agree with
>&g
: Andrzej Hajda <a.ha...@samsung.com>
>> Signed-off-by: Philippe Cornu <philippe.co...@st.com>
>> ---
>> Changes in v3: Simplify px_clk probing thanks to Andrzej Hajda comments
>>
>> Changes in v2: Improve px_clk probing in case of ENOENT dt returned value
>
:06PM +0100, Philippe Cornu wrote:
>> The pixel clock is optional. When available, it offers a better
>> preciseness for timing computations and allows to reduce the extra dsi
>> bandwidth in burst mode (from ~20% to ~10-12%, hw platform dependant).
>>
>> Reviewed-
The pixel clock is optional. When available, it offers a better
preciseness for timing computations and allows to reduce the extra dsi
bandwidth in burst mode (from ~20% to ~10-12%, hw platform dependant).
Reviewed-by: Andrzej Hajda <a.ha...@samsung.com>
Signed-off-by: Philippe Cornu <ph
The pixel clock is optional. When available, it offers a better
preciseness for timing computations and allows to reduce the extra dsi
bandwidth in burst mode (from ~20% to ~10-12%, hw platform dependant).
Reviewed-by: Andrzej Hajda
Signed-off-by: Philippe Cornu
---
Changes in v3: Simplify
The dw_mipi_dsi_host_transfer() must return the number of
bytes transmitted/received on success instead of 0.
Note: nb_bytes is introduced in this patch as it will be
re-used with the future dcs/generic dsi read feature.
Signed-off-by: Philippe Cornu <philippe.co...@st.com>
---
drivers/g
The dw_mipi_dsi_host_transfer() must return the number of
bytes transmitted/received on success instead of 0.
Note: nb_bytes is introduced in this patch as it will be
re-used with the future dcs/generic dsi read feature.
Signed-off-by: Philippe Cornu
---
drivers/gpu/drm/bridge/synopsys/dw-mipi
Add a fix & a warning in the dsi_host_transfer().
Philippe Cornu (2):
drm/bridge/synopsys: dsi: Fix dsi_host_transfer() return value
drm/bridge/synopsys: dsi: Add a warning msg on dsi read operations
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 17 +++--
1 file changed
Add a fix & a warning in the dsi_host_transfer().
Philippe Cornu (2):
drm/bridge/synopsys: dsi: Fix dsi_host_transfer() return value
drm/bridge/synopsys: dsi: Add a warning msg on dsi read operations
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 17 +++--
1 file changed
The DCS/GENERIC DSI read feature is not yet implemented so it
is important to warn the host_transfer() caller in case of
read operation requests.
Signed-off-by: Philippe Cornu <philippe.co...@st.com>
---
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 9 -
1 file changed, 8 inse
The DCS/GENERIC DSI read feature is not yet implemented so it
is important to warn the host_transfer() caller in case of
read operation requests.
Signed-off-by: Philippe Cornu
---
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff
Hi Laurent,
A big *thank* for your review
On 01/23/2018 12:30 AM, Laurent Pinchart wrote:
> Hi Philippe,
>
> Thank you for the patch.
>
> On Monday, 22 January 2018 12:26:08 EET Philippe Cornu wrote:
>> Add SPDX identifiers to the Synopsys DesignWare MIPI DSI
>
Hi Laurent,
A big *thank* for your review
On 01/23/2018 12:30 AM, Laurent Pinchart wrote:
> Hi Philippe,
>
> Thank you for the patch.
>
> On Monday, 22 January 2018 12:26:08 EET Philippe Cornu wrote:
>> Add SPDX identifiers to the Synopsys DesignWare MIPI DSI
>
Add support for the stm dsi phy/wrapper version 1.31.
Only lane capabilities need to be modified.
Signed-off-by: Philippe Cornu <philippe.co...@st.com>
---
drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 39 +++
1 file changed, 30 insertions(+), 9 deletions(-)
diff
Add support for the stm dsi phy/wrapper version 1.31.
Only lane capabilities need to be modified.
Signed-off-by: Philippe Cornu
---
drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 39 +++
1 file changed, 30 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/stm
Add the DPI/RGB input pixel clock in mandatory properties
because it really offers a better preciseness for timing
computations.
Signed-off-by: Philippe Cornu <philippe.co...@st.com>
---
Please apply "dt-bindings: display: stm32: correct clock-names
in dsi panel example" b
Add the DPI/RGB input pixel clock in mandatory properties
because it really offers a better preciseness for timing
computations.
Signed-off-by: Philippe Cornu
---
Please apply "dt-bindings: display: stm32: correct clock-names
in dsi panel example" before this patch.
Changes in
In the dsi panel example, clock names in the "clock-names"
field have been swapped:
* "pclk" (peripheral clock) is < 1 CLK_F469_DSI> on stm32f4
* "ref" (dsi phy pll ref clock) is <_hse> on stm32f4
Signed-off-by: Philippe Cornu <philippe.co...@st.com>
In the dsi panel example, clock names in the "clock-names"
field have been swapped:
* "pclk" (peripheral clock) is < 1 CLK_F469_DSI> on stm32f4
* "ref" (dsi phy pll ref clock) is <_hse> on stm32f4
Signed-off-by: Philippe Cornu
---
Documentation/devicet
From: Philippe CORNU <philippe.co...@st.com>
Add support for the Synopsys DesignWare MIPI DSI version 1.31
Two registers need to be updated/added for supporting 1.31:
* PHY_TMR_CFG 0x9c (updated)
1.30 [31:24] phy_hs2lp_time
[23:16] phy_lp2hs_time
[14: 0] max_rd_time
1.31
From: Philippe CORNU
Add support for the Synopsys DesignWare MIPI DSI version 1.31
Two registers need to be updated/added for supporting 1.31:
* PHY_TMR_CFG 0x9c (updated)
1.30 [31:24] phy_hs2lp_time
[23:16] phy_lp2hs_time
[14: 0] max_rd_time
1.31 [25:16] phy_hs2lp_time
Hi Rob,
On 01/22/2018 03:30 PM, Rob Herring wrote:
> On Sun, Jan 21, 2018 at 2:58 PM, Philippe Cornu <philippe.co...@st.com> wrote:
>> In the dsi panel example, clock names in the "clock-names"
>> field have been swapped:
>> * "pclk" (peripheral c
Hi Rob,
On 01/22/2018 03:30 PM, Rob Herring wrote:
> On Sun, Jan 21, 2018 at 2:58 PM, Philippe Cornu wrote:
>> In the dsi panel example, clock names in the "clock-names"
>> field have been swapped:
>> * "pclk" (peripheral clock) is < 1 CLK_F469_DSI&g
To optimize data transfers, align pitch on 128 bytes & height
on 4 bytes. This optimization is not applicable without MMU.
Signed-off-by: Yannick Fertre <yannick.fer...@st.com>
Signed-off-by: Vincent Abriou <vincent.abr...@st.com>
Signed-off-by: Philippe Cornu <philippe.co...@s
To optimize data transfers, align pitch on 128 bytes & height
on 4 bytes. This optimization is not applicable without MMU.
Signed-off-by: Yannick Fertre
Signed-off-by: Vincent Abriou
Signed-off-by: Philippe Cornu
---
drivers/gpu/drm/stm/drv.c | 21 +
1 file changed
Add SPDX identifiers to the Synopsys DesignWare MIPI DSI
host controller driver.
Signed-off-by: Philippe Cornu <philippe.co...@st.com>
---
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/bridge/synop
Add SPDX identifiers to the Synopsys DesignWare MIPI DSI
host controller driver.
Signed-off-by: Philippe Cornu
---
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
b/drivers/gpu
Hi Rob,
On 01/19/2018 11:43 PM, Rob Herring wrote:
> On Fri, Jan 12, 2018 at 04:30:34PM +0100, Philippe Cornu wrote:
>> Add the DPI/RGB input pixel clock in mandatory properties
>> because it really offers a better preciseness for timing
>> computations.
>> Note: Fix
Hi Rob,
On 01/19/2018 11:43 PM, Rob Herring wrote:
> On Fri, Jan 12, 2018 at 04:30:34PM +0100, Philippe Cornu wrote:
>> Add the DPI/RGB input pixel clock in mandatory properties
>> because it really offers a better preciseness for timing
>> computations.
>> Note: Fix
Add the DPI/RGB input pixel clock in mandatory properties
because it really offers a better preciseness for timing
computations.
Signed-off-by: Philippe Cornu <philippe.co...@st.com>
---
Please apply "dt-bindings: display: stm32: correct clock-names
in dsi panel example" b
Add the DPI/RGB input pixel clock in mandatory properties
because it really offers a better preciseness for timing
computations.
Signed-off-by: Philippe Cornu
---
Please apply "dt-bindings: display: stm32: correct clock-names
in dsi panel example" before this patch.
Changes in
In the dsi panel example, clock names in the "clock-names"
field have been swapped:
* "pclk" (peripheral clock) is < 1 CLK_F469_DSI> on stm32f4
* "ref" (dsi phy pll ref clock) is <_hse> on stm32f4
Signed-off-by: Philippe Cornu <philippe.co...@st.com>
In the dsi panel example, clock names in the "clock-names"
field have been swapped:
* "pclk" (peripheral clock) is < 1 CLK_F469_DSI> on stm32f4
* "ref" (dsi phy pll ref clock) is <_hse> on stm32f4
Signed-off-by: Philippe Cornu
---
Documentation/devicet
Add SPDX identifiers to OriseTech OTM8009a panel driver.
Signed-off-by: Philippe Cornu <philippe.co...@st.com>
---
drivers/gpu/drm/panel/panel-orisetech-otm8009a.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c
b/d
Add SPDX identifiers to OriseTech OTM8009a panel driver.
Signed-off-by: Philippe Cornu
---
drivers/gpu/drm/panel/panel-orisetech-otm8009a.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c
b/drivers/gpu/drm/panel/panel
Hi Gabriel,
Tested successfully on f469 disco board.
Tested-by: Philippe Cornu <philippe.co...@st.com>
Many thanks,
Philippe :-)
On 01/18/2018 03:49 PM, gabriel.fernan...@st.com wrote:
> From: Gabriel Fernandez <gabriel.fernan...@st.com>
>
> Update of END_PRIMARY_CLK
Hi Gabriel,
Tested successfully on f469 disco board.
Tested-by: Philippe Cornu <philippe.co...@st.com>
Many thanks,
Philippe :-)
On 01/18/2018 03:49 PM, gabriel.fernan...@st.com wrote:
> From: Gabriel Fernandez <gabriel.fernan...@st.com>
>
> This patch adds DSI cloc
Hi Gabriel,
Tested successfully on f469 disco board.
Tested-by: Philippe Cornu
Many thanks,
Philippe :-)
On 01/18/2018 03:49 PM, gabriel.fernan...@st.com wrote:
> From: Gabriel Fernandez
>
> Update of END_PRIMARY_CLK was missed, it should be after CLK_SYSCLK
> hsi and sysclk are
Hi Gabriel,
Tested successfully on f469 disco board.
Tested-by: Philippe Cornu
Many thanks,
Philippe :-)
On 01/18/2018 03:49 PM, gabriel.fernan...@st.com wrote:
> From: Gabriel Fernandez
>
> This patch adds DSI clock for STM32F469 board
>
> Signed-off-by: Ga
Hi Brian,
On 01/15/2018 06:11 PM, Andrzej Hajda wrote:
> On 15.01.2018 15:40, Philippe CORNU wrote:
>> Hi Andrzej,
>>
>> On 01/15/2018 02:52 PM, Andrzej Hajda wrote:
>>> On 12.01.2018 17:25, Philippe Cornu wrote:
>>>> The pixel clock is op
Hi Brian,
On 01/15/2018 06:11 PM, Andrzej Hajda wrote:
> On 15.01.2018 15:40, Philippe CORNU wrote:
>> Hi Andrzej,
>>
>> On 01/15/2018 02:52 PM, Andrzej Hajda wrote:
>>> On 12.01.2018 17:25, Philippe Cornu wrote:
>>>> The pixel clock is op
Hi Brian,
On 01/11/2018 12:16 PM, Philippe CORNU wrote:
> Hi Brian,
>
> On 01/09/2018 07:55 PM, Brian Norris wrote:
>> Hi Philippe,
>>
>> On Tue, Jan 09, 2018 at 10:48:43AM +, Philippe CORNU wrote:
>>> Hi Brian,
>>>
>>> And many
Hi Brian,
On 01/11/2018 12:16 PM, Philippe CORNU wrote:
> Hi Brian,
>
> On 01/09/2018 07:55 PM, Brian Norris wrote:
>> Hi Philippe,
>>
>> On Tue, Jan 09, 2018 at 10:48:43AM +, Philippe CORNU wrote:
>>> Hi Brian,
>>>
>>> And many
Hi Andrzej,
On 01/15/2018 02:52 PM, Andrzej Hajda wrote:
> On 12.01.2018 17:25, Philippe Cornu wrote:
>> The pixel clock is optional. When available, it offers a better
>> preciseness for timing computations and allows to reduce the extra dsi
>> bandwidth in burst mode (fro
Hi Andrzej,
On 01/15/2018 02:52 PM, Andrzej Hajda wrote:
> On 12.01.2018 17:25, Philippe Cornu wrote:
>> The pixel clock is optional. When available, it offers a better
>> preciseness for timing computations and allows to reduce the extra dsi
>> bandwidth in burst mode (fro
Hi Andrzej,
On 01/15/2018 10:12 AM, Andrzej Hajda wrote:
> On 12.01.2018 15:48, Philippe Cornu wrote:
>> The function mipi_dsi_device_transfer() returns the number of transmitted
>> or received bytes on success or a negative error code on failure.
>>
>> The functions m
Hi Andrzej,
On 01/15/2018 10:12 AM, Andrzej Hajda wrote:
> On 12.01.2018 15:48, Philippe Cornu wrote:
>> The function mipi_dsi_device_transfer() returns the number of transmitted
>> or received bytes on success or a negative error code on failure.
>>
>> The functions m
The pixel clock is optional. When available, it offers a better
preciseness for timing computations and allows to reduce the extra dsi
bandwidth in burst mode (from ~20% to ~10-12%, hw platform dependent).
Signed-off-by: Philippe Cornu <philippe.co...@st.com>
---
Changes in v2: Improve
The pixel clock is optional. When available, it offers a better
preciseness for timing computations and allows to reduce the extra dsi
bandwidth in burst mode (from ~20% to ~10-12%, hw platform dependent).
Signed-off-by: Philippe Cornu
---
Changes in v2: Improve px_clk probing in case of ENOENT
Add the DPI/RGB input pixel clock in mandatory properties
because it really offers a better preciseness for timing
computations.
Note: Fix also the DSI panel example where "ref" & "pclk"
clocks were swapped.
Signed-off-by: Philippe Cornu <philippe.co...@st.com>
--
Add the DPI/RGB input pixel clock in mandatory properties
because it really offers a better preciseness for timing
computations.
Note: Fix also the DSI panel example where "ref" & "pclk"
clocks were swapped.
Signed-off-by: Philippe Cornu
---
Changes in v2: put new clo
alue in case of success: 0 should be returned instead of the number of
transmitted bytes.
Signed-off-by: Philippe Cornu <philippe.co...@st.com>
---
drivers/gpu/drm/drm_mipi_dsi.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drive
alue in case of success: 0 should be returned instead of the number of
transmitted bytes.
Signed-off-by: Philippe Cornu
---
drivers/gpu/drm/drm_mipi_dsi.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
i
s by Nickey Yang,
> to make the Rockchip DSI driver wrap this common driver.
>
> Signed-off-by: Brian Norris <briannor...@chromium.org>
> Reviewed-by: Philippe Cornu <philippe.co...@st.com>
> Tested-by: Philippe Cornu <philippe.co...@st.com>
> ---
> v2:
>
s by Nickey Yang,
> to make the Rockchip DSI driver wrap this common driver.
>
> Signed-off-by: Brian Norris
> Reviewed-by: Philippe Cornu
> Tested-by: Philippe Cornu
> ---
> v2:
> * remove "dcs" naming, since these commands handle generic DSI too, not
Hi Brian,
Reviewed-by: Philippe Cornu <philippe.co...@st.com>
Many thanks,
Philippe :-)
On 01/09/2018 09:33 PM, Brian Norris wrote:
> sparse complains:
>
> drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c:703:6: warning: symbol
> 'dw_mipi_dsi_bridge_mode_set' was not declared. S
Hi Brian,
Reviewed-by: Philippe Cornu
Many thanks,
Philippe :-)
On 01/09/2018 09:33 PM, Brian Norris wrote:
> sparse complains:
>
> drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c:703:6: warning: symbol
> 'dw_mipi_dsi_bridge_mode_set' was not declared. Should it be static?
>
Hi Brian,
On 01/09/2018 07:55 PM, Brian Norris wrote:
> Hi Philippe,
>
> On Tue, Jan 09, 2018 at 10:48:43AM +, Philippe CORNU wrote:
>> Hi Brian,
>>
>> And many thanks for implementing these TODOs.
>
> And thanks for adding them; it gave me a better opti
Hi Brian,
On 01/09/2018 07:55 PM, Brian Norris wrote:
> Hi Philippe,
>
> On Tue, Jan 09, 2018 at 10:48:43AM +, Philippe CORNU wrote:
>> Hi Brian,
>>
>> And many thanks for implementing these TODOs.
>
> And thanks for adding them; it gave me a better opti
Hi Archit, Andrzej & Laurent,
Regarding this patch from Brian, I think it could be nice to merge it
(1xAcked-by, 2xReviewed-by).
Could you please have a look?
Only the small "typo" in the headline needs to be changed.
Many thanks,
Philippe :-)
On 11/28/2017 10:34 AM, Philip
Hi Archit, Andrzej & Laurent,
Regarding this patch from Brian, I think it could be nice to merge it
(1xAcked-by, 2xReviewed-by).
Could you please have a look?
Only the small "typo" in the headline needs to be changed.
Many thanks,
Philippe :-)
On 11/28/2017 10:34 AM, Philip
Hi all,
Do you think the patch is "acceptable" or should I change it somehow?
Any opinion is welcomed : )
Many thanks,
Philippe :-)
On 11/24/2017 02:54 PM, Philippe CORNU wrote:
> Hi Peter,
>
> On 11/13/2017 11:40 AM, Philippe CORNU wrote:
>> Hi Peter,
>>
>>
Hi all,
Do you think the patch is "acceptable" or should I change it somehow?
Any opinion is welcomed : )
Many thanks,
Philippe :-)
On 11/24/2017 02:54 PM, Philippe CORNU wrote:
> Hi Peter,
>
> On 11/13/2017 11:40 AM, Philippe CORNU wrote:
>> Hi Peter,
>>
>>
eate_packet(, msg);
> + if (ret) {
> + dev_err(dsi->dev, "failed to create packet: %d\n", ret);
> + return ret;
> }
>
> - return ret;
> + dw_mipi_message_config(dsi, msg);
> +
> + return dw_mipi_dsi_dcs_write(dsi, );
> }
>
> static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
>
I performed some tests tracing all DSI_GEN_HDR & DSI_GEN_PLD_DATA reg
writes with panel/panel-orisetech-otm8009a.c (using long dcs commands)
before and after your patch and this is "100% perfect"!
So, apart the un-important "dcs" in dw_mipi_dsi_dcs_write() function name:
Reviewed-by: Philippe Cornu <philippe.co...@st.com>
Tested-by: Philippe Cornu <philippe.co...@st.com>
This clean-up will help a lot to add the dsi read feature in the future.
Very good patch Brian and big "thank you" !
Philippe :-)
if (ret) {
> + dev_err(dsi->dev, "failed to create packet: %d\n", ret);
> + return ret;
> }
>
> - return ret;
> + dw_mipi_message_config(dsi, msg);
> +
> + return dw_mipi_dsi_dcs_write(dsi, );
> }
>
> static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
>
I performed some tests tracing all DSI_GEN_HDR & DSI_GEN_PLD_DATA reg
writes with panel/panel-orisetech-otm8009a.c (using long dcs commands)
before and after your patch and this is "100% perfect"!
So, apart the un-important "dcs" in dw_mipi_dsi_dcs_write() function name:
Reviewed-by: Philippe Cornu
Tested-by: Philippe Cornu
This clean-up will help a lot to add the dsi read feature in the future.
Very good patch Brian and big "thank you" !
Philippe :-)
Hi Nickey,
On 12/12/2017 02:10 AM, Nickey Yang wrote:
> From: Brian Norris
>
> Bridge drivers/helpers shouldn't be clobbering the drvdata, since a
> parent driver might need to own this. Instead, let's return our
> 'dw_mipi_dsi' object and have callers pass that back
Hi Nickey,
On 12/12/2017 02:10 AM, Nickey Yang wrote:
> From: Brian Norris
>
> Bridge drivers/helpers shouldn't be clobbering the drvdata, since a
> parent driver might need to own this. Instead, let's return our
> 'dw_mipi_dsi' object and have callers pass that back to us for removal.
>
>
Hi Brian,
On 12/06/2017 10:52 PM, Brian Norris wrote:
> Hi Nickey, others,
>
> I just want to highlight a thing or two here. Otherwise, my
> 'Reviewed-by' still basically stands (FWIW).
>
> On Wed, Dec 06, 2017 at 05:08:21PM +0800, Nickey Yang wrote:
>> Add the ROCKCHIP DSI controller driver
Hi Brian,
On 12/06/2017 10:52 PM, Brian Norris wrote:
> Hi Nickey, others,
>
> I just want to highlight a thing or two here. Otherwise, my
> 'Reviewed-by' still basically stands (FWIW).
>
> On Wed, Dec 06, 2017 at 05:08:21PM +0800, Nickey Yang wrote:
>> Add the ROCKCHIP DSI controller driver
Hi Nickey,
platform_set_drvdata() is still missing in your version.
Thanks,
Philippe :-)
On 12/06/2017 10:39 PM, Brian Norris wrote:
> On Wed, Dec 06, 2017 at 05:08:19PM +0800, Nickey Yang wrote:
>> From: Brian Norris
>>
>> Bridge drivers/helpers shouldn't be
Hi Nickey,
platform_set_drvdata() is still missing in your version.
Thanks,
Philippe :-)
On 12/06/2017 10:39 PM, Brian Norris wrote:
> On Wed, Dec 06, 2017 at 05:08:19PM +0800, Nickey Yang wrote:
>> From: Brian Norris
>>
>> Bridge drivers/helpers shouldn't be clobbering the drvdata, since a
>>
Hi Nickey,
On 12/01/2017 10:11 AM, Nickey Yang wrote:
> Hi Philippe,
>
>
> On 2017年12月01日 16:32, Philippe CORNU wrote:
>> Dear Nickey,
>>
>> Many thanks for your patch.
>>
>> I am sorry to say that but you can not add my "Acked-by"
Hi Nickey,
On 12/01/2017 10:11 AM, Nickey Yang wrote:
> Hi Philippe,
>
>
> On 2017年12月01日 16:32, Philippe CORNU wrote:
>> Dear Nickey,
>>
>> Many thanks for your patch.
>>
>> I am sorry to say that but you can not add my "Acked-by"
for removal.
>
> Signed-off-by: Brian Norris <briannor...@chromium.org>
> Signed-off-by: Nickey Yang <nickey.y...@rock-chips.com>
> Reviewed-by: Matthias Kaehlcke <m...@chromium.org>
> Reviewed-by: Archit Taneja <arch...@codeaurora.org>
> Acked-by: Philippe Cor
Brian Norris
> Signed-off-by: Nickey Yang
> Reviewed-by: Matthias Kaehlcke
> Reviewed-by: Archit Taneja
> Acked-by: Philippe Cornu
> Link:https://patchwork.kernel.org/patch/10078493/
>
> ---
> Changes in v4:
> - Add From tag,update subject line
> - keep
s cleanup.
(please update the headline with "synopsys")
Successfully tested on stm.
Acked-by: Philippe Cornu <philippe.co...@st.com>
Many thanks,
Philippe :-)
>
> Signed-off-by: Brian Norris <briannor...@chromium.org>
> ---
> drivers
s cleanup.
(please update the headline with "synopsys")
Successfully tested on stm.
Acked-by: Philippe Cornu
Many thanks,
Philippe :-)
>
> Signed-off-by: Brian Norris
> ---
> drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 36
> ++-
>
Hi Peter,
On 11/13/2017 11:40 AM, Philippe CORNU wrote:
> Hi Peter,
>
> On 11/12/2017 01:31 PM, Peter Rosin wrote:
>> On 2017-11-10 17:12, Philippe CORNU wrote:
>>> Hi Peter,
>>>
>>> On 11/07/2017 05:34 PM, Peter Rosin wrote:
>>>> On
Hi Peter,
On 11/13/2017 11:40 AM, Philippe CORNU wrote:
> Hi Peter,
>
> On 11/12/2017 01:31 PM, Peter Rosin wrote:
>> On 2017-11-10 17:12, Philippe CORNU wrote:
>>> Hi Peter,
>>>
>>> On 11/07/2017 05:34 PM, Peter Rosin wrote:
>>>> On
Hi Peter,
On 11/12/2017 01:31 PM, Peter Rosin wrote:
> On 2017-11-10 17:12, Philippe CORNU wrote:
>> Hi Peter,
>>
>> On 11/07/2017 05:34 PM, Peter Rosin wrote:
>>> On 2017-11-07 16:53, Philippe CORNU wrote:
>>>> + Peter
>>>>
>>>>
Hi Peter,
On 11/12/2017 01:31 PM, Peter Rosin wrote:
> On 2017-11-10 17:12, Philippe CORNU wrote:
>> Hi Peter,
>>
>> On 11/07/2017 05:34 PM, Peter Rosin wrote:
>>> On 2017-11-07 16:53, Philippe CORNU wrote:
>>>> + Peter
>>>>
>>>>
Hi Peter,
On 11/07/2017 05:34 PM, Peter Rosin wrote:
> On 2017-11-07 16:53, Philippe CORNU wrote:
>> + Peter
>>
>> Hi Peter,
>>
>> CLUT support on STM32 has been removed thanks to your clean up patch
>
> Support is a bit strong for what I thought w
Hi Peter,
On 11/07/2017 05:34 PM, Peter Rosin wrote:
> On 2017-11-07 16:53, Philippe CORNU wrote:
>> + Peter
>>
>> Hi Peter,
>>
>> CLUT support on STM32 has been removed thanks to your clean up patch
>
> Support is a bit strong for what I thought w
May I ask you please a short review on this patch?
Many thanks,
Philippe :-)
On 10/26/2017 01:17 PM, Philippe Cornu wrote:
> Add the 8-bit clut mode support at crtc level.
> Useful for low memory footprint user interfaces but also for
> 8-bit old games (including color shifting visual
May I ask you please a short review on this patch?
Many thanks,
Philippe :-)
On 10/26/2017 01:17 PM, Philippe Cornu wrote:
> Add the 8-bit clut mode support at crtc level.
> Useful for low memory footprint user interfaces but also for
> 8-bit old games (including color shifting visual
Hi Philipp,
On 10/27/2017 10:06 AM, Philipp Zabel wrote:
> Hi Philippe,
>
> On Thu, 2017-10-26 at 18:09 +0200, Philippe Cornu wrote:
>> The pixel clock is optional. When available, it offers a better
>> preciseness for timing computations.
>>
>> Signed-of
Hi Philipp,
On 10/27/2017 10:06 AM, Philipp Zabel wrote:
> Hi Philippe,
>
> On Thu, 2017-10-26 at 18:09 +0200, Philippe Cornu wrote:
>> The pixel clock is optional. When available, it offers a better
>> preciseness for timing computations.
>>
>> Signed-off-by: Ph
Hi Andrzej,
On 10/27/2017 08:41 AM, Andrzej Hajda wrote:
> On 26.10.2017 18:09, Philippe Cornu wrote:
>> The pixel clock is optional. When available, it offers a better
>> preciseness for timing computations.
>>
>> Signed-off-by: Philippe Cornu <philippe.co...@st.co
Hi Andrzej,
On 10/27/2017 08:41 AM, Andrzej Hajda wrote:
> On 26.10.2017 18:09, Philippe Cornu wrote:
>> The pixel clock is optional. When available, it offers a better
>> preciseness for timing computations.
>>
>> Signed-off-by: Philippe Cornu
>> ---
>>
Hi Rob,
On 10/27/2017 04:38 PM, Rob Herring wrote:
> On Thu, Oct 26, 2017 at 06:12:36PM +0200, Philippe Cornu wrote:
>> Add the DPI/RGB input pixel clock in mandatory properties
>> because it really offers a better preciseness for timing
>> computations.
>> Note: Fix
Hi Rob,
On 10/27/2017 04:38 PM, Rob Herring wrote:
> On Thu, Oct 26, 2017 at 06:12:36PM +0200, Philippe Cornu wrote:
>> Add the DPI/RGB input pixel clock in mandatory properties
>> because it really offers a better preciseness for timing
>> computations.
>> Note: Fix
Add the DPI/RGB input pixel clock in mandatory properties
because it really offers a better preciseness for timing
computations.
Note: Fix also the DSI panel example where "ref" & "pclk"
clocks were swapped.
Signed-off-by: Philippe Cornu <philippe.co...@st.com>
201 - 300 of 403 matches
Mail list logo