[PATCH v9 07/19] mtd: spi-nor: sfdp: prepare BFPT parsing for JESD216 rev D

-by: Pratyush Yadav --- drivers/mtd/spi-nor/sfdp.c | 7 ++- drivers/mtd/spi-nor/sfdp.h | 5 +++-- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c index 5cecc4ba2141..96960f2f3d7a 100644 --- a/drivers/mtd/spi-nor/sfdp.c +++ b

[PATCH v9 19/19] mtd: spi-nor: micron-st: allow using MT35XU512ABA in Octal DTR mode

reset sequence. So, add the flag in the flash's info. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/micron-st.c | 112 +++- 1 file changed, 111 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c index

[PATCH v9 18/19] mtd: spi-nor: spansion: add support for Cypress Semper flash

permanent changes to the flash configuration. The correct data to implement a fixup is not available right now and will be done in a follow-up patch if needed. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/spansion.c | 167 + 1 file changed, 167 insertions

[PATCH v9 16/19] mtd: spi-nor: core: disable Octal DTR mode on suspend.

On resume, the init procedure will be run that will re-enable it. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 68559386f6f8..63ab588299f4 100644

[PATCH v9 05/19] mtd: spi-nor: add support for DTR protocol

phases need to be either DTR or STR. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 305 drivers/mtd/spi-nor/core.h | 6 + drivers/mtd/spi-nor/sfdp.c | 9 +- include/linux/mtd/spi-nor.h | 51 -- 4 files changed, 295 insertions

[PATCH v9 09/19] mtd: spi-nor: sfdp: parse xSPI Profile 1.0 table

. Since we want to set read settings, expose spi_nor_set_read_settings() in core.h. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 2 +- drivers/mtd/spi-nor/core.h | 10 drivers/mtd/spi-nor/sfdp.c | 99 ++ 3 files changed, 110 insertions(+), 1

[PATCH v9 10/19] mtd: spi-nor: core: use dummy cycle and address width info from SFDP

The xSPI Profile 1.0 table specifies how many dummy cycles and address bytes are needed for the Read Status Register command in octal DTR mode. Use that information to send the correct Read SR command. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 25

[PATCH v9 17/19] mtd: spi-nor: core: expose spi_nor_default_setup() in core.h

the spi_nor_default_setup() in core.h to manufacturer-specific files. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 4 ++-- drivers/mtd/spi-nor/core.h | 3 +++ 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index

[PATCH v9 15/19] mtd: spi-nor: core: perform a Soft Reset on shutdown

on it. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 42 + include/linux/mtd/spi-nor.h | 2 ++ 2 files changed, 44 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index a94376344be5..68559386f6f8 100644

[PATCH v9 14/19] mtd: spi-nor: sfdp: detect Soft Reset sequence support from BFPT

A Soft Reset sequence will return the flash to Power-on-Reset (POR) state. It consists of two commands: Soft Reset Enable and Soft Reset. Find out if the sequence is supported from BFPT DWORD 16. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.h | 1 + drivers/mtd/spi-nor/sfdp.c | 4

[PATCH v9 13/19] mtd: spi-nor: sfdp: do not make invalid quad enable fatal

o abort BFPT parsing. Instead, continue BFPT parsing assuming there is no quad enable bit present. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/sfdp.c | 8 +++- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c index 052cab

[PATCH v9 08/19] mtd: spi-nor: sfdp: get command opcode extension type from BFPT

d "inverse" extensions are supported. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/sfdp.c | 17 + drivers/mtd/spi-nor/sfdp.h | 6 ++ 2 files changed, 23 insertions(+) diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c index 96960f2f3d7a.

[PATCH v9 11/19] mtd: spi-nor: core: do 2 byte reads for SR and FSR in DTR mode

Some controllers, like the cadence qspi controller, have trouble reading only 1 byte in DTR mode. So, do 2 byte reads for SR and FSR commands in DTR mode, and then discard the second byte. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 15 +-- 1 file changed, 13

[PATCH v9 02/19] spi: spi-mem: allow specifying a command's extension

se that as the buffer instead. Both these drivers would reject multi-byte opcodes in their supports_op() hook anyway, so we only need to worry about single-byte opcodes for now. The above two changes are put in this commit to keep the series bisectable. Signed-off-by: Pratyush Yadav --- drivers/sp

[PATCH v9 04/19] spi: spi-mtk-nor: reject DTR ops

Double Transfer Rate (DTR) ops are added in spi-mem. But this controller doesn't support DTR transactions. Since we don't use the default supports_op(), which rejects all DTR ops, do that explicitly in our supports_op(). Signed-off-by: Pratyush Yadav --- drivers/spi/spi-mtk-nor.c | 6 ++ 1

[PATCH v9 12/19] mtd: spi-nor: core: enable octal DTR mode when possible

Allow flashes to specify a hook to enable octal DTR mode. Use this hook whenever possible to get optimal transfer speeds. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 35 +++ drivers/mtd/spi-nor/core.h | 2 ++ 2 files changed, 37 insertions

[PATCH v9 03/19] spi: atmel-quadspi: reject DTR ops

Double Transfer Rate (DTR) ops are added in spi-mem. But this controller doesn't support DTR transactions. Since we don't use the default supports_op(), which rejects all DTR ops, do that explicitly in our supports_op(). Signed-off-by: Pratyush Yadav --- drivers/spi/atmel-quadspi.c | 6

[PATCH v9 06/19] mtd: spi-nor: sfdp: default to addr_width of 3 for configurable widths

with configurable address width. If the SMPT descriptor advertises variable address width, we use nor->addr_width as the address width. But since it was not set to any value from the SFDP table, the read command uses an address width of 0, resulting in an incorrect read being issued. Signed-off-by: Praty

[PATCH v9 00/19] mtd: spi-nor: add xSPI Octal DTR support

)' from cqspi_supports_mem_op(). This makes sure the buswidth requirements are also enforced along with the DTR requirements. - Drop the 'is_dtr' argument from spi_check_dtr_req(). We only call it when a phase is DTR so it is redundant. Pratyush Yadav (19): spi: spi-mem: allow specifying

[PATCH v9 01/19] spi: spi-mem: allow specifying whether an op is DTR or not

Each phase is given a separate 'dtr' field so mixed protocols like 4S-4D-4D can be supported. Signed-off-by: Pratyush Yadav --- drivers/spi/spi-mem.c | 3 +++ include/linux/spi/spi-mem.h | 8 2 files changed, 11 insertions(+) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi

[PATCH v8 17/19] mtd: spi-nor: core: expose spi_nor_default_setup() in core.h

the spi_nor_default_setup() in core.h to manufacturer-specific files. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 4 ++-- drivers/mtd/spi-nor/core.h | 3 +++ 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index

[PATCH v8 19/19] mtd: spi-nor: micron-st: allow using MT35XU512ABA in Octal DTR mode

reset sequence. So, add the flag in the flash's info. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/micron-st.c | 112 +++- 1 file changed, 111 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c index

[PATCH v8 07/19] mtd: spi-nor: sfdp: prepare BFPT parsing for JESD216 rev D

-by: Pratyush Yadav --- drivers/mtd/spi-nor/sfdp.c | 7 ++- drivers/mtd/spi-nor/sfdp.h | 5 +++-- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c index 5cecc4ba2141..96960f2f3d7a 100644 --- a/drivers/mtd/spi-nor/sfdp.c +++ b

[PATCH v8 10/19] mtd: spi-nor: core: use dummy cycle and address width info from SFDP

The xSPI Profile 1.0 table specifies how many dummy cycles and address bytes are needed for the Read Status Register command in octal DTR mode. Use that information to send the correct Read SR command. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 25

[PATCH v8 12/19] mtd: spi-nor: core: enable octal DTR mode when possible

Allow flashes to specify a hook to enable octal DTR mode. Use this hook whenever possible to get optimal transfer speeds. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 35 +++ drivers/mtd/spi-nor/core.h | 2 ++ 2 files changed, 37 insertions

[PATCH v8 13/19] mtd: spi-nor: sfdp: do not make invalid quad enable fatal

o abort BFPT parsing. Instead, continue BFPT parsing assuming there is no quad enable bit present. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/sfdp.c | 8 +++- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c index 052cab

[PATCH v8 18/19] mtd: spi-nor: spansion: add support for Cypress Semper flash

permanent changes to the flash configuration. The correct data to implement a fixup is not available right now and will be done in a follow-up patch if needed. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/spansion.c | 167 + 1 file changed, 167 insertions

[PATCH v8 16/19] mtd: spi-nor: core: disable Octal DTR mode on suspend.

On resume, the init procedure will be run that will re-enable it. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 68559386f6f8..63ab588299f4 100644

[PATCH v8 08/19] mtd: spi-nor: sfdp: get command opcode extension type from BFPT

d "inverse" extensions are supported. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/sfdp.c | 17 + drivers/mtd/spi-nor/sfdp.h | 6 ++ 2 files changed, 23 insertions(+) diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c index 96960f2f3d7a.

[PATCH v8 09/19] mtd: spi-nor: sfdp: parse xSPI Profile 1.0 table

. Since we want to set read settings, expose spi_nor_set_read_settings() in core.h. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 2 +- drivers/mtd/spi-nor/core.h | 10 drivers/mtd/spi-nor/sfdp.c | 99 ++ 3 files changed, 110 insertions(+), 1

[PATCH v8 11/19] mtd: spi-nor: core: do 2 byte reads for SR and FSR in DTR mode

Some controllers, like the cadence qspi controller, have trouble reading only 1 byte in DTR mode. So, do 2 byte reads for SR and FSR commands in DTR mode, and then discard the second byte. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 15 +-- 1 file changed, 13

[PATCH v8 15/19] mtd: spi-nor: core: perform a Soft Reset on shutdown

on it. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 42 + include/linux/mtd/spi-nor.h | 2 ++ 2 files changed, 44 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index a94376344be5..68559386f6f8 100644

[PATCH v8 14/19] mtd: spi-nor: sfdp: detect Soft Reset sequence support from BFPT

A Soft Reset sequence will return the flash to Power-on-Reset (POR) state. It consists of two commands: Soft Reset Enable and Soft Reset. Find out if the sequence is supported from BFPT DWORD 16. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.h | 1 + drivers/mtd/spi-nor/sfdp.c | 4

[PATCH v8 03/19] spi: atmel-quadspi: reject DTR ops

Double Transfer Rate (DTR) ops are added in spi-mem. But this controller doesn't support DTR transactions. Since we don't use the default supports_op(), which rejects all DTR ops, do that explicitly in our supports_op(). Signed-off-by: Pratyush Yadav --- drivers/spi/atmel-quadspi.c | 6

[PATCH v8 05/19] mtd: spi-nor: add support for DTR protocol

phases need to be either DTR or STR. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 305 drivers/mtd/spi-nor/core.h | 6 + drivers/mtd/spi-nor/sfdp.c | 9 +- include/linux/mtd/spi-nor.h | 51 -- 4 files changed, 295 insertions

[PATCH v8 02/19] spi: spi-mem: allow specifying a command's extension

se that as the buffer instead. Both these drivers would reject multi-byte opcodes in their supports_op() hook anyway, so we only need to worry about single-byte opcodes for now. The above two changes are put in this commit to keep the series bisectable. Signed-off-by: Pratyush Yadav --- drivers/sp

[PATCH v8 06/19] mtd: spi-nor: sfdp: default to addr_width of 3 for configurable widths

with configurable address width. If the SMPT descriptor advertises variable address width, we use nor->addr_width as the address width. But since it was not set to any value from the SFDP table, the read command uses an address width of 0, resulting in an incorrect read being issued. Signed-off-by: Praty

[PATCH v8 01/19] spi: spi-mem: allow specifying whether an op is DTR or not

Each phase is given a separate 'dtr' field so mixed protocols like 4S-4D-4D can be supported. Signed-off-by: Pratyush Yadav --- drivers/spi/spi-mem.c | 3 +++ include/linux/spi/spi-mem.h | 8 2 files changed, 11 insertions(+) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi

[PATCH v8 04/19] spi: spi-mtk-nor: reject DTR ops

Double Transfer Rate (DTR) ops are added in spi-mem. But this controller doesn't support DTR transactions. Since we don't use the default supports_op(), which rejects all DTR ops, do that explicitly in our supports_op(). Signed-off-by: Pratyush Yadav --- drivers/spi/spi-mtk-nor.c | 6 ++ 1

[PATCH v8 00/19] mtd: spi-nor: add xSPI Octal DTR support

orts_op()' from cqspi_supports_mem_op(). This makes sure the buswidth requirements are also enforced along with the DTR requirements. - Drop the 'is_dtr' argument from spi_check_dtr_req(). We only call it when a phase is DTR so it is redundant. Pratyush Yadav (19): spi: spi-mem: allow specif

Re: [PATCH v7 02/20] spi: spi-mem: allow specifying a command's extension

On 22/05/20 05:32PM, Boris Brezillon wrote: > On Fri, 22 May 2020 15:42:43 +0530 > Pratyush Yadav wrote: > > > In xSPI mode, flashes expect 2-byte opcodes. The second byte is called > > the "command extension". There can be 3 types of extensions in xSPI: &g

Re: [PATCH v6 04/19] spi: spi-mem: allow specifying a command's extension

Hi Boris, On 21/05/20 08:22PM, Boris Brezillon wrote: > On Wed, 20 May 2020 22:00:38 +0530 > Pratyush Yadav wrote: > > As mentioned in one of my previous review, you should patch the mxic > driver before extending the opcode field: > > --->8--- > diff --git a/drive

Re: [PATCH v5 01/19] spi: spi-mem: allow specifying whether an op is DTR or not

allow specifying whether an op is DTR or > not > > > > Each phase is given a separate 'dtr' field so mixed protocols like > > 4S-4D-4D can be supported. > > > > Signed-off-by: Pratyush Yadav > > --- > > drivers/spi/spi-mem.c | 3 +++ >

[PATCH v7 17/20] mtd: spi-nor: core: disable Octal DTR mode on suspend.

On resume, the init procedure will be run that will re-enable it. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 68559386f6f8..63ab588299f4 100644

[PATCH v7 15/20] mtd: spi-nor: sfdp: detect Soft Reset sequence support from BFPT

A Soft Reset sequence will return the flash to Power-on-Reset (POR) state. It consists of two commands: Soft Reset Enable and Soft Reset. Find out if the sequence is supported from BFPT DWORD 16. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.h | 1 + drivers/mtd/spi-nor/sfdp.c | 4

[PATCH v7 20/20] mtd: spi-nor: micron-st: allow using MT35XU512ABA in Octal DTR mode

reset sequence. So, add the flag in the flash's info. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/micron-st.c | 112 +++- 1 file changed, 111 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c index

[PATCH v7 18/20] mtd: spi-nor: core: expose spi_nor_default_setup() in core.h

the spi_nor_default_setup() in core.h to manufacturer-specific files. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 4 ++-- drivers/mtd/spi-nor/core.h | 3 +++ 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index

[PATCH v7 13/20] mtd: spi-nor: core: enable octal DTR mode when possible

Allow flashes to specify a hook to enable octal DTR mode. Use this hook whenever possible to get optimal transfer speeds. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 35 +++ drivers/mtd/spi-nor/core.h | 2 ++ 2 files changed, 37 insertions

[PATCH v7 19/20] mtd: spi-nor: spansion: add support for Cypress Semper flash

permanent changes to the flash configuration. The correct data to implement a fixup is not available right now and will be done in a follow-up patch if needed. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/spansion.c | 167 + 1 file changed, 167 insertions

[PATCH v7 14/20] mtd: spi-nor: sfdp: do not make invalid quad enable fatal

o abort BFPT parsing. Instead, continue BFPT parsing assuming there is no quad enable bit present. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/sfdp.c | 8 +++- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c index 052cab

[PATCH v7 05/20] spi: mxic: Avoid endianness problems with 2-byte opcodes

Signed-off-by: Pratyush Yadav --- drivers/spi/spi-mxic.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c index 69491f3a515d..c3f4136a7c1d 100644 --- a/drivers/spi/spi-mxic.c +++ b/drivers/spi/spi-mxic.c @@ -356,6 +356,7

[PATCH v7 16/20] mtd: spi-nor: core: perform a Soft Reset on shutdown

on it. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 42 + include/linux/mtd/spi-nor.h | 2 ++ 2 files changed, 44 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index a94376344be5..68559386f6f8 100644

[PATCH v7 09/20] mtd: spi-nor: sfdp: get command opcode extension type from BFPT

d "inverse" extensions are supported. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/sfdp.c | 17 + drivers/mtd/spi-nor/sfdp.h | 6 ++ 2 files changed, 23 insertions(+) diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c index 96960f2f3d7a.

[PATCH v7 07/20] mtd: spi-nor: sfdp: default to addr_width of 3 for configurable widths

with configurable address width. If the SMPT descriptor advertises variable address width, we use nor->addr_width as the address width. But since it was not set to any value from the SFDP table, the read command uses an address width of 0, resulting in an incorrect read being issued. Signed-off-by: Praty

[PATCH v7 06/20] mtd: spi-nor: add support for DTR protocol

phases need to be either DTR or STR. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 305 drivers/mtd/spi-nor/core.h | 6 + drivers/mtd/spi-nor/sfdp.c | 9 +- include/linux/mtd/spi-nor.h | 51 -- 4 files changed, 295 insertions

[PATCH v7 08/20] mtd: spi-nor: sfdp: prepare BFPT parsing for JESD216 rev D

-by: Pratyush Yadav --- drivers/mtd/spi-nor/sfdp.c | 7 ++- drivers/mtd/spi-nor/sfdp.h | 5 +++-- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c index 5cecc4ba2141..96960f2f3d7a 100644 --- a/drivers/mtd/spi-nor/sfdp.c +++ b

[PATCH v7 00/20] mtd: spi-nor: add xSPI Octal DTR support

s. - Call the default 'supports_op()' from cqspi_supports_mem_op(). This makes sure the buswidth requirements are also enforced along with the DTR requirements. - Drop the 'is_dtr' argument from spi_check_dtr_req(). We only call it when a phase is DTR so it is redundant. Pratyush Yadav (20): spi:

[PATCH v7 04/20] spi: spi-mtk-nor: reject DTR ops

Double Transfer Rate (DTR) ops are added in spi-mem. But this controller doesn't support DTR transactions. Since we don't use the default supports_op(), which rejects all DTR ops, do that explicitly in our supports_op(). Signed-off-by: Pratyush Yadav --- drivers/spi/spi-mtk-nor.c | 6 ++ 1

[PATCH v7 03/20] spi: atmel-quadspi: reject DTR ops

Double Transfer Rate (DTR) ops are added in spi-mem. But this controller doesn't support DTR transactions. Since we don't use the default supports_op(), which rejects all DTR ops, do that explicitly in our supports_op(). Signed-off-by: Pratyush Yadav --- drivers/spi/atmel-quadspi.c | 6

[PATCH v7 12/20] mtd: spi-nor: core: do 2 byte reads for SR and FSR in DTR mode

Some controllers, like the cadence qspi controller, have trouble reading only 1 byte in DTR mode. So, do 2 byte reads for SR and FSR commands in DTR mode, and then discard the second byte. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 15 +-- 1 file changed, 13

[PATCH v7 02/20] spi: spi-mem: allow specifying a command's extension

e is the inverse of the opcode. When it is "hex" an additional opcode byte based is sent with the command whose value can be anything. So, make opcode a 16-bit value and add a 'nbytes', similar to how multiple address widths are handled. Signed-off-by: Pratyush Yadav --- drivers/spi/

[PATCH v7 01/20] spi: spi-mem: allow specifying whether an op is DTR or not

Each phase is given a separate 'dtr' field so mixed protocols like 4S-4D-4D can be supported. Signed-off-by: Pratyush Yadav --- drivers/spi/spi-mem.c | 3 +++ include/linux/spi/spi-mem.h | 8 2 files changed, 11 insertions(+) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi

[PATCH v7 10/20] mtd: spi-nor: sfdp: parse xSPI Profile 1.0 table

. Since we want to set read settings, expose spi_nor_set_read_settings() in core.h. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 2 +- drivers/mtd/spi-nor/core.h | 10 drivers/mtd/spi-nor/sfdp.c | 99 ++ 3 files changed, 110 insertions(+), 1

[PATCH v7 11/20] mtd: spi-nor: core: use dummy cycle and address width info from SFDP

The xSPI Profile 1.0 table specifies how many dummy cycles and address bytes are needed for the Read Status Register command in octal DTR mode. Use that information to send the correct Read SR command. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 25

Re: [PATCH v5 05/19] mtd: spi-nor: add support for DTR protocol

= op->data.dtr = true; > > + > > + /* 2 bytes per clock cycle in DTR mode. */ > > + op->dummy.nbytes *= 2; > > } > > > + > > + ext = spi_nor_get_cmd_ext(nor, op); > > + op->cmd.opcode = (op->cmd.opcode << 8) | ext; > > + op->cmd.nbytes = 2; > > + } > > +} > > + -- Regards, Pratyush Yadav Texas Instruments India

Re: [PATCH v6 04/19] spi: spi-mem: allow specifying a command's extension

On 22/05/20 01:11AM, Pratyush Yadav wrote: > On 21/05/20 08:22PM, Boris Brezillon wrote: > > On Wed, 20 May 2020 22:00:38 +0530 > > Pratyush Yadav wrote: > > > > > In xSPI mode, flashes expect 2-byte opcodes. The second byte is called > > > the &q

Re: [PATCH v6 04/19] spi: spi-mem: allow specifying a command's extension

On 21/05/20 08:22PM, Boris Brezillon wrote: > On Wed, 20 May 2020 22:00:38 +0530 > Pratyush Yadav wrote: > > > In xSPI mode, flashes expect 2-byte opcodes. The second byte is called > > the "command extension". There can be 3 types of extensions in xSPI: &g

Re: [PATCH v6 00/19] mtd: spi-nor: add xSPI Octal DTR support

Hi Mark, On 21/05/20 05:39PM, Mark Brown wrote: > On Wed, May 20, 2020 at 10:00:34PM +0530, Pratyush Yadav wrote: > > Hi, > > > > This series adds support for octal DTR flashes in the spi-nor framework, > > and then adds hooks for the Cypress Semper and Mircom Xcella f

Re: [PATCH v5 05/19] mtd: spi-nor: add support for DTR protocol

t shouldn't be called RDWR. > more precisely and clearly ? > > thanks, > Mason > -- Regards, Pratyush Yadav Texas Instruments India

Re: [PATCH v5 09/19] mtd: spi-nor: sfdp: parse xSPI Profile 1.0 table

or later usage. > > A device supports xSPI profile table could work in either 8S-8S-8S or > 8D-8D-8D mode. > It seems to setup these parameters somewhere out here is betters. As far as I know, the Profile 1.0 table only describes 8D-8D-8D mode. I see no mention of 8S-8S-8S in JESD251 or JESD216D.01. No field in the table describes anything related to 8S. In fact, searching for "8S" in the JESD251 spec yields 0 results. Anyway, you should set up 8S parameters in SNOR_CMD_READ_8_8_8, not SNOR_CMD_READ_8_8_8_DTR. 8D configuration is independent of 8S configuration. PS: If you have any more comments, please send them now. The merge window is getting close, and I'd like to see this make it in. -- Regards, Pratyush Yadav Texas Instruments India

[PATCH v6 18/19] mtd: spi-nor: spansion: add support for Cypress Semper flash

permanent changes to the flash configuration. The correct data to implement a fixup is not available right now and will be done in a follow-up patch if needed. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/spansion.c | 167 + 1 file changed, 167 insertions

[PATCH v6 19/19] mtd: spi-nor: micron-st: allow using MT35XU512ABA in Octal DTR mode

reset sequence. So, add the flag in the flash's info. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/micron-st.c | 112 +++- 1 file changed, 111 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c index

[PATCH v6 17/19] mtd: spi-nor: core: expose spi_nor_default_setup() in core.h

the spi_nor_default_setup() in core.h to manufacturer-specific files. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 4 ++-- drivers/mtd/spi-nor/core.h | 3 +++ 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index

[PATCH v6 15/19] mtd: spi-nor: core: perform a Soft Reset on shutdown

on it. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 42 + include/linux/mtd/spi-nor.h | 2 ++ 2 files changed, 44 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index a94376344be5..68559386f6f8 100644

[PATCH v6 16/19] mtd: spi-nor: core: disable Octal DTR mode on suspend.

On resume, the init procedure will be run that will re-enable it. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 68559386f6f8..63ab588299f4 100644

[PATCH v6 13/19] mtd: spi-nor: sfdp: do not make invalid quad enable fatal

o abort BFPT parsing. Instead, continue BFPT parsing assuming there is no quad enable bit present. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/sfdp.c | 8 +++- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c index 052cab

[PATCH v6 14/19] mtd: spi-nor: sfdp: detect Soft Reset sequence support from BFPT

A Soft Reset sequence will return the flash to Power-on-Reset (POR) state. It consists of two commands: Soft Reset Enable and Soft Reset. Find out if the sequence is supported from BFPT DWORD 16. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.h | 1 + drivers/mtd/spi-nor/sfdp.c | 4

[PATCH v6 12/19] mtd: spi-nor: core: enable octal DTR mode when possible

Allow flashes to specify a hook to enable octal DTR mode. Use this hook whenever possible to get optimal transfer speeds. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 35 +++ drivers/mtd/spi-nor/core.h | 2 ++ 2 files changed, 37 insertions

[PATCH v6 01/19] spi: spi-mem: allow specifying whether an op is DTR or not

Each phase is given a separate 'dtr' field so mixed protocols like 4S-4D-4D can be supported. Signed-off-by: Pratyush Yadav --- drivers/spi/spi-mem.c | 3 +++ include/linux/spi/spi-mem.h | 8 2 files changed, 11 insertions(+) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi

[PATCH v6 05/19] mtd: spi-nor: add support for DTR protocol

phases need to be either DTR or STR. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 305 drivers/mtd/spi-nor/core.h | 6 + drivers/mtd/spi-nor/sfdp.c | 9 +- include/linux/mtd/spi-nor.h | 51 -- 4 files changed, 295 insertions

[PATCH v6 10/19] mtd: spi-nor: core: use dummy cycle and address width info from SFDP

The xSPI Profile 1.0 table specifies how many dummy cycles and address bytes are needed for the Read Status Register command in octal DTR mode. Use that information to send the correct Read SR command. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 25

[PATCH v6 07/19] mtd: spi-nor: sfdp: prepare BFPT parsing for JESD216 rev D

-by: Pratyush Yadav --- drivers/mtd/spi-nor/sfdp.c | 7 ++- drivers/mtd/spi-nor/sfdp.h | 5 +++-- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c index 5cecc4ba2141..96960f2f3d7a 100644 --- a/drivers/mtd/spi-nor/sfdp.c +++ b

[PATCH v6 02/19] spi: atmel-quadspi: reject DTR ops

Double Transfer Rate (DTR) ops are added in spi-mem. But this controller doesn't support DTR transactions. Since we don't use the default supports_op(), which rejects all DTR ops, do that explicitly in our supports_op(). Signed-off-by: Pratyush Yadav --- drivers/spi/atmel-quadspi.c | 4 1

[PATCH v6 09/19] mtd: spi-nor: sfdp: parse xSPI Profile 1.0 table

. Since we want to set read settings, expose spi_nor_set_read_settings() in core.h. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 2 +- drivers/mtd/spi-nor/core.h | 10 drivers/mtd/spi-nor/sfdp.c | 99 ++ 3 files changed, 110 insertions(+), 1

[PATCH v6 11/19] mtd: spi-nor: core: do 2 byte reads for SR and FSR in DTR mode

Some controllers, like the cadence qspi controller, have trouble reading only 1 byte in DTR mode. So, do 2 byte reads for SR and FSR commands in DTR mode, and then discard the second byte. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 15 +-- 1 file changed, 13

[PATCH v6 08/19] mtd: spi-nor: sfdp: get command opcode extension type from BFPT

d "inverse" extensions are supported. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/sfdp.c | 17 + drivers/mtd/spi-nor/sfdp.h | 6 ++ 2 files changed, 23 insertions(+) diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c index 96960f2f3d7a.

[PATCH v6 04/19] spi: spi-mem: allow specifying a command's extension

e is the inverse of the opcode. When it is "hex" an additional opcode byte based is sent with the command whose value can be anything. So, make opcode a 16-bit value and add a 'nbytes', similar to how multiple address widths are handled. Signed-off-by: Pratyush Yadav --- include/linux

[PATCH v6 06/19] mtd: spi-nor: sfdp: default to addr_width of 3 for configurable widths

with configurable address width. If the SMPT descriptor advertises variable address width, we use nor->addr_width as the address width. But since it was not set to any value from the SFDP table, the read command uses an address width of 0, resulting in an incorrect read being issued. Signed-off-by: Praty

[PATCH v6 00/19] mtd: spi-nor: add xSPI Octal DTR support

s_op()' from cqspi_supports_mem_op(). This makes sure the buswidth requirements are also enforced along with the DTR requirements. - Drop the 'is_dtr' argument from spi_check_dtr_req(). We only call it when a phase is DTR so it is redundant. Pratyush Yadav (19): spi: spi-mem: allow specify

[PATCH v6 03/19] spi: spi-mtk-nor: reject DTR ops

Double Transfer Rate (DTR) ops are added in spi-mem. But this controller doesn't support DTR transactions. Since we don't use the default supports_op(), which rejects all DTR ops, do that explicitly in our supports_op(). Signed-off-by: Pratyush Yadav --- drivers/spi/spi-mtk-nor.c | 4 1

Re: [PATCH v5 09/19] mtd: spi-nor: sfdp: parse xSPI Profile 1.0 table

BFPT tells us the > > maximum speed of the flash based on if Data Strobe is being used. The > > controller can also drive it slower than the maximum. And it can drive > > it with or without DS. > > This is for flash, not every Octal flash could work in 200MHz, > The Max operation speeds for other Octal Flash is 100, 133 , or 166MHz. > > If a specific Octal Flash could work in 166MHz(Max), and driver setup the > correct 16 dummy cycles for it rather than 20 dummy cycles. > it's for performance concern. Agreed. Like I mentioned in the next paragraph, will fix. > > > > So, we have to be conservative and just use the dummy cycles for the > > maximum speed so we can at least make sure the flash works, albeit at > > slightly less efficiency. I hard-coded it to 20 but I suppose we can > > find it out from the Profile 1.0 table and use that (though we'd have to > > > round it to an even value to avoid tripping up controllers). Will fix in > > > next version (or, Tudor if you're fine with fixup! patches, I can send > > that too because I suspect it will be a small change). > > -- Regards, Pratyush Yadav Texas Instruments India

Re: [PATCH v5 09/19] mtd: spi-nor: sfdp: parse xSPI Profile 1.0 table

dummy address > bytes. > > +*/ > > + if (table[0] & PROFILE1_DWORD1_RDSR_DUMMY) > > + params->rdsr_dummy = 8; > > + else > > + params->rdsr_dummy = 4; > > + > > + if (table[0] & PROFILE1_DWORD1_RDSR_ADDR_BYTES) > > + params->rdsr_addr_nbytes = 4; > > + else > > + params->rdsr_addr_nbytes = 0; > > + > > +out: > > + kfree(table); > > + return ret; > > +} > > + > -- Regards, Pratyush Yadav Texas Instruments India

[PATCH v5 17/19] mtd: spi-nor: core: expose spi_nor_default_setup() in core.h

the spi_nor_default_setup() in core.h to manufacturer-specific files. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 4 ++-- drivers/mtd/spi-nor/core.h | 3 +++ 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index

[PATCH v5 18/19] mtd: spi-nor: spansion: add support for Cypress Semper flash

permanent changes to the flash configuration. The correct data to implement a fixup is not available right now and will be done in a follow-up patch if needed. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/spansion.c | 167 + 1 file changed, 167 insertions

[PATCH v5 16/19] mtd: spi-nor: core: disable Octal DTR mode on suspend.

On resume, the init procedure will be run that will re-enable it. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 68559386f6f8..63ab588299f4 100644

[PATCH v5 15/19] mtd: spi-nor: core: perform a Soft Reset on shutdown

on it. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 42 + include/linux/mtd/spi-nor.h | 2 ++ 2 files changed, 44 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index a94376344be5..68559386f6f8 100644

[PATCH v5 14/19] mtd: spi-nor: sfdp: detect Soft Reset sequence support from BFPT

A Soft Reset sequence will return the flash to Power-on-Reset (POR) state. It consists of two commands: Soft Reset Enable and Soft Reset. Find out if the sequence is supported from BFPT DWORD 16. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.h | 1 + drivers/mtd/spi-nor/sfdp.c | 4

[PATCH v5 19/19] mtd: spi-nor: micron-st: allow using MT35XU512ABA in Octal DTR mode

reset sequence. So, add the flag in the flash's info. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/micron-st.c | 112 +++- 1 file changed, 111 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c index

[PATCH v5 04/19] spi: spi-mem: allow specifying a command's extension

e is the inverse of the opcode. When it is "hex" an additional opcode byte based is sent with the command whose value can be anything. So, make opcode a 16-bit value and add a 'nbytes', similar to how multiple address widths are handled. Signed-off-by: Pratyush Yadav --- include/linux

[PATCH v5 05/19] mtd: spi-nor: add support for DTR protocol

phases need to be either DTR or STR. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 305 drivers/mtd/spi-nor/core.h | 6 + drivers/mtd/spi-nor/sfdp.c | 9 +- include/linux/mtd/spi-nor.h | 51 -- 4 files changed, 295 insertions

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