Enabling clocks through the init_table mechanism is deprecated. Clocks
that need to be enabled early and stay on should be marked as CRITICAL.
Signed-off-by: Rhyland Klein <rkl...@nvidia.com>
---
drivers/clk/tegra/clk.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/clk
Enabling clocks through the init_table mechanism is deprecated. Clocks
that need to be enabled early and stay on should be marked as CRITICAL.
Signed-off-by: Rhyland Klein
---
drivers/clk/tegra/clk.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/clk/tegra/clk.c b/drivers/clk
to be able to easily tell what clks are CRITICAL
through the table.
I added a warning for using the init_table to enable clks. I considered
removing it entirely, but I thought phasing it out might be better.
Rhyland Klein (11):
clk: tegra: Switch to using critical clks
clk: tegra20: Mark required clks
Remove entries from the init_table where the clks are now defined
as CRITICAL clks, if we were only enabling them in the init_table.
Remove the flag to signal to enable CRITICAL clks if they are still
needed in the init_table to set other properties.
Signed-off-by: Rhyland Klein <
Remove entries from the init_table where the clks are now defined
as CRITICAL clks, if we were only enabling them in the init_table.
Remove the flag to signal to enable CRITICAL clks if they are still
needed in the init_table to set other properties.
Signed-off-by: Rhyland Klein
---
drivers
to be able to easily tell what clks are CRITICAL
through the table.
I added a warning for using the init_table to enable clks. I considered
removing it entirely, but I thought phasing it out might be better.
Rhyland Klein (11):
clk: tegra: Switch to using critical clks
clk: tegra20: Mark required clks
On 5/12/2016 1:52 PM, Laxman Dewangan wrote:
>
> On Thursday 12 May 2016 11:15 PM, Rhyland Klein wrote:
>> When configuring FPS during probe, assuming a DT node is present for
>> FPS, the code can run into a problem with the switch statements in
>
On 5/12/2016 1:52 PM, Laxman Dewangan wrote:
>
> On Thursday 12 May 2016 11:15 PM, Rhyland Klein wrote:
>> When configuring FPS during probe, assuming a DT node is present for
>> FPS, the code can run into a problem with the switch statements in
>
version:
define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
which matches the Tegra124 TRM register definition.
Signed-off-by: Andrew Bresticker <abres...@chromium.org>
[rklein: Merged in some later fixes for potential deadlocks]
Signed-off-by: Rhyland Klein <rkl...
n:
define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
which matches the Tegra124 TRM register definition.
Signed-off-by: Andrew Bresticker
[rklein: Merged in some later fixes for potential deadlocks]
Signed-off-by: Rhyland Klein
---
v5:
- Initialized flags to 0 to avoid harmless spinlock warni
ort is
less in mainline and some clks might not be requested then
Signed-off-by: Rhyland Klein <rkl...@nvidia.com>
---
drivers/clk/tegra/clk-tegra-periph.c | 21 ++---
drivers/clk/tegra/clk-tegra-super-gen4.c | 12 +++-
2 files changed, 21 insertions(+), 12 deletions
Mark clks that are required to be on as CRITICAL clks.
Signed-off-by: Rhyland Klein <rkl...@nvidia.com>
---
drivers/clk/tegra/clk-tegra20.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
ort is
less in mainline and some clks might not be requested then
Signed-off-by: Rhyland Klein
---
drivers/clk/tegra/clk-tegra-periph.c | 21 ++---
drivers/clk/tegra/clk-tegra-super-gen4.c | 12 +++-
2 files changed, 21 insertions(+), 12 deletions(-)
diff --git a/drivers/
Mark clks that are required to be on as CRITICAL clks.
Signed-off-by: Rhyland Klein
---
drivers/clk/tegra/clk-tegra20.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 837e5cbd60e9
Remove entries from the init_table where the clks are now defined
as CRITICAL clks, if we were only enabling them in the init_table.
Remove the flag to signal to enable CRITICAL clks if they are still
needed in the init_table to set other properties.
Signed-off-by: Rhyland Klein <
Remove entries from the init_table where the clks are now defined
as CRITICAL clks, if we were only enabling them in the init_table.
Remove the flag to signal to enable CRITICAL clks if they are still
needed in the init_table to set other properties.
Signed-off-by: Rhyland Klein
---
drivers
Remove entries from the init_table where the clks are now defined
as CRITICAL clks, if we were only enabling them in the init_table.
Remove the flag to signal to enable CRITICAL clks if they are still
needed in the init_table to set other properties.
Signed-off-by: Rhyland Klein <
Remove entries from the init_table where the clks are now defined
as CRITICAL clks, if we were only enabling them in the init_table.
Remove the flag to signal to enable CRITICAL clks if they are still
needed in the init_table to set other properties.
Signed-off-by: Rhyland Klein
---
drivers
Remove entries from the init_table where the clks are now defined
as CRITICAL clks, if we were only enabling them in the init_table.
Remove the flag to signal to enable CRITICAL clks if they are still
needed in the init_table to set other properties.
Signed-off-by: Rhyland Klein <
Remove entries from the init_table where the clks are now defined
as CRITICAL clks, if we were only enabling them in the init_table.
Remove the flag to signal to enable CRITICAL clks if they are still
needed in the init_table to set other properties.
Signed-off-by: Rhyland Klein <
Remove entries from the init_table where the clks are now defined
as CRITICAL clks, if we were only enabling them in the init_table.
Remove the flag to signal to enable CRITICAL clks if they are still
needed in the init_table to set other properties.
Signed-off-by: Rhyland Klein
---
drivers
Remove entries from the init_table where the clks are now defined
as CRITICAL clks, if we were only enabling them in the init_table.
Remove the flag to signal to enable CRITICAL clks if they are still
needed in the init_table to set other properties.
Signed-off-by: Rhyland Klein
---
drivers
Remove entries from the init_table where the clks are now defined
as CRITICAL clks, if we were only enabling them in the init_table.
Remove the flag to signal to enable CRITICAL clks if they are still
needed in the init_table to set other properties.
Signed-off-by: Rhyland Klein <
Remove entries from the init_table where the clks are now defined
as CRITICAL clks, if we were only enabling them in the init_table.
Remove the flag to signal to enable CRITICAL clks if they are still
needed in the init_table to set other properties.
Signed-off-by: Rhyland Klein
---
drivers
Mark clks that are required to be on as CRITICAL clks.
Signed-off-by: Rhyland Klein <rkl...@nvidia.com>
---
drivers/clk/tegra/clk-tegra210.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index b85518
Enabling clocks through the init_table mechanism is deprecated. Clocks
that need to be enabled early and stay on should be marked as CRITICAL.
Signed-off-by: Rhyland Klein <rkl...@nvidia.com>
---
drivers/clk/tegra/clk.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/clk
Mark the required clks as critical so the core will enable them during
registration and therefore they will stay on.
Signed-off-by: Rhyland Klein <rkl...@nvidia.com>
---
drivers/clk/tegra/clk-tegra30.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drive
Mark clks that are required to be on as CRITICAL clks.
Signed-off-by: Rhyland Klein
---
drivers/clk/tegra/clk-tegra210.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index b8551813ec43..156dc8ec6bf6
Enabling clocks through the init_table mechanism is deprecated. Clocks
that need to be enabled early and stay on should be marked as CRITICAL.
Signed-off-by: Rhyland Klein
---
drivers/clk/tegra/clk.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/clk/tegra/clk.c b/drivers/clk
Mark the required clks as critical so the core will enable them during
registration and therefore they will stay on.
Signed-off-by: Rhyland Klein
---
drivers/clk/tegra/clk-tegra30.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra30
Add a '^' character to the beginning of clk entries that are for
CRITICAL clks.
Signed-off-by: Rhyland Klein <rkl...@nvidia.com>
---
drivers/clk/clk.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 874c7dd8ef66..22dd0c
Add a '^' character to the beginning of clk entries that are for
CRITICAL clks.
Signed-off-by: Rhyland Klein
---
drivers/clk/clk.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 874c7dd8ef66..22dd0ca1e491 100644
to be able to easily tell what clks are CRITICAL
through the table.
I added a warning for using the init_table to enable clks. I considered
removing it entirely, but I thought phasing it out might be better.
Rhyland Klein (11):
clk: tegra: Switch to using critical/handoff clks
clk: tegra20: Mark
to be able to easily tell what clks are CRITICAL
through the table.
I added a warning for using the init_table to enable clks. I considered
removing it entirely, but I thought phasing it out might be better.
Rhyland Klein (11):
clk: tegra: Switch to using critical/handoff clks
clk: tegra20: Mark
On 5/25/2016 1:26 PM, Jon Hunter wrote:
>
> On 25/05/16 17:36, Rhyland Klein wrote:
>
> ...
>
>> I can see that getting the temperature could work. I would point out
>> that I don't see any recent changes to bq27xxx or the power_supply_core
>> that would imp
On 5/25/2016 1:26 PM, Jon Hunter wrote:
>
> On 25/05/16 17:36, Rhyland Klein wrote:
>
> ...
>
>> I can see that getting the temperature could work. I would point out
>> that I don't see any recent changes to bq27xxx or the power_supply_core
>> that would imp
On 5/25/2016 12:29 PM, Jon Hunter wrote:
>
> On 25/05/16 17:10, Jon Hunter wrote:
>
> ...
>
>> So power_supply_read_temp() calls ->get_property() and passes the
>> power_supply psy struct which is initialised. The problem is that inside
>> the bq27xxx driver, this then kicks off the worker
On 5/25/2016 12:29 PM, Jon Hunter wrote:
>
> On 25/05/16 17:10, Jon Hunter wrote:
>
> ...
>
>> So power_supply_read_temp() calls ->get_property() and passes the
>> power_supply psy struct which is initialised. The problem is that inside
>> the bq27xxx driver, this then kicks off the worker
On 5/25/2016 11:46 AM, Thierry Reding wrote:
> On Wed, May 25, 2016 at 12:03:47PM +0100, Jon Hunter wrote:
>>
>> On 25/05/16 11:58, Jon Hunter wrote:
>>
>> ...
>>
>>> Looking at this a bit more I am wondering if we should prevent the
>>> battery for being polled before the registration has
On 5/25/2016 11:46 AM, Thierry Reding wrote:
> On Wed, May 25, 2016 at 12:03:47PM +0100, Jon Hunter wrote:
>>
>> On 25/05/16 11:58, Jon Hunter wrote:
>>
>> ...
>>
>>> Looking at this a bit more I am wondering if we should prevent the
>>> battery for being polled before the registration has
On 5/25/2016 7:03 AM, Jon Hunter wrote:
>
> On 25/05/16 11:58, Jon Hunter wrote:
>
> ...
I am aware of the splat, and I was considering the proper place for
working around that.
>
>> Looking at this a bit more I am wondering if we should prevent the
>> battery for being polled before the
On 5/25/2016 7:03 AM, Jon Hunter wrote:
>
> On 25/05/16 11:58, Jon Hunter wrote:
>
> ...
I am aware of the splat, and I was considering the proper place for
working around that.
>
>> Looking at this a bit more I am wondering if we should prevent the
>> battery for being polled before the
On 5/24/2016 10:09 AM, Jon Hunter wrote:
> Hi Rhyland,
>
> On 03/05/16 16:45, Rhyland Klein wrote:
>> Enable the ChromeOS Embedded Controller, its I2C tunnel driver, and
>> the BA27XXX battery driver. These are all used on the Tegra210 Smaug
>> platform.
>>
>
On 5/24/2016 10:09 AM, Jon Hunter wrote:
> Hi Rhyland,
>
> On 03/05/16 16:45, Rhyland Klein wrote:
>> Enable the ChromeOS Embedded Controller, its I2C tunnel driver, and
>> the BA27XXX battery driver. These are all used on the Tegra210 Smaug
>> platform.
>>
>&g
On 5/3/2016 11:45 AM, Rhyland Klein wrote:
> Enable the ChromeOS Embedded Controller, its I2C tunnel driver, and
> the BA27XXX battery driver. These are all used on the Tegra210 Smaug
> platform.
>
> Signed-off-by: Rhyland Klein <rkl...@nvidia.com>
Has anyone had a chan
On 5/3/2016 11:45 AM, Rhyland Klein wrote:
> Enable the ChromeOS Embedded Controller, its I2C tunnel driver, and
> the BA27XXX battery driver. These are all used on the Tegra210 Smaug
> platform.
>
> Signed-off-by: Rhyland Klein
Has anyone had a chance to review this
On 5/18/2016 3:58 PM, Rhyland Klein wrote:
> On 5/18/2016 3:36 PM, Rob Herring wrote:
>> On Wed, May 18, 2016 at 10:34 AM, Sasha Levin <sasha.le...@oracle.com> wrote:
>>> Hi Rhyland,
>>>
>>> I'm seeing a crash on boot that seems to have been caused by
&g
On 5/18/2016 3:58 PM, Rhyland Klein wrote:
> On 5/18/2016 3:36 PM, Rob Herring wrote:
>> On Wed, May 18, 2016 at 10:34 AM, Sasha Levin wrote:
>>> Hi Rhyland,
>>>
>>> I'm seeing a crash on boot that seems to have been caused by
>>> "
On 5/18/2016 3:36 PM, Rob Herring wrote:
> On Wed, May 18, 2016 at 10:34 AM, Sasha Levin wrote:
>> Hi Rhyland,
>>
>> I'm seeing a crash on boot that seems to have been caused by
>> "drivers/of: Fix depth when unflattening devicetree":
>>
>> [ 61.145229]
>>
On 5/18/2016 3:36 PM, Rob Herring wrote:
> On Wed, May 18, 2016 at 10:34 AM, Sasha Levin wrote:
>> Hi Rhyland,
>>
>> I'm seeing a crash on boot that seems to have been caused by
>> "drivers/of: Fix depth when unflattening devicetree":
>>
>> [ 61.145229]
>>
all through to the default switch case
and return -EINVAL. Returning this from max77620_config_fps() will
cause probe to fail.
Signed-off-by: Rhyland Klein <rkl...@nvidia.com>
---
drivers/mfd/max77620.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mfd/max77620.c b/drivers/mfd/m
all through to the default switch case
and return -EINVAL. Returning this from max77620_config_fps() will
cause probe to fail.
Signed-off-by: Rhyland Klein
---
drivers/mfd/max77620.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mfd/max77620.c b/drivers/mfd/max77620.c
index 199d26199
Enable the ChromeOS Embedded Controller, its I2C tunnel driver, and
the BA27XXX battery driver. These are all used on the Tegra210 Smaug
platform.
Signed-off-by: Rhyland Klein <rkl...@nvidia.com>
---
arch/arm64/configs/defconfig | 4
1 file changed, 4 insertions(+)
diff --git a/arch
Enable the ChromeOS Embedded Controller, its I2C tunnel driver, and
the BA27XXX battery driver. These are all used on the Tegra210 Smaug
platform.
Signed-off-by: Rhyland Klein
---
arch/arm64/configs/defconfig | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/configs/defconfig b
On 5/2/2016 10:28 AM, Laxman Dewangan wrote:
> NVIDIA's Tegra210 support the park bit to make pinmux configuration
> enable/disable. If parked bit is 1 then configuration does not apply
> and if it is 0 then pinmux configuration applies. This is to support
> to avoid any glitch in pinmux
On 5/2/2016 10:28 AM, Laxman Dewangan wrote:
> NVIDIA's Tegra210 support the park bit to make pinmux configuration
> enable/disable. If parked bit is 1 then configuration does not apply
> and if it is 0 then pinmux configuration applies. This is to support
> to avoid any glitch in pinmux
On 4/12/2016 11:23 AM, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Mon, Mar 21, 2016 at 03:58:52PM -0400, Rhyland Klein wrote:
>> Use a new Tegra210 version of the pll_register_pllre function to
>> allow setting the proper settings for the m and n div field
On 4/12/2016 11:23 AM, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Mon, Mar 21, 2016 at 03:58:52PM -0400, Rhyland Klein wrote:
>> Use a new Tegra210 version of the pll_register_pllre function to
>> allow setting the proper settings for the m and n div field
Add nodes for the ChromeOS Embedded Controller and for the gas gauge
connected to the I2C bus that it controls.
Signed-off-by: Rhyland Klein <rkl...@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 27 +++
1 file changed, 27 insertions(+)
diff --git
Add nodes for the ChromeOS Embedded Controller and for the gas gauge
connected to the I2C bus that it controls.
Signed-off-by: Rhyland Klein
---
arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts
The cros-ec driver should also be enabled for arm64 platforms as there
are platforms, like the tegra210-smaug which make use of the ChromeOS
Embedded Controller.
Signed-off-by: Rhyland Klein <rkl...@nvidia.com>
---
drivers/mfd/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
The cros-ec driver should also be enabled for arm64 platforms as there
are platforms, like the tegra210-smaug which make use of the ChromeOS
Embedded Controller.
Signed-off-by: Rhyland Klein
---
drivers/mfd/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mfd
Add pinmux node for Tegra210 Smaug board.
Signed-off-by: Rhyland Klein <rkl...@nvidia.com>
---
v2:
- Fixed address to align with recent patch:
'arm64: tegra: Remove 0, prefix from unit-addresses'
arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 1271 +
1 file c
Add pinmux node for Tegra210 Smaug board.
Signed-off-by: Rhyland Klein
---
v2:
- Fixed address to align with recent patch:
'arm64: tegra: Remove 0, prefix from unit-addresses'
arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 1271 +
1 file changed, 1271 insertions
On 3/21/2016 3:58 PM, Rhyland Klein wrote:
> Use a new Tegra210 version of the pll_register_pllre function to
> allow setting the proper settings for the m and n div fields.
>
> Additionally define PLL_RE_OUT1 on Tegra210.
>
> Signed-off-by: Rhyland Klein <rkl...@nv
On 3/21/2016 3:58 PM, Rhyland Klein wrote:
> Use a new Tegra210 version of the pll_register_pllre function to
> allow setting the proper settings for the m and n div fields.
>
> Additionally define PLL_RE_OUT1 on Tegra210.
>
> Signed-off-by: Rhyland Klein
> ---
Ping.
>
to disable.
The park bit is used to prevent glitching when reprogramming pinctrl
registers.
Based on work by:
Shravani Dingari <shrava...@nvidia.com>
Signed-off-by: Rhyland Klein <rkl...@nvidia.com>
---
drivers/pinctrl/tegra/pinctrl-tegra.c| 18 ++
drivers/pinctrl/t
to disable.
The park bit is used to prevent glitching when reprogramming pinctrl
registers.
Based on work by:
Shravani Dingari
Signed-off-by: Rhyland Klein
---
drivers/pinctrl/tegra/pinctrl-tegra.c| 18 ++
drivers/pinctrl/tegra/pinctrl-tegra.h| 6 ++
drivers/pinctrl
Add pinmux node for Tegra210 Smaug board.
Signed-off-by: Rhyland Klein <rkl...@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 1272 +
1 file changed, 1272 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
b/arch/arm64/bo
Add pinmux node for Tegra210 Smaug board.
Signed-off-by: Rhyland Klein
---
arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 1272 +
1 file changed, 1272 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
b/arch/arm64/boot/dts/nvidia/tegra210
On 3/30/2016 4:58 AM, YH Huang wrote:
> On Tue, 2016-03-29 at 11:05 -0400, Rhyland Klein wrote:
>> On 3/28/2016 9:52 PM, YH Huang wrote:
>>> On Mon, 2016-03-28 at 11:57 -0400, Rhyland Klein wrote:
>>>> On 3/28/2016 6:05 AM, Daniel Kurtz wrote:
>>>>>
On 3/30/2016 4:58 AM, YH Huang wrote:
> On Tue, 2016-03-29 at 11:05 -0400, Rhyland Klein wrote:
>> On 3/28/2016 9:52 PM, YH Huang wrote:
>>> On Mon, 2016-03-28 at 11:57 -0400, Rhyland Klein wrote:
>>>> On 3/28/2016 6:05 AM, Daniel Kurtz wrote:
>>>>>
On 3/28/2016 9:52 PM, YH Huang wrote:
> On Mon, 2016-03-28 at 11:57 -0400, Rhyland Klein wrote:
>> On 3/28/2016 6:05 AM, Daniel Kurtz wrote:
>>> +Rhyland Klein who original wrote this code...
>>>
>>> On Mon, Mar 28, 2016 at 10:32 AM, YH Huang <yh.hu...@medi
On 3/28/2016 9:52 PM, YH Huang wrote:
> On Mon, 2016-03-28 at 11:57 -0400, Rhyland Klein wrote:
>> On 3/28/2016 6:05 AM, Daniel Kurtz wrote:
>>> +Rhyland Klein who original wrote this code...
>>>
>>> On Mon, Mar 28, 2016 at 10:32 AM, YH Huang wrote:
>>
On 3/28/2016 6:05 AM, Daniel Kurtz wrote:
> +Rhyland Klein who original wrote this code...
>
> On Mon, Mar 28, 2016 at 10:32 AM, YH Huang <yh.hu...@mediatek.com> wrote:
>>
>> On Fri, 2016-03-25 at 11:06 +0800, Daniel Kurtz wrote:
>>> On Thu, Mar
On 3/28/2016 6:05 AM, Daniel Kurtz wrote:
> +Rhyland Klein who original wrote this code...
>
> On Mon, Mar 28, 2016 at 10:32 AM, YH Huang wrote:
>>
>> On Fri, 2016-03-25 at 11:06 +0800, Daniel Kurtz wrote:
>>> On Thu, Mar 24, 2016 at 2:43 PM, YH Hua
or potential deadlocks]
Signed-off-by: Rhyland Klein <rkl...@nvidia.com>
---
drivers/clk/tegra/clk-pll.c | 482 +++
drivers/clk/tegra/clk-tegra114.c | 155 +
drivers/clk/tegra/clk-tegra124.c | 156 +
drivers/clk/tegra/cl
Use a new Tegra210 version of the pll_register_pllre function to
allow setting the proper settings for the m and n div fields.
Additionally define PLL_RE_OUT1 on Tegra210.
Signed-off-by: Rhyland Klein <rkl...@nvidia.com>
---
drivers/clk/tegra/clk-pll.c
From: Andrew Bresticker
Move the UTMIPLL initialization code from the clk-tegra.c
files into clk-pll.c and perform the initialization sequence when
PLLU is enabled.
Signed-off-by: Andrew Bresticker
[rklein: Merged in some later fixes for potential deadlocks]
Signed-off-by: Rhyland Klein
Use a new Tegra210 version of the pll_register_pllre function to
allow setting the proper settings for the m and n div fields.
Additionally define PLL_RE_OUT1 on Tegra210.
Signed-off-by: Rhyland Klein
---
drivers/clk/tegra/clk-pll.c | 46
drivers
On 3/1/2016 2:00 PM, Stephen Boyd wrote:
> This flag is a no-op now. Remove usage of the flag.
>
> Cc: Rhyland Klein <rkl...@nvidia.com>
> Cc: Thierry Reding <tred...@nvidia.com>
> Signed-off-by: Stephen Boyd <sb...@codeaurora.org>
> ---
> drivers/clk/teg
On 3/1/2016 2:00 PM, Stephen Boyd wrote:
> This flag is a no-op now. Remove usage of the flag.
>
> Cc: Rhyland Klein
> Cc: Thierry Reding
> Signed-off-by: Stephen Boyd
> ---
> drivers/clk/tegra/clk-audio-sync.c | 2 +-
> drivers/clk/tegra/clk-dfll.c| 1 -
On 2/19/2016 11:28 AM, Rhyland Klein wrote:
> On 2/19/2016 3:50 AM, Lee Jones wrote:
>> On Thu, 18 Feb 2016, Rhyland Klein wrote:
>>
>>> MFD_ARRAY_SIZE() would not accurately return 0 if the passed
>>> parameter was NULL. Fix this so that num_resources wil
On 2/19/2016 11:28 AM, Rhyland Klein wrote:
> On 2/19/2016 3:50 AM, Lee Jones wrote:
>> On Thu, 18 Feb 2016, Rhyland Klein wrote:
>>
>>> MFD_ARRAY_SIZE() would not accurately return 0 if the passed
>>> parameter was NULL. Fix this so that num_resources wil
On 2/19/2016 3:50 AM, Lee Jones wrote:
> On Thu, 18 Feb 2016, Rhyland Klein wrote:
>
>> MFD_ARRAY_SIZE() would not accurately return 0 if the passed
>> parameter was NULL. Fix this so that num_resources will
>> accurately be 0 in the case that _res is NULL.
>
On 2/19/2016 3:50 AM, Lee Jones wrote:
> On Thu, 18 Feb 2016, Rhyland Klein wrote:
>
>> MFD_ARRAY_SIZE() would not accurately return 0 if the passed
>> parameter was NULL. Fix this so that num_resources will
>> accurately be 0 in the case that _res is NULL.
>>
&
MFD_ARRAY_SIZE() would not accurately return 0 if the passed
parameter was NULL. Fix this so that num_resources will
accurately be 0 in the case that _res is NULL.
cc: Lee Jones <lee.jo...@linaro.org>
cc: Laxman Dewangan <ldewan...@nvidia.com>
Signed-off-by: Rhyland Klein <rk
MFD_ARRAY_SIZE() would not accurately return 0 if the passed
parameter was NULL. Fix this so that num_resources will
accurately be 0 in the case that _res is NULL.
cc: Lee Jones
cc: Laxman Dewangan
Signed-off-by: Rhyland Klein
---
include/linux/mfd/core.h | 15 +--
1 file changed
On 2/11/2016 4:32 PM, Michael Turquette wrote:
> Quoting Rhyland Klein (2016-02-10 10:34:16)
>> On 2/9/2016 9:56 PM, Emilio López wrote:
>>> Hi,
>>>
>>> El 09/02/16 a las 19:48, Rhyland Klein escribió:
>>>> When clocks are registered, they coul
On 2/11/2016 4:32 PM, Michael Turquette wrote:
> Quoting Rhyland Klein (2016-02-10 10:34:16)
>> On 2/9/2016 9:56 PM, Emilio López wrote:
>>> Hi,
>>>
>>> El 09/02/16 a las 19:48, Rhyland Klein escribió:
>>>> When clocks are registered, they coul
On 2/9/2016 9:56 PM, Emilio López wrote:
> Hi,
>
> El 09/02/16 a las 19:48, Rhyland Klein escribió:
>> When clocks are registered, they could be enabled already in
>> hardware. As of now, the enable count will start at 0. When this
>> happens, it means a clock is enable
On 2/9/2016 9:56 PM, Emilio López wrote:
> Hi,
>
> El 09/02/16 a las 19:48, Rhyland Klein escribió:
>> When clocks are registered, they could be enabled already in
>> hardware. As of now, the enable count will start at 0. When this
>> happens, it means a clock is enable
the first time someone
calls clk_enable() for a clk that was on at boot.
Signed-off-by: Rhyland Klein
---
Perhaps this code should be something optional right now? I can't test
all boards that use this framework, and some boards may be using the
clocks that are on but thought off without realizing
the first time someone
calls clk_enable() for a clk that was on at boot.
Signed-off-by: Rhyland Klein <rkl...@nvidia.com>
---
Perhaps this code should be something optional right now? I can't test
all boards that use this framework, and some boards may be using the
clocks that are on but thoug
On 2/5/2016 9:01 AM, Jon Hunter wrote:
> When setting the pll_a frequency, to what should be 368639844 Hz, the
> actual output frequency of the pll is 737279687 Hz (as reported by the
> debugfs clk_summary entry), which is double the expect frequency. The
> calculations for the pll frequency
On 2/5/2016 9:01 AM, Jon Hunter wrote:
> When setting the pll_a frequency, to what should be 368639844 Hz, the
> actual output frequency of the pll is 737279687 Hz (as reported by the
> debugfs clk_summary entry), which is double the expect frequency. The
> calculations for the pll frequency
- val &= ~BIT(24); /* disable PLLU_OVERRIDE */
> + val &= ~PLLU_BASE_OVERRIDE; /* disable PLLU_OVERRIDE */
> writel(val, clk_base + pll_u_vco_params.base_reg);
>
> clk = tegra_clk_register_pllre("pll_u_vco", "pll_ref", clk_base, pmc,
{ TEGRA210_CLK_PLL_RE_VCO, TEGRA210_CLK_CLK_MAX, 67200, 1 },
> - { TEGRA210_CLK_PLL_U_OUT1, TEGRA210_CLK_CLK_MAX, 4800, 1 },
> - { TEGRA210_CLK_PLL_U_OUT2, TEGRA210_CLK_CLK_MAX, 6000, 1 },
> { TEGRA210_CLK_XUSB_GATE, TEGRA210_CLK_CLK_MAX, 0, 1 },
>
TEGRA210_CLK_PLL_P, 1200, 1 },
> { TEGRA210_CLK_PLL_RE_VCO, TEGRA210_CLK_CLK_MAX, 67200, 1 },
> - { TEGRA210_CLK_PLL_U_OUT1, TEGRA210_CLK_CLK_MAX, 4800, 1 },
> - { TEGRA210_CLK_PLL_U_OUT2, TEGRA210_CLK_CLK_MAX, 6000, 1 },
> { TEGRA210_CLK_XUSB_GATE, TEG
+ pll_u_vco_params.base_reg);
> - val &= ~BIT(24); /* disable PLLU_OVERRIDE */
> + val &= ~PLLU_BASE_OVERRIDE; /* disable PLLU_OVERRIDE */
> writel(val, clk_base + pll_u_vco_params.base_reg);
>
> clk = tegra_clk_register_pllre("pll_u_vco", "pll_r
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