On 5/1/2015 11:12 PM, Jim Lin wrote:
+static void clk_plle_tegra210_is_enabled(struct struct clk_hw *hw) {
Returned type is int instead of void.
Also one struct only for clk_hw *hw?
+struct tegra_clk_pll *pll = to_clk_pll(hw);
+u32 val;
+
+val = pll_readl_base(pll);
+
+
callback
clk: tegra: pll: Add Set_default logic
clk: tegra: Add Super Gen5 Logic
Rhyland Klein (12):
clk: tegra: Modify tegra_audio_clk_init to accept more plls
clk: tegra: periph: add new periph clks and muxes for Tegra210
clk: tegra: pll: add tegra_pll_wait_for_lock to clk header
clk: tegra
tegra_audio_clk_init was written expecting a single PLL to be
passed in directly. Change this to accept an array which will
allow for supporting multiple plls and specifying specific data
about them, like their parent, which may change over time.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
From: Bill Huang bilhu...@nvidia.com
New SoC's may have more then 3 MISC registers, so bump up the
array size and use a #define to be more informative about the value.
Signed-off-by: Bill Huang bilhu...@nvidia.com
---
drivers/clk/tegra/clk.h |4 +++-
1 file changed, 3 insertions(+), 1
Swap out the generic WARN_ON with a WARN which gives more
information about what is happening.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
drivers/clk/tegra/clk-pll.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra
Instead of having multiple similar wrapper functions for
_clk_pll_[enable|disable], we can simplify it to single
wrappers and use checks to avoid the logic we don't want to use.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
v2:
- Moved the iddq settings into _clk_pll_enable/disable
From: Bill Huang bilhu...@nvidia.com
Add logic which (if specified for a pll) can verify that a PLL is set
to the proper default value and if not can set it. This can be
specified per PLL as each will have different default values.
Based on original work by Aleksandr Frid af...@nvidia.com
Create a wrapper interface to make use of the existing
clk_pll_wait_for_lock. This will be useful for implementations
of callbacks in Tegra SoC specific clock drivers.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
drivers/clk/tegra/clk-pll.c |5 +
drivers/clk/tegra/clk.h |1
the other fields.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
v2:
- Added fix for _calc_dynamic_ramp_rate where input_rate wasn't ever
populated in the cfg, which could cause problems later if/when
accessed.
drivers/clk/tegra/clk-pll.c |8 ++--
1 file changed, 2 insertions(+), 6
Tegra210 has significant differences in muxes for peripheral clocks.
One of the most important changes is that pll_m isn't to be used
as a source for peripherals. Therefore, we need to define the new
muxes and new clocks to use those muxes for Tegra210 support.
Signed-off-by: Rhyland Klein rkl
From: Bill Huang bilhu...@nvidia.com
Add a callback to the pll_params for custom dynamic ramping
functions which can be specified per PLL.
Signed-off-by: Bill Huang bilhu...@nvidia.com
---
drivers/clk/tegra/clk.h |4
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/tegra/clk.h
abres...@chromium.org
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
v3:
- Added fix for this bug which was found during testing
drivers/clk/tegra/clk-pll.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk
From: Bill Huang bilhu...@nvidia.com
Super clock divider control and clock source mux of Tegra210 has changed
a little against prior SoCs, this patch adds Gen5 logic to address those
differences.
Signed-off-by: Bill Huang bilhu...@nvidia.com
---
v2:
- Fixed sclk divider address (0x370 - 0x2c)
Tegra210 SoC's have 2 PLLS for memory usage. Add plumbing to register
and handle PLLMB.
PLLMB is used to allow switching between 2 PLLM's without having to use
and intermediate backup PLL, as we need to lock the PLL before we can
switch to it.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
Implement clock support for Tegra210.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
v4:
- Fixed checkpatch errors
- Fixed pllx_dyn_ramp error (missing -params)
v3:
- Fixed pll_u hierarchy. PLL_U has a vco output now, and out1 and out2
clocks which are used to generate 60M and 48M
From: Bill Huang bilhu...@nvidia.com
This code makes use of the SDM fractional divider if present to
contrain the allowable programming range of the PLL divider register
bitfields to take advantage of higher frequency granularity that can
be induced by the SDM divider.
Based on original work by
On Tegra210 SoC's, the logic to enable several of the plls is different
from previous generations. Therefore, add registeration functions specific
to Tegra210 which will handle them appropriately.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
v4:
- Fixed plle_tegra210_is_enabled callback
From: Bill Huang bilhu...@nvidia.com
If a PLL has a reset_reg specified, properly handle that in the
enable/disable logic paths.
Signed-off-by: Bill Huang bilhu...@nvidia.com
---
v2:
- Moved reset logic to _clk_pll_enable/disable as well
drivers/clk/tegra/clk-pll.c | 12
-by: Rhyland Klein rkl...@nvidia.com
---
drivers/clk/tegra/clk-pll.c | 24 ++--
drivers/clk/tegra/clk.h | 10 ++
2 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 2a559408cee1..0b9cbe12a3eb
.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
drivers/clk/tegra/clk-pll.c | 11 ++-
drivers/clk/tegra/clk-tegra114.c | 23 +--
drivers/clk/tegra/clk-tegra124.c | 24 +++-
drivers/clk/tegra/clk-tegra20.c | 18
This adds logic for taking SDM_DIN (Sigma Delta Modulator) setting into
the equation to calculate the effective N value for PLL which supports
fractional divider.
The effective N = NDIV + 1/2 + SDM_DIN/2^13, where NDIV is the integer
feedback divider.
Signed-off-by: Rhyland Klein rkl
From: Bill Huang bilhu...@nvidia.com
Add some logic for Spread Spectrum control. It is used in conjuncture
with SDM fractional dividers. SSC has to be disabled when we configure
the divider settings.
Signed-off-by: Bill Huang bilhu...@nvidia.com
---
drivers/clk/tegra/clk-pll.c | 25
tegra_audio_clk_init was written expecting a single PLL to be
passed in directly. Change this to accept an array which will
allow for supporting multiple plls and specifying specific data
about them, like their parent, which may change over time.
Signed-off-by: Rhyland Klein
---
drivers/clk
Tegra210 has significant differences in muxes for peripheral clocks.
One of the most important changes is that pll_m isn't to be used
as a source for peripherals. Therefore, we need to define the new
muxes and new clocks to use those muxes for Tegra210 support.
Signed-off-by: Rhyland Klein
Instead of having multiple similar wrapper functions for
_clk_pll_[enable|disable], we can simplify it to single
wrappers and use checks to avoid the logic we don't want to use.
Signed-off-by: Rhyland Klein
---
v2:
- Moved the iddq settings into _clk_pll_enable/disable. This is because
Swap out the generic WARN_ON with a WARN which gives more
information about what is happening.
Signed-off-by: Rhyland Klein
---
drivers/clk/tegra/clk-pll.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index
This adds logic for taking SDM_DIN (Sigma Delta Modulator) setting into
the equation to calculate the effective N value for PLL which supports
fractional divider.
The effective N = NDIV + 1/2 + SDM_DIN/2^13, where NDIV is the integer
feedback divider.
Signed-off-by: Rhyland Klein
---
drivers
Create a wrapper interface to make use of the existing
clk_pll_wait_for_lock. This will be useful for implementations
of callbacks in Tegra SoC specific clock drivers.
Signed-off-by: Rhyland Klein
---
drivers/clk/tegra/clk-pll.c |5 +
drivers/clk/tegra/clk.h |1 +
2 files
On Tegra210 SoC's, the logic to enable several of the plls is different
from previous generations. Therefore, add registeration functions specific
to Tegra210 which will handle them appropriately.
Signed-off-by: Rhyland Klein
---
v2:
- Fixed plle logic. PLLE on Tegra210 has had its enable bit
From: Bill Huang
Add some logic for Spread Spectrum control. It is used in conjuncture
with SDM fractional dividers. SSC has to be disabled when we configure
the divider settings.
Signed-off-by: Bill Huang
---
drivers/clk/tegra/clk-pll.c | 25 -
From: Bill Huang
This code makes use of the SDM fractional divider if present to
contrain the allowable programming range of the PLL divider register
bitfields to take advantage of higher frequency granularity that can
be induced by the SDM divider.
Based on original work by Aleksandr Frid
.
Signed-off-by: Rhyland Klein
---
drivers/clk/tegra/clk-pll.c | 11 ++-
drivers/clk/tegra/clk-tegra114.c | 23 +--
drivers/clk/tegra/clk-tegra124.c | 24 +++-
drivers/clk/tegra/clk-tegra20.c | 18 ++
drivers/clk/tegra
Tegra210 SoC's have 2 PLLS for memory usage. Add plumbing to register
and handle PLLMB.
PLLMB is used to allow switching between 2 PLLM's without having to use
and intermediate backup PLL, as we need to lock the PLL before we can
switch to it.
Signed-off-by: Rhyland Klein
---
v3:
- Flushed
For Tegra210, the logic to calculate out-of-table rates is different
from previous generations. Add callbacks that can be overridden to
allow for different ways of calculating rates. Default to
_cal_rate when not specified.
Based on original work by Aleksandr Frid
Signed-off-by: Rhyland Klein
the other fields.
Signed-off-by: Rhyland Klein
---
v2:
- Added fix for _calc_dynamic_ramp_rate where input_rate wasn't ever
populated in the cfg, which could cause problems later if/when
accessed.
drivers/clk/tegra/clk-pll.c |8 ++--
1 file changed, 2 insertions(+), 6 deletions
From: Bill Huang
Super clock divider control and clock source mux of Tegra210 has changed
a little against prior SoCs, this patch adds Gen5 logic to address those
differences.
Signed-off-by: Bill Huang
---
v2:
- Fixed sclk divider address (0x370 -> 0x2c)
drivers/clk/tegra/Makefile
From: Bill Huang
If a PLL has a reset_reg specified, properly handle that in the
enable/disable logic paths.
Signed-off-by: Bill Huang
---
v2:
- Moved reset logic to _clk_pll_enable/disable as well
drivers/clk/tegra/clk-pll.c | 12
drivers/clk/tegra/clk.h |2 ++
2
Implement clock support for Tegra210.
Signed-off-by: Rhyland Klein
---
v3:
- Fixed pll_u hierarchy. PLL_U has a vco output now, and out1 and out2
clocks which are used to generate 60M and 48M clocks. VCO is used for
480M clock and the pll_u_out clock generates the 240M clock
From: Bill Huang
Add logic which (if specified for a pll) can verify that a PLL is set
to the proper default value and if not can set it. This can be
specified per PLL as each will have different default values.
Based on original work by Aleksandr Frid
Signed-off-by: Bill Huang
---
v2:
-
From: Bill Huang
Add a callback to the pll_params for custom dynamic ramping
functions which can be specified per PLL.
Signed-off-by: Bill Huang
---
drivers/clk/tegra/clk.h |4
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index
From: Andrew Bresticker
Without this change clk_get_rate would return the final output
rather than the VCO output as it would factor in the pdiv when
it shouldn't. This will cause problems for all dividers in the
subtree of the VCO PLL.
Signed-off-by: Andrew Bresticker
Signed-off-by: Rhyland
From: Bill Huang
New SoC's may have more then 3 MISC registers, so bump up the
array size and use a #define to be more informative about the value.
Signed-off-by: Bill Huang
---
drivers/clk/tegra/clk.h |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
clk: tegra: Add Super Gen5 Logic
Rhyland Klein (12):
clk: tegra: Modify tegra_audio_clk_init to accept more plls
clk: tegra: periph: add new periph clks and muxes for Tegra210
clk: tegra: pll: add tegra_pll_wait_for_lock to clk header
clk: tegra: pll: simplify clk_enable_path
clk: tegra:
From: Bill Huang bilhu...@nvidia.com
If a PLL has a reset_reg specified, properly handle that in the
enable/disable logic paths.
Signed-off-by: Bill Huang bilhu...@nvidia.com
---
v2:
- Moved reset logic to _clk_pll_enable/disable as well
drivers/clk/tegra/clk-pll.c | 12
From: Bill Huang bilhu...@nvidia.com
Super clock divider control and clock source mux of Tegra210 has changed
a little against prior SoCs, this patch adds Gen5 logic to address those
differences.
Signed-off-by: Bill Huang bilhu...@nvidia.com
---
v2:
- Fixed sclk divider address (0x370 - 0x2c)
On Tegra210 SoC's, the logic to enable several of the plls is different
from previous generations. Therefore, add registeration functions specific
to Tegra210 which will handle them appropriately.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
v2:
- Fixed plle logic. PLLE on Tegra210 has
Create a wrapper interface to make use of the existing
clk_pll_wait_for_lock. This will be useful for implementations
of callbacks in Tegra SoC specific clock drivers.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
drivers/clk/tegra/clk-pll.c |5 +
drivers/clk/tegra/clk.h |1
From: Bill Huang bilhu...@nvidia.com
Add some logic for Spread Spectrum control. It is used in conjuncture
with SDM fractional dividers. SSC has to be disabled when we configure
the divider settings.
Signed-off-by: Bill Huang bilhu...@nvidia.com
---
drivers/clk/tegra/clk-pll.c | 25
This adds logic for taking SDM_DIN (Sigma Delta Modulator) setting into
the equation to calculate the effective N value for PLL which supports
fractional divider.
The effective N = NDIV + 1/2 + SDM_DIN/2^13, where NDIV is the integer
feedback divider.
Signed-off-by: Rhyland Klein rkl
From: Bill Huang bilhu...@nvidia.com
Add logic which (if specified for a pll) can verify that a PLL is set
to the proper default value and if not can set it. This can be
specified per PLL as each will have different default values.
Based on original work by Aleksandr Frid af...@nvidia.com
Implement clock support for Tegra210.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
v3:
- Fixed pll_u hierarchy. PLL_U has a vco output now, and out1 and out2
clocks which are used to generate 60M and 48M clocks. VCO is used for
480M clock and the pll_u_out clock generates the 240M
From: Bill Huang bilhu...@nvidia.com
New SoC's may have more then 3 MISC registers, so bump up the
array size and use a #define to be more informative about the value.
Signed-off-by: Bill Huang bilhu...@nvidia.com
---
drivers/clk/tegra/clk.h |4 +++-
1 file changed, 3 insertions(+), 1
From: Bill Huang bilhu...@nvidia.com
Add a callback to the pll_params for custom dynamic ramping
functions which can be specified per PLL.
Signed-off-by: Bill Huang bilhu...@nvidia.com
---
drivers/clk/tegra/clk.h |4
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/tegra/clk.h
abres...@chromium.org
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
v3:
- Added fix for this bug which was found during testing
drivers/clk/tegra/clk-pll.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk
Swap out the generic WARN_ON with a WARN which gives more
information about what is happening.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
drivers/clk/tegra/clk-pll.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra
Instead of having multiple similar wrapper functions for
_clk_pll_[enable|disable], we can simplify it to single
wrappers and use checks to avoid the logic we don't want to use.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
v2:
- Moved the iddq settings into _clk_pll_enable/disable
Tegra210 has significant differences in muxes for peripheral clocks.
One of the most important changes is that pll_m isn't to be used
as a source for peripherals. Therefore, we need to define the new
muxes and new clocks to use those muxes for Tegra210 support.
Signed-off-by: Rhyland Klein rkl
tegra_audio_clk_init was written expecting a single PLL to be
passed in directly. Change this to accept an array which will
allow for supporting multiple plls and specifying specific data
about them, like their parent, which may change over time.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
: tegra: Add Super Gen5 Logic
Rhyland Klein (12):
clk: tegra: Modify tegra_audio_clk_init to accept more plls
clk: tegra: periph: add new periph clks and muxes for Tegra210
clk: tegra: pll: add tegra_pll_wait_for_lock to clk header
clk: tegra: pll: simplify clk_enable_path
clk: tegra: pll
From: Bill Huang bilhu...@nvidia.com
This code makes use of the SDM fractional divider if present to
contrain the allowable programming range of the PLL divider register
bitfields to take advantage of higher frequency granularity that can
be induced by the SDM divider.
Based on original work by
.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
drivers/clk/tegra/clk-pll.c | 11 ++-
drivers/clk/tegra/clk-tegra114.c | 23 +--
drivers/clk/tegra/clk-tegra124.c | 24 +++-
drivers/clk/tegra/clk-tegra20.c | 18
Tegra210 SoC's have 2 PLLS for memory usage. Add plumbing to register
and handle PLLMB.
PLLMB is used to allow switching between 2 PLLM's without having to use
and intermediate backup PLL, as we need to lock the PLL before we can
switch to it.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
-by: Rhyland Klein rkl...@nvidia.com
---
drivers/clk/tegra/clk-pll.c | 24 ++--
drivers/clk/tegra/clk.h | 10 ++
2 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 2a559408cee1..0b9cbe12a3eb
the other fields.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
v2:
- Added fix for _calc_dynamic_ramp_rate where input_rate wasn't ever
populated in the cfg, which could cause problems later if/when
accessed.
drivers/clk/tegra/clk-pll.c |8 ++--
1 file changed, 2 insertions(+), 6
On 4/30/2015 4:43 PM, Andrew Bresticker wrote:
> Hi Rhyland,
>
> On Wed, Apr 29, 2015 at 10:21 AM, Rhyland Klein wrote:
>> Implement clock support for Tegra210.
>>
>> Signed-off-by: Rhyland Klein
>
>> --- /dev/null
>> +++ b/drivers/clk/
On 4/30/2015 6:12 AM, Peter De Schrijver wrote:
> On Wed, Apr 29, 2015 at 01:21:46PM -0400, Rhyland Klein wrote:
>> From: Bill Huang
>>
>> Add logic which (if specified for a pll) can verify that a PLL is set
>> to the proper default value and if not can set it. This
On 4/30/2015 4:43 PM, Andrew Bresticker wrote:
Hi Rhyland,
On Wed, Apr 29, 2015 at 10:21 AM, Rhyland Klein rkl...@nvidia.com wrote:
Implement clock support for Tegra210.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
--- /dev/null
+++ b/drivers/clk/tegra/clk-tegra210.c
On 4/30/2015 6:12 AM, Peter De Schrijver wrote:
On Wed, Apr 29, 2015 at 01:21:46PM -0400, Rhyland Klein wrote:
From: Bill Huang bilhu...@nvidia.com
Add logic which (if specified for a pll) can verify that a PLL is set
to the proper default value and if not can set it. This can be
specified
On 4/29/2015 2:27 PM, Andrew Bresticker wrote:
> Hi Rhyland,
>
> On Wed, Apr 29, 2015 at 10:21 AM, Rhyland Klein wrote:
>> On Tegra210 SoC's, the logic to enable several of the plls is different
>> from previous generations. Therefore, add registeration functions specific
tegra_audio_clk_init was written expecting a single PLL to be
passed in directly. Change this to accept an array which will
allow for supporting multiple plls and specifying specific data
about them, like their parent, which may change over time.
Signed-off-by: Rhyland Klein
---
drivers/clk
Swap out the generic WARN_ON with a WARN which gives more
information about what is happening.
Signed-off-by: Rhyland Klein
---
drivers/clk/tegra/clk-pll.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index
From: Bill Huang
New SoC's may have more then 3 MISC registers, so bump up the
array size and use a #define to be more informative about the value.
Signed-off-by: Bill Huang
---
drivers/clk/tegra/clk.h |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
.
Signed-off-by: Rhyland Klein
---
drivers/clk/tegra/clk-pll.c | 11 ++-
drivers/clk/tegra/clk-tegra114.c | 23 +--
drivers/clk/tegra/clk-tegra124.c | 24 +++-
drivers/clk/tegra/clk-tegra20.c | 18 ++
drivers/clk/tegra
From: Bill Huang
Add some logic for Spread Spectrum control. It is used in conjuncture
with SDM fractional dividers. SSC has to be disabled when we configure
the divider settings.
Signed-off-by: Bill Huang
---
drivers/clk/tegra/clk-pll.c | 25 -
This adds logic for taking SDM_DIN (Sigma Delta Modulator) setting into
the equation to calculate the effective N value for PLL which supports
fractional divider.
The effective N = NDIV + 1/2 + SDM_DIN/2^13, where NDIV is the integer
feedback divider.
Signed-off-by: Rhyland Klein
---
drivers
Create a wrapper interface to make use of the existing
clk_pll_wait_for_lock. This will be useful for implementations
of callbacks in Tegra SoC specific clock drivers.
Signed-off-by: Rhyland Klein
---
drivers/clk/tegra/clk-pll.c |5 +
drivers/clk/tegra/clk.h |1 +
2 files
Tegra210 SoC's have 2 PLLS for memory usage. Add plumbing to register
and handle PLLMB.
Signed-off-by: Rhyland Klein
---
v2:
- Fixed commit description as suggested.
drivers/clk/tegra/clk-pll.c | 46 +++
drivers/clk/tegra/clk.h |9
From: Bill Huang
If a PLL has a reset_reg specified, properly handle that in the
enable/disable logic paths.
Signed-off-by: Bill Huang
---
v2:
- Moved reset logic to _clk_pll_enable/disable as well
drivers/clk/tegra/clk-pll.c | 12
drivers/clk/tegra/clk.h |2 ++
2
For Tegra210, the logic to calculate out-of-table rates is different
from previous generations. Add callbacks that can be overridden to
allow for different ways of calculating rates. Default to
_cal_rate when not specified.
Based on original work by Aleksandr Frid
Signed-off-by: Rhyland Klein
On Tegra210 SoC's, the logic to enable several of the plls is different
from previous generations. Therefore, add registeration functions specific
to Tegra210 which will handle them appropriately.
Signed-off-by: Rhyland Klein
---
v2:
- Fixed plle logic. PLLE on Tegra210 has had its enable bit
Tegra210 has significant differences in muxes for peripheral clocks.
One of the most important changes is that pll_m isn't to be used
as a source for peripherals. Therefore, we need to define the new
muxes and new clocks to use those muxes for Tegra210 support.
Signed-off-by: Rhyland Klein
the other fields.
Signed-off-by: Rhyland Klein
---
v2:
- Added fix for _calc_dynamic_ramp_rate where input_rate wasn't ever
populated in the cfg, which could cause problems later if/when
accessed.
drivers/clk/tegra/clk-pll.c |8 ++--
1 file changed, 2 insertions(+), 6 deletions
From: Bill Huang
Add a callback to the pll_params for custom dynamic ramping
functions which can be specified per PLL.
Signed-off-by: Bill Huang
---
drivers/clk/tegra/clk.h |4
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index
From: Bill Huang
This code makes use of the SDM fractional divider if present to
contrain the allowable programming range of the PLL divider register
bitfields to take advantage of higher frequency granularity that can
be induced by the SDM divider.
Based on original work by Aleksandr Frid
From: Bill Huang
Super clock divider control and clock source mux of Tegra210 has changed
a little against prior SoCs, this patch adds Gen5 logic to address those
differences.
Signed-off-by: Bill Huang
---
v2:
- Fixed sclk divider address (0x370 -> 0x2c)
drivers/clk/tegra/Makefile
Implement clock support for Tegra210.
Signed-off-by: Rhyland Klein
---
v2:
- Fixed pll_a sdm_din_reg address (MISC0 -> MISC1)
- Fixed plld_set_defaults to not override DSI_CLKENABLE
- Fixed error in pll_e_freq table where cml divider was set into wrong field
- Removed freq comments ba
misc_reg count from 3 -> 6
clk: tegra: pll: Add logic for SS
clk: tegra: pll: Add code to handle if resets are supported by PLL
clk: tegra: pll: Adjust vco_min if SDM present
clk: tegra: pll: Add dyn_ramp callback
clk: tegra: pll: Add Set_default logic
clk: tegra: Add Super Gen5 Logic
Rhyl
From: Bill Huang
Add logic which (if specified for a pll) can verify that a PLL is set
to the proper default value and if not can set it. This can be
specified per PLL as each will have different default values.
Signed-off-by: Bill Huang
---
v2:
- Remove MACRO for PLL_MISC_CHECK_DEFAULT as
Instead of having multiple similar wrapper functions for
_clk_pll_[enable|disable], we can simplify it to single
wrappers and use checks to avoid the logic we don't want to use.
Signed-off-by: Rhyland Klein
---
v2:
- Moved the iddq settings into _clk_pll_enable/disable. This is because
From: Bill Huang bilhu...@nvidia.com
Super clock divider control and clock source mux of Tegra210 has changed
a little against prior SoCs, this patch adds Gen5 logic to address those
differences.
Signed-off-by: Bill Huang bilhu...@nvidia.com
---
v2:
- Fixed sclk divider address (0x370 - 0x2c)
Implement clock support for Tegra210.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
v2:
- Fixed pll_a sdm_din_reg address (MISC0 - MISC1)
- Fixed plld_set_defaults to not override DSI_CLKENABLE
- Fixed error in pll_e_freq table where cml divider was set into wrong field
- Removed
misc_reg count from 3 - 6
clk: tegra: pll: Add logic for SS
clk: tegra: pll: Add code to handle if resets are supported by PLL
clk: tegra: pll: Adjust vco_min if SDM present
clk: tegra: pll: Add dyn_ramp callback
clk: tegra: pll: Add Set_default logic
clk: tegra: Add Super Gen5 Logic
Rhyland
Create a wrapper interface to make use of the existing
clk_pll_wait_for_lock. This will be useful for implementations
of callbacks in Tegra SoC specific clock drivers.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
drivers/clk/tegra/clk-pll.c |5 +
drivers/clk/tegra/clk.h |1
This adds logic for taking SDM_DIN (Sigma Delta Modulator) setting into
the equation to calculate the effective N value for PLL which supports
fractional divider.
The effective N = NDIV + 1/2 + SDM_DIN/2^13, where NDIV is the integer
feedback divider.
Signed-off-by: Rhyland Klein rkl
.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
drivers/clk/tegra/clk-pll.c | 11 ++-
drivers/clk/tegra/clk-tegra114.c | 23 +--
drivers/clk/tegra/clk-tegra124.c | 24 +++-
drivers/clk/tegra/clk-tegra20.c | 18
From: Bill Huang bilhu...@nvidia.com
Add some logic for Spread Spectrum control. It is used in conjuncture
with SDM fractional dividers. SSC has to be disabled when we configure
the divider settings.
Signed-off-by: Bill Huang bilhu...@nvidia.com
---
drivers/clk/tegra/clk-pll.c | 25
From: Bill Huang bilhu...@nvidia.com
New SoC's may have more then 3 MISC registers, so bump up the
array size and use a #define to be more informative about the value.
Signed-off-by: Bill Huang bilhu...@nvidia.com
---
drivers/clk/tegra/clk.h |4 +++-
1 file changed, 3 insertions(+), 1
Tegra210 SoC's have 2 PLLS for memory usage. Add plumbing to register
and handle PLLMB.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
v2:
- Fixed commit description as suggested.
drivers/clk/tegra/clk-pll.c | 46 +++
drivers/clk/tegra/clk.h
Tegra210 has significant differences in muxes for peripheral clocks.
One of the most important changes is that pll_m isn't to be used
as a source for peripherals. Therefore, we need to define the new
muxes and new clocks to use those muxes for Tegra210 support.
Signed-off-by: Rhyland Klein rkl
On Tegra210 SoC's, the logic to enable several of the plls is different
from previous generations. Therefore, add registeration functions specific
to Tegra210 which will handle them appropriately.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
v2:
- Fixed plle logic. PLLE on Tegra210 has
401 - 500 of 762 matches
Mail list logo
