-by: Rhyland Klein rkl...@nvidia.com
---
drivers/clk/tegra/clk-pll.c | 24 ++--
drivers/clk/tegra/clk.h | 10 ++
2 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 2a559408cee1..0b9cbe12a3eb
From: Bill Huang bilhu...@nvidia.com
If a PLL has a reset_reg specified, properly handle that in the
enable/disable logic paths.
Signed-off-by: Bill Huang bilhu...@nvidia.com
---
v2:
- Moved reset logic to _clk_pll_enable/disable as well
drivers/clk/tegra/clk-pll.c | 12
From: Bill Huang bilhu...@nvidia.com
Add a callback to the pll_params for custom dynamic ramping
functions which can be specified per PLL.
Signed-off-by: Bill Huang bilhu...@nvidia.com
---
drivers/clk/tegra/clk.h |4
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/tegra/clk.h
From: Bill Huang bilhu...@nvidia.com
This code makes use of the SDM fractional divider if present to
contrain the allowable programming range of the PLL divider register
bitfields to take advantage of higher frequency granularity that can
be induced by the SDM divider.
Based on original work by
Instead of having multiple similar wrapper functions for
_clk_pll_[enable|disable], we can simplify it to single
wrappers and use checks to avoid the logic we don't want to use.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
v2:
- Moved the iddq settings into _clk_pll_enable/disable
From: Bill Huang bilhu...@nvidia.com
Add logic which (if specified for a pll) can verify that a PLL is set
to the proper default value and if not can set it. This can be
specified per PLL as each will have different default values.
Signed-off-by: Bill Huang bilhu...@nvidia.com
---
v2:
- Remove
the other fields.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
v2:
- Added fix for _calc_dynamic_ramp_rate where input_rate wasn't ever
populated in the cfg, which could cause problems later if/when
accessed.
drivers/clk/tegra/clk-pll.c |8 ++--
1 file changed, 2 insertions(+), 6
Swap out the generic WARN_ON with a WARN which gives more
information about what is happening.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
drivers/clk/tegra/clk-pll.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra
tegra_audio_clk_init was written expecting a single PLL to be
passed in directly. Change this to accept an array which will
allow for supporting multiple plls and specifying specific data
about them, like their parent, which may change over time.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
On 4/29/2015 2:27 PM, Andrew Bresticker wrote:
Hi Rhyland,
On Wed, Apr 29, 2015 at 10:21 AM, Rhyland Klein rkl...@nvidia.com wrote:
On Tegra210 SoC's, the logic to enable several of the plls is different
from previous generations. Therefore, add registeration functions specific
to Tegra210
Tegra210 has significant differences in muxes for peripheral clocks.
One of the most important changes is that pll_m isn't to be used
as a source for peripherals. Therefore, we need to define the new
muxes and new clocks to use those muxes for Tegra210 support.
Signed-off-by: Rhyland Klein
Create a wrapper interface to make use of the existing
clk_pll_wait_for_lock. This will be useful for implementations
of callbacks in Tegra SoC specific clock drivers.
Signed-off-by: Rhyland Klein
---
drivers/clk/tegra/clk-pll.c |5 +
drivers/clk/tegra/clk.h |1 +
2 files
From: Bill Huang
New SoC's may have more then 3 MISC registers, so bump up the
array size and use a #define to be more informative about the value.
Signed-off-by: Bill Huang
---
drivers/clk/tegra/clk.h |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
.
Signed-off-by: Rhyland Klein
---
drivers/clk/tegra/clk-pll.c | 11 ++-
drivers/clk/tegra/clk-tegra114.c | 23 +--
drivers/clk/tegra/clk-tegra124.c | 24 +++-
drivers/clk/tegra/clk-tegra20.c | 18 ++
drivers/clk/tegra
This adds logic for taking SDM_DIN (Sigma Delta Modulator) setting into
the equation to calculate the effective N value for PLL which supports
fractional divider.
The effective N = NDIV + 1/2 + SDM_DIN/2^13, where NDIV is the integer
feedback divider.
Signed-off-by: Rhyland Klein
---
drivers
For Tegra210, the logic to calculate out-of-table rates is different
from previous generations. Add callbacks that can be overridden to
allow for different ways of calculating rates. Default to
_cal_rate when not specified.
Based on original work by Aleksandr Frid
Signed-off-by: Rhyland Klein
Tegra210 SoC's have a backup PLL for memory usage, PLLMB. Add
plumbing to register and handle it.
Signed-off-by: Rhyland Klein
---
drivers/clk/tegra/clk-pll.c | 46 +++
drivers/clk/tegra/clk.h |9 +
2 files changed, 51 insertions(+), 4
From: Bill Huang
If a PLL has a reset_reg specified, properly handle that in the
enable/disable logic paths._
Signed-off-by: Bill Huang
---
drivers/clk/tegra/clk-pll.c | 12
drivers/clk/tegra/clk.h |2 ++
2 files changed, 14 insertions(+)
diff --git
From: Bill Huang
Add logic which (if specified for a pll) can verify that a PLL is set
to the proper default value and if not can set it. This can be
specified per PLL as each will have different default values.
Signed-off-by: Bill Huang
---
drivers/clk/tegra/clk-pll.c | 46
Instead of having multiple similar wrapper functions for
_clk_pll_[enable|disable], we can simplify it to single
wrappers and use checks to avoid the logic we don't want to use.
Signed-off-by: Rhyland Klein
---
drivers/clk/tegra/clk-pll.c | 79 ++-
1
From: Bill Huang
Add a callback to the pll_params for custom dynamic ramping
functions which can be specified per PLL.
Signed-off-by: Bill Huang
---
drivers/clk/tegra/clk.h |4
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index
From: Bill Huang
This code makes use of the SDM fractional divider if present to
contrain the allowable programming range of the PLL divider register
bitfields to take advantage of higher frequency granularity that can
be induced by the SDM divider.
Based on original work by Aleksandr Frid
On Tegra210 SoC's, the logic to enable several of the plls is different
from previous generations. Therefore, add registeration functions specific
to Tegra210 which will handle them appropriately.
Signed-off-by: Rhyland Klein
---
drivers/clk/tegra/clk-pll.c | 332
This removes the conversion from pdiv to hw, which is already taken
care of by _get_table_rate before this code is run. This avoids
incorrectly converting pdiv to hw twice and getting the wrong hw value.
Signed-off-by: Rhyland Klein
---
drivers/clk/tegra/clk-pll.c |7 +--
1 file changed
Implement clock support for Tegra210.
Signed-off-by: Rhyland Klein
---
.../bindings/clock/nvidia,tegra210-car.txt | 56 +
drivers/clk/tegra/Makefile |1 +
drivers/clk/tegra/clk-id.h |4 +
drivers/clk/tegra/clk-tegra210.c
From: Bill Huang
Add some logic for Spread Spectrum control. It is used in conjuncture
with SDM fractional dividers. SSC has to be disabled when we configure
the divider settings.
Signed-off-by: Bill Huang
---
drivers/clk/tegra/clk-pll.c | 25 -
From: Bill Huang
Super clock divider control and clock source mux of Tegra210 has changed
a little against prior SoCs, this patch adds Gen5 logic to address those
differences.
Signed-off-by: Bill Huang
---
drivers/clk/tegra/Makefile |1 +
ent
clk: tegra: pll: Add dyn_ramp callback
clk: tegra: pll: Add Set_default logic
clk: tegra: Add Super Gen5 Logic
Rhyland Klein (12):
clk: tegra: Modify tegra_audio_clk_init to accept more plls
clk: tegra: periph: add new periph clks and muxes for Tegra210
clk: tegra: pll:
tegra_audio_clk_init was written expecting a single PLL to be
passed in directly. Change this to accept an array which will
allow for supporting multiple plls and specifying specific data
about them, like their parent, which may change over time.
Signed-off-by: Rhyland Klein
---
drivers/clk
Swap out the generic WARN_ON with a WARN which gives more
information about what is happening.
Signed-off-by: Rhyland Klein
---
drivers/clk/tegra/clk-pll.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index
Instead of having multiple similar wrapper functions for
_clk_pll_[enable|disable], we can simplify it to single
wrappers and use checks to avoid the logic we don't want to use.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
drivers/clk/tegra/clk-pll.c | 79
.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
drivers/clk/tegra/clk-pll.c | 11 ++-
drivers/clk/tegra/clk-tegra114.c | 23 +--
drivers/clk/tegra/clk-tegra124.c | 24 +++-
drivers/clk/tegra/clk-tegra20.c | 18
This adds logic for taking SDM_DIN (Sigma Delta Modulator) setting into
the equation to calculate the effective N value for PLL which supports
fractional divider.
The effective N = NDIV + 1/2 + SDM_DIN/2^13, where NDIV is the integer
feedback divider.
Signed-off-by: Rhyland Klein rkl
-by: Rhyland Klein rkl...@nvidia.com
---
drivers/clk/tegra/clk-pll.c | 24 ++--
drivers/clk/tegra/clk.h | 10 ++
2 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 806ae48020e5..f612a8b65651
From: Bill Huang bilhu...@nvidia.com
New SoC's may have more then 3 MISC registers, so bump up the
array size and use a #define to be more informative about the value.
Signed-off-by: Bill Huang bilhu...@nvidia.com
---
drivers/clk/tegra/clk.h |4 +++-
1 file changed, 3 insertions(+), 1
Tegra210 SoC's have a backup PLL for memory usage, PLLMB. Add
plumbing to register and handle it.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
drivers/clk/tegra/clk-pll.c | 46 +++
drivers/clk/tegra/clk.h |9 +
2 files changed, 51
From: Bill Huang bilhu...@nvidia.com
If a PLL has a reset_reg specified, properly handle that in the
enable/disable logic paths._
Signed-off-by: Bill Huang bilhu...@nvidia.com
---
drivers/clk/tegra/clk-pll.c | 12
drivers/clk/tegra/clk.h |2 ++
2 files changed, 14
From: Bill Huang bilhu...@nvidia.com
Add logic which (if specified for a pll) can verify that a PLL is set
to the proper default value and if not can set it. This can be
specified per PLL as each will have different default values.
Signed-off-by: Bill Huang bilhu...@nvidia.com
---
From: Bill Huang bilhu...@nvidia.com
Add a callback to the pll_params for custom dynamic ramping
functions which can be specified per PLL.
Signed-off-by: Bill Huang bilhu...@nvidia.com
---
drivers/clk/tegra/clk.h |4
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/tegra/clk.h
From: Bill Huang bilhu...@nvidia.com
This code makes use of the SDM fractional divider if present to
contrain the allowable programming range of the PLL divider register
bitfields to take advantage of higher frequency granularity that can
be induced by the SDM divider.
Based on original work by
On Tegra210 SoC's, the logic to enable several of the plls is different
from previous generations. Therefore, add registeration functions specific
to Tegra210 which will handle them appropriately.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
drivers/clk/tegra/clk-pll.c | 332
Implement clock support for Tegra210.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
.../bindings/clock/nvidia,tegra210-car.txt | 56 +
drivers/clk/tegra/Makefile |1 +
drivers/clk/tegra/clk-id.h |4 +
drivers/clk/tegra/clk
From: Bill Huang bilhu...@nvidia.com
Add some logic for Spread Spectrum control. It is used in conjuncture
with SDM fractional dividers. SSC has to be disabled when we configure
the divider settings.
Signed-off-by: Bill Huang bilhu...@nvidia.com
---
drivers/clk/tegra/clk-pll.c | 25
This removes the conversion from pdiv to hw, which is already taken
care of by _get_table_rate before this code is run. This avoids
incorrectly converting pdiv to hw twice and getting the wrong hw value.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
drivers/clk/tegra/clk-pll.c |7
From: Bill Huang bilhu...@nvidia.com
Super clock divider control and clock source mux of Tegra210 has changed
a little against prior SoCs, this patch adds Gen5 logic to address those
differences.
Signed-off-by: Bill Huang bilhu...@nvidia.com
---
drivers/clk/tegra/Makefile |1 +
tegra_audio_clk_init was written expecting a single PLL to be
passed in directly. Change this to accept an array which will
allow for supporting multiple plls and specifying specific data
about them, like their parent, which may change over time.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
clk: tegra: pll: Add dyn_ramp callback
clk: tegra: pll: Add Set_default logic
clk: tegra: Add Super Gen5 Logic
Rhyland Klein (12):
clk: tegra: Modify tegra_audio_clk_init to accept more plls
clk: tegra: periph: add new periph clks and muxes for Tegra210
clk: tegra: pll: add
Swap out the generic WARN_ON with a WARN which gives more
information about what is happening.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
drivers/clk/tegra/clk-pll.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra
Tegra210 has significant differences in muxes for peripheral clocks.
One of the most important changes is that pll_m isn't to be used
as a source for peripherals. Therefore, we need to define the new
muxes and new clocks to use those muxes for Tegra210 support.
Signed-off-by: Rhyland Klein rkl
Create a wrapper interface to make use of the existing
clk_pll_wait_for_lock. This will be useful for implementations
of callbacks in Tegra SoC specific clock drivers.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
drivers/clk/tegra/clk-pll.c |5 +
drivers/clk/tegra/clk.h |1
Some fields moved from the tegra_clk_pll struct to
the tegra_pll_params struct. Update the struct comments
to reflect where the fields really are.
Signed-off-by: Rhyland Klein
---
drivers/clk/tegra/clk.h | 74 +++
1 file changed, 37 insertions
Some fields moved from the tegra_clk_pll struct to
the tegra_pll_params struct. Update the struct comments
to reflect where the fields really are.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
drivers/clk/tegra/clk.h | 74 +++
1 file changed, 37
> Signed-off-by: Mans Rullgard
> Cc: Rhyland Klein
> ---
> drivers/clk/clk.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index d48ac71..bc0662b 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/c
: Rhyland Klein rkl...@nvidia.com
---
drivers/clk/clk.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index d48ac71..bc0662b 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1950,7 +1950,8 @@ int __clk_init(struct device
I saw a series of patches posted last year by Ambresh which addresses
(at least mostly) changing the return type of clk_mux_get_parent.
Namely, this series changing it to an int from an u8.
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-June/179367.html
I am running into this error
I saw a series of patches posted last year by Ambresh which addresses
(at least mostly) changing the return type of clk_mux_get_parent.
Namely, this series changing it to an int from an u8.
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-June/179367.html
I am running into this error
On 2/11/2015 10:50 PM, Alexandre Courbot wrote:
> On Thu, Feb 12, 2015 at 2:55 AM, Rhyland Klein wrote:
>> Setup a different set of sdhci_ops for tegra114 and later so that
>> the write_w callback is only used on tegra114. This allows us to
>> remove the NVQUIRK_SHADOW_XFE
On 2/11/2015 10:50 PM, Alexandre Courbot wrote:
On Thu, Feb 12, 2015 at 2:55 AM, Rhyland Klein rkl...@nvidia.com wrote:
Setup a different set of sdhci_ops for tegra114 and later so that
the write_w callback is only used on tegra114. This allows us to
remove the NVQUIRK_SHADOW_XFER_MODE_REG
Setup a different set of sdhci_ops for tegra114 and later so that
the write_w callback is only used on tegra114. This allows us to
remove the NVQUIRK_SHADOW_XFER_MODE_REG and simply the logic
in tegra_sdhci_writew.
This was suggested by Alexandre Courbot.
Signed-off-by: Rhyland Klein
Setup a different set of sdhci_ops for tegra114 and later so that
the write_w callback is only used on tegra114. This allows us to
remove the NVQUIRK_SHADOW_XFER_MODE_REG and simply the logic
in tegra_sdhci_writew.
This was suggested by Alexandre Courbot.
Signed-off-by: Rhyland Klein rkl
as an NVQUIRK as it applies to T114, T124 and
T132.
Signed-off-by: Pavan Kunapuli
Signed-off-by: Rhyland Klein
---
v2:
- Fixed quirk flag check s/*/&
- Removed line clearing xfer_mode_shadow
- Added explicit mention of which platforms this applies to in
description
drivers/mmc/
On 1/28/2015 1:06 AM, Alexandre Courbot wrote:
> On Wed, Jan 28, 2015 at 2:23 AM, Rhyland Klein wrote:
>> From: Pavan Kunapuli
>>
>> If there is a gap between xfer mode and command register writes,
>> tegra SDMMC controller can sometimes issue a spurious command
.
This is implemented as an NVQUIRK as it applies to T114, T124 and
T132.
Signed-off-by: Pavan Kunapuli pkunap...@nvidia.com
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
v2:
- Fixed quirk flag check s/*/
- Removed line clearing xfer_mode_shadow
- Added explicit mention of which platforms
On 1/28/2015 1:06 AM, Alexandre Courbot wrote:
On Wed, Jan 28, 2015 at 2:23 AM, Rhyland Klein rkl...@nvidia.com wrote:
From: Pavan Kunapuli pkunap...@nvidia.com
If there is a gap between xfer mode and command register writes,
tegra SDMMC controller can sometimes issue a spurious command
-by: Pavan Kunapuli
Signed-off-by: Rhyland Klein
---
drivers/mmc/host/sdhci-tegra.c | 31 ++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 59797106af93..3d34de47e57e 100644
--- a/drivers
.
Signed-off-by: Pavan Kunapuli pkunap...@nvidia.com
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
drivers/mmc/host/sdhci-tegra.c | 31 ++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
On 7/15/2014 4:35 PM, Rhyland Klein wrote:
> On 7/15/2014 11:24 AM, Peter De Schrijver wrote:
>> Add support for the ccplex clocks in Tegra132.
>>
>> Signed-off-by: Peter De Schrijver
>> ---
>> drivers/clk/tegra/Makefile |2 ++
>> 1 files changed, 2 i
On 7/15/2014 11:24 AM, Peter De Schrijver wrote:
> Add support for the ccplex clocks in Tegra132.
>
> Signed-off-by: Peter De Schrijver
> ---
> drivers/clk/tegra/Makefile |2 ++
> 1 files changed, 2 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/clk/tegra/Makefile
On 7/15/2014 11:24 AM, Peter De Schrijver wrote:
Add support for the ccplex clocks in Tegra132.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
drivers/clk/tegra/Makefile |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/drivers/clk/tegra/Makefile
On 7/15/2014 4:35 PM, Rhyland Klein wrote:
On 7/15/2014 11:24 AM, Peter De Schrijver wrote:
Add support for the ccplex clocks in Tegra132.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
drivers/clk/tegra/Makefile |2 ++
1 files changed, 2 insertions(+), 0 deletions
On 11/26/2013 5:05 AM, Mika Westerberg wrote:
> From: Heikki Krogerus
>
> This makes it possible to request the gpio descriptors in
> rfkill_gpio driver regardless of the platform.
>
> Signed-off-by: Heikki Krogerus
> Signed-off-by: Mika Westerberg
> Tested-by: Stephen Warren
> ---
>
On 11/26/2013 5:05 AM, Mika Westerberg wrote:
From: Heikki Krogerus heikki.kroge...@linux.intel.com
This makes it possible to request the gpio descriptors in
rfkill_gpio driver regardless of the platform.
Signed-off-by: Heikki Krogerus heikki.kroge...@linux.intel.com
Signed-off-by: Mika
On 11/19/2013 3:42 AM, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Mon, Nov 18, 2013 at 11:48:10AM +, Mark Rutland wrote:
>> On Mon, Nov 18, 2013 at 10:30:47AM +, Thierry Reding wrote:
>>> From: Rhyland Klein
>>>
>>> The EC ha
On 11/19/2013 3:42 AM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Mon, Nov 18, 2013 at 11:48:10AM +, Mark Rutland wrote:
On Mon, Nov 18, 2013 at 10:30:47AM +, Thierry Reding wrote:
From: Rhyland Klein rkl...@nvidia.com
The EC has specific timing it requires. Add
On 10/14/2013 2:21 PM, Stephen Warren wrote:
> On 10/11/2013 03:15 PM, Rhyland Klein wrote:
>> From: Darbha Sriharsha
>>
>> Adds support for the bq24735 charger chipset. The bq24735 is a
>> high-efficiency, synchronous battery charger.
>>
>> It allows
On 10/14/2013 2:21 PM, Stephen Warren wrote:
On 10/11/2013 03:15 PM, Rhyland Klein wrote:
From: Darbha Sriharsha dsrihar...@nvidia.com
Adds support for the bq24735 charger chipset. The bq24735 is a
high-efficiency, synchronous battery charger.
It allows control of the charging current
From: Darbha Sriharsha
Adds support for the bq24735 charger chipset. The bq24735 is a
high-efficiency, synchronous battery charger.
It allows control of the charging current, input current, and the charger
voltage DAC's through SMBus.
Signed-off-by: Darbha Sriharsha
Signed-off-by: Rhyland
dsrihar...@nvidia.com
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
v5:
- Clarified ti,charge-[current/voltage] and input-current properties in
documentation
v4:
- Added GPIO # to dev_err when gpio_request fails, for verbosity.
v3:
*Note: I decided to maintain non-DT support, but tried to do
; -}
> -#endif
>
> static int tps65090_charger_probe(struct platform_device *pdev)
> {
> @@ -228,7 +219,7 @@ static int tps65090_charger_probe(struct platform_device
> *pdev)
>
> pdata = dev_get_platdata(pdev->dev.parent);
>
> - if (!pdata &&
)
pdata = tps65090_parse_dt_charger_data(pdev);
if (!pdata) {
LGTM
Acked-by: Rhyland Klein rkl...@nvidia.com
--
nvpublic
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info
driver.
Signed-off-by: Rhyland Klein
---
v2:
- Split start_transfer_one into setup & start, now setup it always safe
to call, and we can simplify the checks for a transfer with no length.
- removed unnecessary whitespace changes
- I also cleaned up the parame
From: Darbha Sriharsha
Adds support for the bq24735 charger chipset. The bq24735 is a
high-efficiency, synchronous battery charger.
It allows control of the charging current, input current, and the charger
voltage DAC's through SMBus.
Signed-off-by: Darbha Sriharsha
Signed-off-by: Rhyland
dsrihar...@nvidia.com
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
v4:
- Added GPIO # to dev_err when gpio_request fails, for verbosity.
v3:
*Note: I decided to maintain non-DT support, but tried to do it in the most
clean manner using the suggestions from Thierry Reding.
- Simplified devicetree
driver.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
v2:
- Split start_transfer_one into setup start, now setup it always safe
to call, and we can simplify the checks for a transfer with no length.
- removed unnecessary whitespace changes
- I also cleaned up the parameters
From: Darbha Sriharsha
Adds support for the bq24735 charger chipset. The bq24735 is a
high-efficiency, synchronous battery charger.
It allows control of the charging current, input current, and the charger
voltage DAC's through SMBus.
Signed-off-by: Darbha Sriharsha
Signed-off-by: Rhyland
On 9/20/2013 3:53 AM, Thierry Reding wrote:
+ name = charger_device->pdata->name;
+ if (!name) {
+ name = kasprintf(GFP_KERNEL, "bq24735-%s",
+ dev_name(>dev));
>>>
>>> Won't the device name already include bq24735 because of the
On 9/23/2013 6:05 PM, Stephen Warren wrote:
> On 09/23/2013 04:01 PM, Rhyland Klein wrote:
>> On 9/23/2013 5:53 PM, Stephen Warren wrote:
>>> On 09/19/2013 10:18 AM, Rhyland Klein wrote:
>>>> Adding driver support for bq24735 charger chipset.
>>>
>>>
On 9/23/2013 7:08 PM, Trent Piepho wrote:
> On Mon, Sep 23, 2013 at 2:14 PM, Stephen Warren wrote:
>>
>> That sounds broken. Normally, shouldn't CS assert before a transaction,
>> stay asserted during a transaction, then deassert after the transaction?
>> It shouldn't rise and fall very quickly
On 9/23/2013 7:08 PM, Trent Piepho wrote:
On Mon, Sep 23, 2013 at 2:14 PM, Stephen Warren swar...@wwwdotorg.org wrote:
That sounds broken. Normally, shouldn't CS assert before a transaction,
stay asserted during a transaction, then deassert after the transaction?
It shouldn't rise and fall
On 9/23/2013 6:05 PM, Stephen Warren wrote:
On 09/23/2013 04:01 PM, Rhyland Klein wrote:
On 9/23/2013 5:53 PM, Stephen Warren wrote:
On 09/19/2013 10:18 AM, Rhyland Klein wrote:
Adding driver support for bq24735 charger chipset.
diff --git a/Documentation/devicetree/bindings/power_supply/ti
On 9/20/2013 3:53 AM, Thierry Reding wrote:
+ name = charger_device-pdata-name;
+ if (!name) {
+ name = kasprintf(GFP_KERNEL, bq24735-%s,
+ dev_name(client-dev));
Won't the device name already include bq24735 because of the driver
name?
In
dsrihar...@nvidia.com
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
*Note: I decided to maintain non-DT support, but tried to do it in the most
clean manner using the suggestions from Thierry Reding.
v3:
- Simplified devicetree bindings for charger current/voltage and input current
- added
On 9/23/2013 5:53 PM, Stephen Warren wrote:
> On 09/19/2013 10:18 AM, Rhyland Klein wrote:
>> Adding driver support for bq24735 charger chipset.
>
>> diff --git a/Documentation/devicetree/bindings/power_supply/ti,bq24735.txt
>> b/Documentation/devicetree/bindings/pow
On 9/23/2013 3:58 PM, Stephen Warren wrote:
> On 09/23/2013 01:48 PM, Rhyland Klein wrote:
>> On 9/23/2013 2:51 PM, Stephen Warren wrote:
>>> On 09/18/2013 12:17 PM, Rhyland Klein wrote:
>>>> The tegra114 driver wasn't currently handling the cs_change functionali
On 9/23/2013 2:51 PM, Stephen Warren wrote:
> On 09/18/2013 12:17 PM, Rhyland Klein wrote:
>> The tegra114 driver wasn't currently handling the cs_change functionality.
>> It is meant to invert normal behavior, and we were only using it to possibly
>> delay at the end of a t
On 9/23/2013 2:51 PM, Stephen Warren wrote:
On 09/18/2013 12:17 PM, Rhyland Klein wrote:
The tegra114 driver wasn't currently handling the cs_change functionality.
It is meant to invert normal behavior, and we were only using it to possibly
delay at the end of a transfer.
I don't really
On 9/23/2013 3:58 PM, Stephen Warren wrote:
On 09/23/2013 01:48 PM, Rhyland Klein wrote:
On 9/23/2013 2:51 PM, Stephen Warren wrote:
On 09/18/2013 12:17 PM, Rhyland Klein wrote:
The tegra114 driver wasn't currently handling the cs_change functionality.
It is meant to invert normal behavior
On 9/23/2013 5:53 PM, Stephen Warren wrote:
On 09/19/2013 10:18 AM, Rhyland Klein wrote:
Adding driver support for bq24735 charger chipset.
diff --git a/Documentation/devicetree/bindings/power_supply/ti,bq24735.txt
b/Documentation/devicetree/bindings/power_supply/ti,bq24735.txt
+Optional
On 9/20/2013 3:53 AM, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Thu, Sep 19, 2013 at 04:45:11PM -0400, Rhyland Klein wrote:
>> On 9/19/2013 4:27 PM, Thierry Reding wrote:
>>>> Old Signed by an unknown key
>>>
>>> On Thu, Sep 19,
On 9/20/2013 3:53 AM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Thu, Sep 19, 2013 at 04:45:11PM -0400, Rhyland Klein wrote:
On 9/19/2013 4:27 PM, Thierry Reding wrote:
Old Signed by an unknown key
On Thu, Sep 19, 2013 at 12:18:33PM -0400, Rhyland Klein wrote:
From: Darbha
501 - 600 of 762 matches
Mail list logo
