[PATCHv1] Add reset manager offsets for Stratix10

From: Richard Gong <richard.g...@intel.com> There are several changes in reset manager offsets from Arria10 to stratix10. This patch is derived from Steffen Trumtrar's "altr,rst-mgr-a10.h" and adds additional offset updates for Stratix10 Richard Gong (1): dt-bindings: reset: A

[PATCHv1] dt-bindings: reset: Add reset manager offsets for Stratix10

From: Richard Gong <richard.g...@intel.com> There are several changes in reset manager offsets from Arria10 to Stratix10. This patch is based on one from Arria10 and adds offset updates for Stratix10 Signed-off-by: Richard Gong <richard.g...@intel.com> --- include/dt-bindings/reset/

[PATCHv4 1/7] dt-bindings, firmware: add Intel Stratix10 service layer binding

From: Richard Gong <richard.g...@intel.com> Add a device tree binding for the Intel Stratix10 service layer driver Signed-off-by: Richard Gong <richard.g...@intel.com> Signed-off-by: Alan Tull <at...@kernel.org> Reviewed-by: Rob Herring <r...@kernel.org> --- v2: Cha

[PATCHv4 2/7] arm64: dts: stratix10: add stratix10 service driver binding to base dtsi

From: Richard Gong <richard.g...@intel.com> Add Intel Stratix10 service layer to the device tree Signed-off-by: Richard Gong <richard.g...@intel.com> Signed-off-by: Alan Tull <at...@kernel.org> --- v2: Change to put service layer driver node under the firmware node

[PATCHv4 3/7] driver, misc: add Intel Stratix10 service layer driver

From: Richard Gong <richard.g...@intel.com> Some features of the Intel Stratix10 SoC require a level of privilege higher than the kernel is granted. Such secure features include FPGA programming. In terms of the ARMv8 architecture, the kernel runs at Exception Level 1 (EL1),

[PATCHv4 0/7] Add Intel Stratix10 FPGA manager and service layer

From: Richard Gong <richard.g...@intel.com> This is the 4th submission of Intel stratix10 service layer patches. Intel Stratix10 FPGA manager, which is 1st Stratix10 service layer client, is included in this submission. Stratix10 service layer patches have been reviewed internally by Ala

[PATCHv4 6/7] fpga: add intel stratix10 soc fpga manager driver

n Tull <at...@kernel.org> Signed-off-by: Richard Gong <richard.g...@intel.com> --- v2: this patch is added in patch set version 2 v3: change to align to the update of service client APIs, and the update of fpga_mgr device node v4: changes to align with stratix10-svc-client API updates

[PATCHv4 5/7] arm64: dts: stratix10: add fpga manager and region

From: Alan Tull <at...@kernel.org> Add the Stratix10 FPGA manager and a FPGA region to the device tree. Signed-off-by: Alan Tull <at...@kernel.org> Signed-off-by: Richard Gong <richard.g...@intel.com> --- v2: this patch is added in patch set version 2 v3: change to put f

[PATCHv4 7/7] defconfig: enable fpga and service layer

From: Richard Gong <richard.g...@intel.com> Enable fpga framework, Stratix 10 SoC FPGA manager and Stratix10 Service Layer Signed-off-by: Richard Gong <richard.g...@intel.com> Signed-off-by: Alan Tull <at...@kernel.org> --- v2: this patch is added in patch set version 2 v

[PATCHv4 4/7] dt-bindings: fpga: add Stratix10 SoC FPGA manager binding

From: Alan Tull <at...@kernel.org> Add a Device Tree binding for the Intel Stratix10 SoC FPGA manager. Signed-off-by: Alan Tull <at...@kernel.org> Signed-off-by: Richard Gong <richard.g...@intel.com> --- v2: this patch is added in patch set version 2 v3: change to put f

[PATCHv5 3/8] driver, misc: add Intel Stratix10 service layer driver

From: Richard Gong <richard.g...@intel.com> Some features of the Intel Stratix10 SoC require a level of privilege higher than the kernel is granted. Such secure features include FPGA programming. In terms of the ARMv8 architecture, the kernel runs at Exception Level 1 (EL1),

[PATCHv5 6/8] fpga: add intel stratix10 soc fpga manager driver

n Tull <at...@kernel.org> Signed-off-by: Richard Gong <richard.g...@intel.com> --- v2: this patch is added in patch set version 2 v3: change to align to the update of service client APIs, and the update of fpga_mgr device node v4: changes to align with stratix10-svc-client API updates

[PATCHv5 7/8] defconfig: enable fpga and service layer

From: Richard Gong <richard.g...@intel.com> Enable fpga framework, Stratix 10 SoC FPGA manager and Stratix10 Service Layer Signed-off-by: Richard Gong <richard.g...@intel.com> Signed-off-by: Alan Tull <at...@kernel.org> --- v2: this patch is added in patch set version 2 v

[PATCHv5 4/8] dt-bindings: fpga: add Stratix10 SoC FPGA manager binding

From: Alan Tull <at...@kernel.org> Add a Device Tree binding for the Intel Stratix10 SoC FPGA manager. Signed-off-by: Alan Tull <at...@kernel.org> Signed-off-by: Richard Gong <richard.g...@intel.com> Reviewed-by: Rob Herring <r...@kernel.org> --- v2: this patch is added i

[PATCHv5 2/8] arm64: dts: stratix10: add stratix10 service driver binding to base dtsi

From: Richard Gong <richard.g...@intel.com> Add Intel Stratix10 service layer to the device tree Signed-off-by: Richard Gong <richard.g...@intel.com> Signed-off-by: Alan Tull <at...@kernel.org> --- v2: Change to put service layer driver node under the firmware node

[PATCHv5 0/8] Add Intel Stratix10 FPGA manager and service layer

From: Richard Gong <richard.g...@intel.com> This is the 5th submission of Intel stratix10 service layer patches. Intel Stratix10 FPGA manager, which is 1st Stratix10 service layer client, is included in this submission. Stratix10 service layer patches have been reviewed internally by Ala

[PATCHv5 1/8] dt-bindings, firmware: add Intel Stratix10 service layer binding

From: Richard Gong <richard.g...@intel.com> Add a device tree binding for the Intel Stratix10 service layer driver Signed-off-by: Richard Gong <richard.g...@intel.com> Signed-off-by: Alan Tull <at...@kernel.org> Reviewed-by: Rob Herring <r...@kernel.org> --- v2: Cha

[PATCHv5 5/8] arm64: dts: stratix10: add fpga manager and region

From: Alan Tull <at...@kernel.org> Add the Stratix10 FPGA manager and a FPGA region to the device tree. Signed-off-by: Alan Tull <at...@kernel.org> Signed-off-by: Richard Gong <richard.g...@intel.com> --- v2: this patch is added in patch set version 2 v3: change to put f

[PATCHv5 8/8] Documentation: driver-api: add stratix10 service layer

From: Richard Gong <richard.g...@intel.com> Add new file stratix10-svc.rst Add stratix10-svc.rst to driver-api/index.rst Signed-off-by: Richard Gong <richard.g...@intel.com> Signed-off-by: Alan Tull <at...@kernel.org> --- v5: this patch is added in patch set version 5 --- Do

[PATCHv1] driver: misc: add Intel Stratix10 service layer driver

From: Richard Gong <richard.g...@intel.com> Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard processor system (HPS) and Secure Device Manager (SDM). SDM is the hardware which does the FPGA configuration, QSPI, Crypto and warm reset. When the FPGA is configured fr

[PATCHv1] Add Intel Stratix10 service layer driver

From: Richard Gong <richard.g...@intel.com> Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard processor system (HPS) and Secure Device Manager (SDM). SDM is the hardware which does the FPGA configuration, QSPI, Crypto and warm reset. When the FPGA is configured fr

Re: [PATCHv1] dt-bindings: misc: add Intel Stratix10 service layer binding

On 01/30/2018 10:57 AM, Rob Herring wrote: On Tue, Jan 23, 2018 at 01:25:02PM -0600, richard.g...@linux.intel.com wrote: From: Richard Gong <richard.g...@intel.com> Add a device tree binding for the Intel Stratix10 service layer driver Signed-off-by: Richard Gong <richard.g...@

Re: [PATCHv1] Add Intel Stratix10 service layer driver

Hi Greg, Many thanks for your reviews. On 01/25/2018 10:53 AM, Greg KH wrote: On Thu, Jan 25, 2018 at 10:39:03AM -0600, richard.g...@linux.intel.com wrote: From: Richard Gong <richard.g...@intel.com> Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard processor

[PATCHv7 8/9] Documentation: driver-api: add stratix10 service layer

From: Richard Gong Add new file stratix10-svc.rst Add stratix10-svc.rst to driver-api/index.rst Signed-off-by: Richard Gong Signed-off-by: Alan Tull --- v5: this patch is added in patch set version 5 v6: no change v7: no change --- Documentation/driver-api/index.rst | 1

[PATCHv7 6/9] fpga: add intel stratix10 soc fpga manager driver

From: Alan Tull Add driver for reconfiguring Intel Stratix10 SoC FPGA devices. This driver communicates through the Intel Service Driver which does communication with privileged hardware (that does the FPGA programming) through a secure mailbox. Signed-off-by: Alan Tull Signed-off-by: Richard

[PATCHv7 5/9] arm64: dts: stratix10: add fpga manager and region

From: Alan Tull Add the Stratix10 FPGA manager and a FPGA region to the device tree. Signed-off-by: Alan Tull Signed-off-by: Richard Gong --- v2: this patch is added in patch set version 2 v3: change to put fpga_mgr node under firmware/svc node v4: s/fpga-mgr@0/fpga-mgr/ to remove

[PATCHv1] dt-bindings: misc: add Intel Stratix10 service layer binding

From: Richard Gong <richard.g...@intel.com> Add a device tree binding for the Intel Stratix10 service layer driver Signed-off-by: Richard Gong <richard.g...@intel.com> --- .../devicetree/bindings/misc/intel-service.txt | 56 ++ 1 file changed, 56 insertion

[PATCHv1] Add Intel Stratix10 service layer binding

From: Richard Gong <richard.g...@intel.com> Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard processor system (HPS) and Secure Device Manager (SDM). When the FPGA is configured from HPS, there needs to be a way for HPS to notify SDM the location an

[PATCHv3 3/7] driver, misc: add Intel Stratix10 service layer driver

From: Richard Gong <richard.g...@intel.com> Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard processor system (HPS) and Secure Device Manager (SDM). SDM is the hardware which does the FPGA configuration, QSPI, Crypto and warm reset. In order to configure the FPG

[PATCHv3 0/7] Add Intel Stratix10 FPGA manager and service layer

From: Richard Gong <richard.g...@intel.com> This is the 3rd submission of Intel service layer patches. Intel Stratix10 FPGA manager, which is 1st service layer client, is included in this submission. Service layer patches have been reviewed internally by Alan Tull and other colleagues at

[PATCHv3 2/7] arm64: dts: stratix10: add service driver binding to base dtsi

From: Richard Gong <richard.g...@intel.com> Add Intel Stratix10 service layer to the device tree Signed-off-by: Richard Gong <richard.g...@intel.com> Signed-off-by: Alan Tull <at...@kernel.org> --- v2: Change to put service layer driver node under the firmware node

[PATCHv3 1/7] dt-bindings, firmware: add Intel Stratix10 service layer binding

From: Richard Gong <richard.g...@intel.com> Add a device tree binding for the Intel Stratix10 service layer driver Signed-off-by: Richard Gong <richard.g...@intel.com> Signed-off-by: Alan Tull <at...@kernel.org> --- v2: Change to put service layer driver node under the firmwa

[PATCHv3 5/7] arm64: dts: stratix10: add fpga manager and region

From: Alan Tull Add the Stratix10 FPGA manager and a FPGA region to the device tree. Signed-off-by: Alan Tull --- v2: this patch is added in patch set version 2 v3: change to put fpga_mgr node under firmware/svc node ---

[PATCHv3 7/7] defconfig: enable fpga and service layer

From: Richard Gong <richard.g...@intel.com> Enable fpga framework, Stratix 10 SoC FPGA manager, and Intel Service Layer Signed-off-by: Richard Gong <richard.g...@intel.com> Signed-off-by: Alan Tull <at...@kernel.org> --- v2: this patch is added in patch set version 2 v3: n

[PATCHv3 6/7] fpga: add intel stratix10 soc fpga manager driver

From: Alan Tull Add driver for reconfiguring Intel Stratix10 SoC FPGA devices. This driver communicates through the Intel Service Driver which does communication with privileged hardware (that does the FPGA programming) through a secure mailbox. Signed-off-by: Alan Tull

[PATCHv3 4/7] dt-bindings: fpga: add Stratix10 SoC FPGA manager binding

From: Alan Tull Add a Device Tree binding for the Intel Stratix10 SoC FPGA manager. Signed-off-by: Alan Tull --- v2: this patch is added in patch set version 2 v3: change to put fpga_mgr node under firmware/svc node ---

[PATCHv2 3/7] driver, misc: add Intel Stratix10 service layer driver

From: Richard Gong <richard.g...@intel.com> Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard processor system (HPS) and Secure Device Manager (SDM). SDM is the hardware which does the FPGA configuration, QSPI, Crypto and warm reset. When the FPGA is configured fr

[PATCHv2 1/7] dt-bindings, firmware: add Intel Stratix10 service layer binding

From: Richard Gong <richard.g...@intel.com> Add a device tree binding for the Intel Stratix10 service layer driver Signed-off-by: Richard Gong <richard.g...@intel.com> Signed-off-by: Alan Tull <at...@kernel.org> --- v2: Change to put service layer driver node under the firmwa

[PATCHv2 4/7] dt-bindings: fpga: add Stratix10 SoC FPGA manager binding

From: Alan Tull Add a Device Tree binding for the Intel Stratix10 SoC FPGA manager. Signed-off-by: Alan Tull --- v2: this patch is added in patch set version 2 --- .../devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt | 10 ++ 1 file

[PATCHv2 7/7] defconfig: enable fpga and service layer

From: Richard Gong <richard.g...@intel.com> Enable fpga framework, Stratix 10 SoC FPGA manager, and Intel Service Layer Signed-off-by: Richard Gong <richard.g...@intel.com> Signed-off-by: Alan Tull <at...@kernel.org> --- v2: this patch is added in patch set version 2 ---

[PATCHv2 0/7] Add Intel Stratix10 FPGA manager and service layer

From: Richard Gong <richard.g...@intel.com> This is the 2nd submission of Intel service layer patches. Intel Stratix10 FPGA manager, which is 1st service layer client, is included in this submission. Service layer patches have been reviewed internally by Alan Tull and other colleagues at

[PATCHv2 5/7] arm64: dts: stratix10: add fpga manager and region

From: Alan Tull Add the Stratix10 FPGA manager and a FPGA region to the device tree. Signed-off-by: Alan Tull --- v2: this patch is added in patch set version 2 --- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 12 1 file changed, 12

[PATCHv2 6/7] fpga: add intel stratix10 soc fpga manager driver

From: Alan Tull Add driver for reconfiguring Intel Stratix10 SoC FPGA devices. This driver communicates through the Intel Service Driver which does communication with privileged hardware (that does the FPGA programming) through a secure mailbox. Signed-off-by: Alan Tull

[PATCHv2 2/7] arm64: dts: stratix10: add service driver binding to base dtsi

From: Richard Gong <richard.g...@intel.com> Add Intel Stratix10 service layer to the device tree Signed-off-by: Richard Gong <richard.g...@intel.com> Signed-off-by: Alan Tull <at...@kernel.org> --- v2: Change to put service layer driver node under the firmware node

[PATCHv10 0/8] Add Intel Stratix10 FPGA manager and service layer

From: Richard Gong This is the 10th submission of Intel Stratix10 service layer and FPGA manager driver patches. In this submission I have moved Stratix10 service layer driver .c file to drivers/firmware and header files to include/linux/firmware/intel. I have added Stratix10 service layer

[PATCHv10 2/8] arm64: dts: stratix10: add stratix10 service driver binding to base dtsi

From: Richard Gong Add Intel Stratix10 service layer to the device tree Signed-off-by: Richard Gong Signed-off-by: Alan Tull Acked-by: Moritz Fischer --- v2: change to put service layer driver node under the firmware node change compatible to "intel, stratix10-svc" v3: no ch

[PATCHv11 0/8] Add Intel Stratix10 FPGA manager and service layer

From: Richard Gong This is the 11th submission of Intel Stratix10 service layer and FPGA manager driver patches. Starting from 10th submission Stratix10 service layer driver .c file is moved to drivers/firmware, header files is moved to include/linux/firmware/intel. And other firmware interface

[PATCHv2 2/7] arm64: dts: stratix10: add service driver binding to base dtsi

From: Richard Gong Add Intel Stratix10 service layer to the device tree Signed-off-by: Richard Gong Signed-off-by: Alan Tull --- v2: Change to put service layer driver node under the firmware node Change compatible to "intel, stratix10-svc" --- arch/arm64/boot/

[PATCHv2 5/7] arm64: dts: stratix10: add fpga manager and region

From: Alan Tull Add the Stratix10 FPGA manager and a FPGA region to the device tree. Signed-off-by: Alan Tull --- v2: this patch is added in patch set version 2 --- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 12 1 file changed, 12 insertions(+) diff --git

[PATCHv2 6/7] fpga: add intel stratix10 soc fpga manager driver

From: Alan Tull Add driver for reconfiguring Intel Stratix10 SoC FPGA devices. This driver communicates through the Intel Service Driver which does communication with privileged hardware (that does the FPGA programming) through a secure mailbox. Signed-off-by: Alan Tull --- v2: this patch is

[PATCHv2 1/7] dt-bindings, firmware: add Intel Stratix10 service layer binding

From: Richard Gong Add a device tree binding for the Intel Stratix10 service layer driver Signed-off-by: Richard Gong Signed-off-by: Alan Tull --- v2: Change to put service layer driver node under the firmware node Change compatible to "intel, stratix10-svc" --- .../binding

[PATCHv2 4/7] dt-bindings: fpga: add Stratix10 SoC FPGA manager binding

From: Alan Tull Add a Device Tree binding for the Intel Stratix10 SoC FPGA manager. Signed-off-by: Alan Tull --- v2: this patch is added in patch set version 2 --- .../devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt | 10 ++ 1 file changed, 10 insertions(+) create mode

[PATCHv2 7/7] defconfig: enable fpga and service layer

From: Richard Gong Enable fpga framework, Stratix 10 SoC FPGA manager, and Intel Service Layer Signed-off-by: Richard Gong Signed-off-by: Alan Tull --- v2: this patch is added in patch set version 2 --- arch/arm64/configs/defconfig | 5 + 1 file changed, 5 insertions(+) diff --git

[PATCHv2 3/7] driver, misc: add Intel Stratix10 service layer driver

From: Richard Gong Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard processor system (HPS) and Secure Device Manager (SDM). SDM is the hardware which does the FPGA configuration, QSPI, Crypto and warm reset. When the FPGA is configured from HPS, there needs to be a way

[PATCHv2 0/7] Add Intel Stratix10 FPGA manager and service layer

From: Richard Gong This is the 2nd submission of Intel service layer patches. Intel Stratix10 FPGA manager, which is 1st service layer client, is included in this submission. Service layer patches have been reviewed internally by Alan Tull and other colleagues at Intel. Intel Stratix10 SoC

[PATCHv3 1/7] dt-bindings, firmware: add Intel Stratix10 service layer binding

From: Richard Gong Add a device tree binding for the Intel Stratix10 service layer driver Signed-off-by: Richard Gong Signed-off-by: Alan Tull --- v2: Change to put service layer driver node under the firmware node Change compatible to "intel, stratix10-svc" v3:

[PATCHv3 0/7] Add Intel Stratix10 FPGA manager and service layer

From: Richard Gong This is the 3rd submission of Intel service layer patches. Intel Stratix10 FPGA manager, which is 1st service layer client, is included in this submission. Service layer patches have been reviewed internally by Alan Tull and other colleagues at Intel. Intel Stratix10 SoC

[PATCHv3 2/7] arm64: dts: stratix10: add service driver binding to base dtsi

From: Richard Gong Add Intel Stratix10 service layer to the device tree Signed-off-by: Richard Gong Signed-off-by: Alan Tull --- v2: Change to put service layer driver node under the firmware node Change compatible to "intel, stratix10-svc" v3: No change --- arch/arm64/boot/

[PATCHv3 3/7] driver, misc: add Intel Stratix10 service layer driver

From: Richard Gong Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard processor system (HPS) and Secure Device Manager (SDM). SDM is the hardware which does the FPGA configuration, QSPI, Crypto and warm reset. In order to configure the FPGA from HPS, there needs

[PATCHv3 7/7] defconfig: enable fpga and service layer

From: Richard Gong Enable fpga framework, Stratix 10 SoC FPGA manager, and Intel Service Layer Signed-off-by: Richard Gong Signed-off-by: Alan Tull --- v2: this patch is added in patch set version 2 v3: no change --- arch/arm64/configs/defconfig | 5 + 1 file changed, 5 insertions

[PATCHv3 6/7] fpga: add intel stratix10 soc fpga manager driver

From: Alan Tull Add driver for reconfiguring Intel Stratix10 SoC FPGA devices. This driver communicates through the Intel Service Driver which does communication with privileged hardware (that does the FPGA programming) through a secure mailbox. Signed-off-by: Alan Tull --- v2: this patch is

[PATCHv3 4/7] dt-bindings: fpga: add Stratix10 SoC FPGA manager binding

From: Alan Tull Add a Device Tree binding for the Intel Stratix10 SoC FPGA manager. Signed-off-by: Alan Tull --- v2: this patch is added in patch set version 2 v3: change to put fpga_mgr node under firmware/svc node --- .../bindings/fpga/intel-stratix10-soc-fpga-mgr.txt | 17

[PATCHv3 5/7] arm64: dts: stratix10: add fpga manager and region

From: Alan Tull Add the Stratix10 FPGA manager and a FPGA region to the device tree. Signed-off-by: Alan Tull --- v2: this patch is added in patch set version 2 v3: change to put fpga_mgr node under firmware/svc node --- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 12 1

[PATCHv4 0/7] Add Intel Stratix10 FPGA manager and service layer

From: Richard Gong This is the 4th submission of Intel stratix10 service layer patches. Intel Stratix10 FPGA manager, which is 1st Stratix10 service layer client, is included in this submission. Stratix10 service layer patches have been reviewed internally by Alan Tull and other colleagues

[PATCHv4 1/7] dt-bindings, firmware: add Intel Stratix10 service layer binding

From: Richard Gong Add a device tree binding for the Intel Stratix10 service layer driver Signed-off-by: Richard Gong Signed-off-by: Alan Tull Reviewed-by: Rob Herring --- v2: Change to put service layer driver node under the firmware node Change compatible to "intel, stratix10-sv

[PATCHv4 2/7] arm64: dts: stratix10: add stratix10 service driver binding to base dtsi

From: Richard Gong Add Intel Stratix10 service layer to the device tree Signed-off-by: Richard Gong Signed-off-by: Alan Tull --- v2: Change to put service layer driver node under the firmware node Change compatible to "intel, stratix10-svc" v3: No change v4: s/service driver

[PATCHv4 3/7] driver, misc: add Intel Stratix10 service layer driver

From: Richard Gong Some features of the Intel Stratix10 SoC require a level of privilege higher than the kernel is granted. Such secure features include FPGA programming. In terms of the ARMv8 architecture, the kernel runs at Exception Level 1 (EL1), access to the features requires Exception

[PATCHv4 5/7] arm64: dts: stratix10: add fpga manager and region

From: Alan Tull Add the Stratix10 FPGA manager and a FPGA region to the device tree. Signed-off-by: Alan Tull Signed-off-by: Richard Gong --- v2: this patch is added in patch set version 2 v3: change to put fpga_mgr node under firmware/svc node v4: s/fpga-mgr@0/fpga-mgr/ to remove

[PATCHv4 7/7] defconfig: enable fpga and service layer

From: Richard Gong Enable fpga framework, Stratix 10 SoC FPGA manager and Stratix10 Service Layer Signed-off-by: Richard Gong Signed-off-by: Alan Tull --- v2: this patch is added in patch set version 2 v3: no change v4: s/CONFIG_INTEL_SERVICE/CONFIG_STRATIX10_SERVICE/ Add

[PATCHv4 6/7] fpga: add intel stratix10 soc fpga manager driver

From: Alan Tull Add driver for reconfiguring Intel Stratix10 SoC FPGA devices. This driver communicates through the Intel Service Driver which does communication with privileged hardware (that does the FPGA programming) through a secure mailbox. Signed-off-by: Alan Tull Signed-off-by: Richard

[PATCHv4 4/7] dt-bindings: fpga: add Stratix10 SoC FPGA manager binding

From: Alan Tull Add a Device Tree binding for the Intel Stratix10 SoC FPGA manager. Signed-off-by: Alan Tull Signed-off-by: Richard Gong --- v2: this patch is added in patch set version 2 v3: change to put fpga_mgr node under firmware/svc node v4: s/fpga-mgr@0/fpga-mgr/ to remove unit_address

Re: [PATCHv1] dt-bindings: misc: add Intel Stratix10 service layer binding

On 01/30/2018 10:57 AM, Rob Herring wrote: On Tue, Jan 23, 2018 at 01:25:02PM -0600, richard.g...@linux.intel.com wrote: From: Richard Gong Add a device tree binding for the Intel Stratix10 service layer driver Signed-off-by: Richard Gong --- .../devicetree/bindings/misc/intel

[PATCHv1] Add reset manager offsets for Stratix10

From: Richard Gong There are several changes in reset manager offsets from Arria10 to stratix10. This patch is derived from Steffen Trumtrar's "altr,rst-mgr-a10.h" and adds additional offset updates for Stratix10 Richard Gong (1): dt-bindings: reset: Add reset manager offsets for

[PATCHv1] dt-bindings: reset: Add reset manager offsets for Stratix10

From: Richard Gong There are several changes in reset manager offsets from Arria10 to Stratix10. This patch is based on one from Arria10 and adds offset updates for Stratix10 Signed-off-by: Richard Gong --- include/dt-bindings/reset/altr,rst-mgr-s10.h | 108 +++ 1 file

[PATCHv3 0/6] [PATCHv3 0/6] Extend Intel service layer, FPGA manager and region

From: Richard Gong This is 3rd submission of Intel service layer and FPGA patches. This submission include additional changes for Intel service layer driver to get the firmware version running at FPGA SoC device. Then FPGA manager driver, one of Intel service layer driver's client, can decide

[PATCHv3 4/6] fpga: of-fpga-region: add authenticate-fpga-config property

From: Richard Gong Add authenticate-fpga-config property to support FPGA bitstream authentication, which makes sure a signed bitstream has valid signatures. Signed-off-by: Richard Gong --- v3: no change v2: changed in alphabetical order --- drivers/fpga/of-fpga-region.c | 3 +++ 1 file

[PATCHv3 5/6] dt-bindings: fpga: add authenticate-fpga-config property

From: Richard Gong Add authenticate-fpga-config property for FPGA bitstream authentication, which makes sure a signed bitstream has valid signatures. Signed-off-by: Richard Gong --- v3: no change v2: put authenticate-fpga-config above partial-fpga-config update commit messages

[PATCHv3 3/6] fpga: fpga-mgr: add FPGA_MGR_BITSTREM_AUTHENTICATION flag

From: Richard Gong Add FPGA_MGR_BITSTREM_AUTHENTICATION flag for FPGA bitstream authentication, which makes sure a signed bitstream has valid signatures. Except for the actual configuration of the device, the authentication works the same way as FPGA configuration does. If the authentication

[PATCHv3 2/6] firmware: stratix10-svc: extend SVC driver to get the firmware version

From: Richard Gong Extend Intel service layer driver to get the firmware version running at FPGA device. Therefore FPGA manager driver, one of Intel service layer driver's client, can decide whether to handle the newly added bitstream authentication function based on the retrieved firmware

[PATCHv3 1/6] firmware: stratix10-svc: add COMMAND_AUTHENTICATE_BITSTREAM flag

From: Richard Gong Add COMMAND_AUTHENTICATE_BITSTREAM command flag for new added bitstream authentication feature. Authenticating a bitstream is to make sure a signed bitstream has the valid signatures. Except for the actual configuration of the device, the bitstream authentication works

[PATCHv3 6/6] fpga: stratix10-soc: extend driver for bitstream authentication

From: Richard Gong Extend FPGA manager driver to support FPGA bitstream authentication on Intel SocFPGA platforms. Signed-off-by: Richard Gong --- v3: add handle to retriev the firmware version to keep driver back compatible v2: use flag defined in stratix10-svc driver --- drivers/fpga

Re: [RESEND PATCHv1] fpga: stratix10-soc: make FPGA task un-interruptible

Hi Moritz, No problem. Thanks you very much for applying patch to the next! Regards, Richard On 8/4/20 11:43 AM, Moritz Fischer wrote: On Fri, Jul 24, 2020 at 11:10:09AM -0500, richard.g...@linux.intel.com wrote: From: Richard Gong When CTRL+C occurs during the process of FPGA

[PATCH] arm64: dts: agilex: increase shared memory size to 32Mb

From: Richard Gong Increase the shared memory size from 16Mb to 32Mb so that we can properly handle the image authorization for 12+ Mb RBF/JIC files. Signed-off-by: Richard Gong --- arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[PATCHv1 0/2] add Intel SoCFPGA crypto service driver

From: Richard Gong I followed the process to register or request a valid IOCTL number/letter, but I got the delivery failure status notification. Cypto service driver and service layer driver patches have been reviewed internally by colleagues at Intel. Intel SoCFPGA is composed of a 64 bit

[PATCHv1 1/2] firmware: stratix10-svc: extend svc to support new crypto features

From: Richard Gong Extend Intel service layer driver to support new crypto services on Intel SoCFPGA platforms. The crypto services include security certificate, image boot validation, security key cancellation, get provision data, random number generation, advance encrtption standard (AES

[PATCHv1 2/2] crypto: add Intel SoCFPGA crypto service driver

From: Richard Gong Add Intel FPGA crypto service (FCS) driver to support new crypto services on Intel SoCFPGA platforms. The crypto services include security certificate, image boot validation, security key cancellation, get provision data, random number generation, advance encrtption standard

[PATCH] arm64: defconfig: include Intel Diamond Mesa platform

From: Richard Gong Include Intel Diamond Mesa SoC platform to the arm64 defconfig so that we build the Diamond Mesa in the standard arm64 defconfig. Signed-off-by: Richard Gong --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b

[PATCH] arm64: dts: diamonmesa: add device tree for Intel Diamond Mesa

From: Richard Gong Add the device tree files for Intel Diamond Mesa SoC Signed-off-by: Richard Gong --- arch/arm64/Kconfig.platforms | 5 + arch/arm64/boot/dts/intel/Makefile | 1 + arch/arm64/boot/dts/intel/socfpga_diamondmesa.dts | 41 ++ arch

Re: [PATCHv1 2/2] crypto: add Intel SoCFPGA crypto service driver

I will move them to drivers/misc. Regards, Richard On 8/11/20 7:34 PM, Herbert Xu wrote: On Tue, Aug 11, 2020 at 08:56:22AM -0500, richard.g...@linux.intel.com wrote: From: Richard Gong Add Intel FPGA crypto service (FCS) driver to support new crypto services on Intel SoCFPGA platforms

[PATCHv2] arm64: dts: diamonmesa: add device tree for Intel Diamond Mesa

From: Richard Gong Add the device tree files for Intel Diamond Mesa SoC Signed-off-by: Richard Gong --- v2: use socfpga_agilex.dtsi rather than socfpga_diamondmesa.dtsi --- arch/arm64/Kconfig.platforms | 5 ++ arch/arm64/boot/dts/intel/Makefile| 1

Re: [PATCH v3 40/56] firmware: stratix10-svc: fix kernel-doc markups

Acked-by: Richard Gong On 10/23/20 11:33 AM, Mauro Carvalho Chehab wrote: There are some common comments marked, instead, with kernel-doc notation, which won't work. While here, rename an identifier, in order to match the function prototype below kernel-doc markup. Signed-off-by: Mauro

Re: [PATCHv2 0/5] Extend Intel service layer, FPGA manager and region

Hi Moritz, Greg, Sorry for asking. Any comment on Intel service layer and FPGA patches submitted on 11/18/20? Regards, Richard On 11/18/20 8:29 AM, richard.g...@linux.intel.com wrote: From: Richard Gong This is 2nd submission of Intel service layer and FPGA patches. The customer wants

[RESEND PATCHv2 4/5] dt-bindings: fpga: add authenticate-fpga-config property

From: Richard Gong Add authenticate-fpga-config property for FPGA bitstream authentication, which makes sure a signed bitstream has valid signatures. Signed-off-by: Richard Gong --- v2: put authenticate-fpga-config above partial-fpga-config update commit messages --- Documentation

[RESEND PATCHv2 5/5] fpga: stratix10-soc: extend driver for bitstream authentication

From: Richard Gong Extend FPGA manager driver to support FPGA bitstream authentication on Intel SocFPGA platforms. Signed-off-by: Richard Gong --- v2: use flag defined in stratix10-svc driver --- drivers/fpga/stratix10-soc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/fpga

[RESEND PATCHv2 3/5] fpga: of-fpga-region: add authenticate-fpga-config property

From: Richard Gong Add authenticate-fpga-config property to support FPGA bitstream authentication, which makes sure a signed bitstream has valid signatures. Signed-off-by: Richard Gong --- v2: changed in alphabetical order --- drivers/fpga/of-fpga-region.c | 3 +++ 1 file changed, 3

[RESEND PATCHv2 1/5] firmware: stratix10-svc: add COMMAND_AUTHENTICATE_BITSTREAM flag

From: Richard Gong Add COMMAND_AUTHENTICATE_BITSTREAM command flag for new added bitstream authentication feature. Authenticating a bistream is to make sure a signed bitstream has the valid signatures. Except for the actual configuration of the device, the bitstream authentication works

Re: [PATCHv2 0/5] Extend Intel service layer, FPGA manager and region

Hi Greg, On 12/14/20 8:05 AM, Greg KH wrote: On Mon, Dec 14, 2020 at 08:03:07AM -0600, Richard Gong wrote: Hi Moritz, Greg, Sorry for asking. Any comment on Intel service layer and FPGA patches submitted on 11/18/20? I don't see them in my review queue, sorry. I just re-submitted

[RESEND PATCHv2 2/5] fpga: fpga-mgr: add FPGA_MGR_BITSTREM_AUTHENTICATION flag

From: Richard Gong Add FPGA_MGR_BITSTREM_AUTHENTICATION flag for FPGA bitstream authentication, which makes sure a signed bitstream has valid signatures. Except for the actual configuration of the device, the authentication works the same way as FPGA configuration does. If the authentication

[RESEND PATCHv2 0/5] Extend Intel service layer, FPGA manager and

From: Richard Gong This is 2nd submission of Intel service layer and FPGA patches. The customer wants to verify that a FPGA bitstream can be started properly before saving the bitstream to the QSPI flash memory. Bitstream authentication makes sure a signed bitstream has valid signatures

[PATCHv1 0/4] Extend FPGA manager and region drivers for

From: Richard Gong The customer wants to verify that a FPGA bitstream can be started properly before saving the bitstream to the QSPI flash memory. The customer sends the bitstream via FPGA framework and overlay, the firmware will authenticate the bitstream but not program the bitstream

  1   2   3   >