On 27.05.15 10:01:32, Robert Richter wrote:
From: Robert Richter rrich...@cavium.com
The irq number for msix devices is taken from msi_list instead of
pci_dev. Thus, the irq number of a device needs to be stored in struct
ahci_host_priv now. Host controller can be activated
From: Robert Richter rrich...@cavium.com
This patch set adds generic support for MSI-X interrupts to the SATA
PCI driver.
The first 2 patches rework the code, one splits msi and intx code into
separate functions, the other changes interrupt initialization to
store the irq number in the ahci data
From: Robert Richter rrich...@cavium.com
This patch refactors ahci_init_interrupts() and moves code to separate
functions for msi and intx. Needed since we add msix initialization in
a later patch. The initialization for msix is done after msi but
before intx.
Signed-off-by: Robert Richter rrich
From: Robert Richter rrich...@cavium.com
The irq number for msix devices is taken from msi_list instead of
pci_dev. Thus, the irq number of a device needs to be stored in struct
ahci_host_priv now. Host controller can be activated then in a
generic way.
Signed-off-by: Robert Richter rrich
From: Robert Richter rrich...@cavium.com
This patch adds generic support for MSI-X interrupts to the SATA PCI
driver. MSI-X support is needed for host controller that only have
MSI-X support implemented, such as the controller on Cavium's ThunderX
SoC. Only support for single interrupts is added
On 21.05.15 09:35:47, Marc Zyngier wrote:
> On 20/05/15 17:48, Catalin Marinas wrote:
> > On Wed, May 20, 2015 at 02:31:59PM +0200, Robert Richter wrote:
> >> On 20.05.15 13:22:13, Marc Zyngier wrote:
> >>> On Tue, 12 May 2015 18:24:16 +0100
> >>> Will
On 21.05.15 09:35:47, Marc Zyngier wrote:
On 20/05/15 17:48, Catalin Marinas wrote:
On Wed, May 20, 2015 at 02:31:59PM +0200, Robert Richter wrote:
On 20.05.15 13:22:13, Marc Zyngier wrote:
On Tue, 12 May 2015 18:24:16 +0100
Will Deacon will.dea...@arm.com wrote:
On Tue, May 12, 2015
Mark,
thanks for review, also of the other patches of this series.
See below
On 20.05.15 13:11:38, Marc Zyngier wrote:
> > - dev_alias->dev_id = alias;
> > + dev_alias->dev_id = (pci_domain_nr(pdev->bus) << 16) | alias;
> This feels very scary. We're now assuming that the domain number
On 20.05.15 13:22:13, Marc Zyngier wrote:
> On Tue, 12 May 2015 18:24:16 +0100
> Will Deacon wrote:
> > On Tue, May 12, 2015 at 05:20:49PM +0100, Robert Richter wrote:
> > > On 12.05.15 13:30:57, Will Deacon wrote:
> > > For allocation of 16MB cont. phys
On 20.05.15 13:22:13, Marc Zyngier wrote:
On Tue, 12 May 2015 18:24:16 +0100
Will Deacon will.dea...@arm.com wrote:
On Tue, May 12, 2015 at 05:20:49PM +0100, Robert Richter wrote:
On 12.05.15 13:30:57, Will Deacon wrote:
For allocation of 16MB cont. phys mem of a defconfig kernel (4KB
Mark,
thanks for review, also of the other patches of this series.
See below
On 20.05.15 13:11:38, Marc Zyngier wrote:
- dev_alias-dev_id = alias;
+ dev_alias-dev_id = (pci_domain_nr(pdev-bus) 16) | alias;
This feels very scary. We're now assuming that the domain number will
always
On 17.05.15 08:33:32, Alexander Gordeev wrote:
> You enable MSI-X for a single chip, but introduce a change to the
> generic AHCI code.
>
> In general MSI-X case, what makes you believe that IRQ vectors are
> assigned continuously?
>
> (Interface ahci_host_activate() kinda expects a contiguous
On 17.05.15 08:33:32, Alexander Gordeev wrote:
You enable MSI-X for a single chip, but introduce a change to the
generic AHCI code.
In general MSI-X case, what makes you believe that IRQ vectors are
assigned continuously?
(Interface ahci_host_activate() kinda expects a contiguous vector
On 13.05.15 13:46:40, Tejun Heo wrote:
> Hello, Robert.
>
> On Wed, May 13, 2015 at 07:28:28PM +0200, Robert Richter wrote:
> > > > This looks not very useful to do. Since irq is used only a single
> > > > time, there is no reason to store it in the host's data s
Tejun,
On 13.05.15 10:39:06, Tejun Heo wrote:
> On Tue, May 12, 2015 at 01:46:47PM +0200, Robert Richter wrote:
> > I don't think this is worth the effort as all internal and external
> > drivers need to be changed basically from:
> >
> > ahci_ho
Tejun,
On 13.05.15 10:39:06, Tejun Heo wrote:
On Tue, May 12, 2015 at 01:46:47PM +0200, Robert Richter wrote:
I don't think this is worth the effort as all internal and external
drivers need to be changed basically from:
ahci_host_activate(host, irq, ahci_sht);
to:
host-irq
On 13.05.15 13:46:40, Tejun Heo wrote:
Hello, Robert.
On Wed, May 13, 2015 at 07:28:28PM +0200, Robert Richter wrote:
This looks not very useful to do. Since irq is used only a single
time, there is no reason to store it in the host's data structure. It
Doesn't really matter tho
On 12.05.15 18:24:16, Will Deacon wrote:
> On Tue, May 12, 2015 at 05:20:49PM +0100, Robert Richter wrote:
> > For allocation of 16MB cont. phys mem of a defconfig kernel (4KB
> > default pagesize) I see this different approaches:
>
> 16MB sounds like an awful lot. Is this be
Will,
On 12.05.15 13:30:57, Will Deacon wrote:
> On Mon, May 11, 2015 at 10:14:38AM +0100, Robert Richter wrote:
> > On 05.05.15 11:53:29, Will Deacon wrote:
> > > On Sun, May 03, 2015 at 09:49:32PM +0100, Robert Richter wrote:
> > > > From: Radha Mohan Chintaku
Tejun,
On 11.05.15 19:18:10, Robert Richter wrote:
> > > +static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int
> > > n_ports,
> > > + struct ahci_host_priv *hpriv)
> > > +{
> > > + struct msi_desc *desc;
On 12.05.15 18:24:16, Will Deacon wrote:
On Tue, May 12, 2015 at 05:20:49PM +0100, Robert Richter wrote:
For allocation of 16MB cont. phys mem of a defconfig kernel (4KB
default pagesize) I see this different approaches:
16MB sounds like an awful lot. Is this because you have tonnes
Will,
On 12.05.15 13:30:57, Will Deacon wrote:
On Mon, May 11, 2015 at 10:14:38AM +0100, Robert Richter wrote:
On 05.05.15 11:53:29, Will Deacon wrote:
On Sun, May 03, 2015 at 09:49:32PM +0100, Robert Richter wrote:
From: Radha Mohan Chintakuntla rchintakun...@cavium.com
Tejun,
On 11.05.15 19:18:10, Robert Richter wrote:
+static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int
n_ports,
+ struct ahci_host_priv *hpriv)
+{
+ struct msi_desc *desc;
+
+ __ahci_init_interrupts(pdev, n_ports, hpriv
Tejun,
thanks for your review and answer.
On 04.05.15 12:06:52, Tejun Heo wrote:
> > This patch also enables AHCI for Cavium Thunder SoCs that uses MSI-X.
>
> Please don't mix these two changes in the same patch.
I will split the patch.
> > + /* per-port msix interrupts are not supported */
On 05.05.15 11:53:29, Will Deacon wrote:
> On Sun, May 03, 2015 at 09:49:32PM +0100, Robert Richter wrote:
> > From: Radha Mohan Chintakuntla
> >
> > In case of ARCH_THUNDER, there is a need to allocate the GICv3 ITS table
> > which is bigger than the allowed max order
On 05.05.15 11:53:29, Will Deacon wrote:
On Sun, May 03, 2015 at 09:49:32PM +0100, Robert Richter wrote:
From: Radha Mohan Chintakuntla rchintakun...@cavium.com
In case of ARCH_THUNDER, there is a need to allocate the GICv3 ITS table
which is bigger than the allowed max order. So we
Tejun,
thanks for your review and answer.
On 04.05.15 12:06:52, Tejun Heo wrote:
This patch also enables AHCI for Cavium Thunder SoCs that uses MSI-X.
Please don't mix these two changes in the same patch.
I will split the patch.
+ /* per-port msix interrupts are not supported */
+
From: Robert Richter
This patch adds generic support for MSI-X interrupts to the SATA PCI
driver. Only single interrupt support is implemented. Thus, per-port
interrupts can not yet be enabled.
The driver now checks the device for the existence of MSI-X and tries
to enable the interrupt
From: Robert Richter rrich...@cavium.com
This patch adds generic support for MSI-X interrupts to the SATA PCI
driver. Only single interrupt support is implemented. Thus, per-port
interrupts can not yet be enabled.
The driver now checks the device for the existence of MSI-X and tries
to enable
From: Robert Richter
The number of pages for the its table may exceed the maximum of 256.
Adding a range check and limitting the number to its maximum.
Based on a patch from Tirumalesh Chalamarla .
Signed-off-by: Robert Richter
---
drivers/irqchip/irq-gic-v3-its.c | 11 ++-
include
From: Radha Mohan Chintakuntla
In case of ARCH_THUNDER, there is a need to allocate the GICv3 ITS table
which is bigger than the allowed max order. So we are forcing it only in
case of 4KB page size.
Signed-off-by: Radha Mohan Chintakuntla
Signed-off-by: Robert Richter
---
arch/arm64/Kconfig
From: Robert Richter
No need to read the typer register in the loop. Values do not change.
Signed-off-by: Robert Richter
---
drivers/irqchip/irq-gic-v3-its.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3
From: Tirumalesh Chalamarla
PCI stream ids need to consider pci bridge number to be unique on the
system. Using only bus and devfn can't do the trick in systems that
have multiple pci bridges.
Signed-off-by: Tirumalesh Chalamarla
Signed-off-by: Robert Richter
---
drivers/irqchip/irq-gic-v3
From: Robert Richter
This patch series adds fixes and updates for ThunderX.
Patches are unrelated each other and can be applied individually.
Radha Mohan Chintakuntla (1):
arm64: gicv3: its: Increase FORCE_MAX_ZONEORDER for Cavium ThunderX
Robert Richter (2):
arm64: gicv3: its: Add range
-by: Robert Richter rrich...@cavium.com
---
drivers/irqchip/irq-gic-v3-its.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 9687f8afebff..e30b4de04c6c 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers
From: Robert Richter rrich...@cavium.com
The number of pages for the its table may exceed the maximum of 256.
Adding a range check and limitting the number to its maximum.
Based on a patch from Tirumalesh Chalamarla tchalama...@cavium.com.
Signed-off-by: Robert Richter rrich...@cavium.com
-off-by: Robert Richter rrich...@cavium.com
---
arch/arm64/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 1b8e97331ffb..c519f3777453 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -542,6 +542,7 @@ config XEN
config
From: Robert Richter rrich...@cavium.com
No need to read the typer register in the loop. Values do not change.
Signed-off-by: Robert Richter rrich...@cavium.com
---
drivers/irqchip/irq-gic-v3-its.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-gic
From: Robert Richter rrich...@cavium.com
This patch series adds fixes and updates for ThunderX.
Patches are unrelated each other and can be applied individually.
Radha Mohan Chintakuntla (1):
arm64: gicv3: its: Increase FORCE_MAX_ZONEORDER for Cavium ThunderX
Robert Richter (2):
arm64
On 01.04.15 10:56:00, Robert Richter wrote:
> (cc'ing Andi)
>
> > On Wed, Apr 01, 2015 at 10:15:58AM +0200, Borislav Petkov wrote:
> > > From: Borislav Petkov
> > >
> > > Today, April 1st 2015, marks almost 15 years since the introduction of
> > &g
od to start with it now. Also, I really would like to
finally switch off and retire my K7 which still runs some regression
tests (will need to check the actual used kernel version). It was a
good time, but now I realize it's somehow over. Considering this and
apart from my concerns above:
Acked-by: Ro
to
finally switch off and retire my K7 which still runs some regression
tests (will need to check the actual used kernel version). It was a
good time, but now I realize it's somehow over. Considering this and
apart from my concerns above:
Acked-by: Robert Richter r...@kernel.org
-Robert
On 01.04.15 10:56:00, Robert Richter wrote:
(cc'ing Andi)
On Wed, Apr 01, 2015 at 10:15:58AM +0200, Borislav Petkov wrote:
From: Borislav Petkov b...@suse.de
Today, April 1st 2015, marks almost 15 years since the introduction of
the 64-bit extensions to the x86 architecture
On 13.02.15 10:48:18, Hanjun Guo wrote:
> On 2015年02月12日 18:02, Robert Richter wrote:
> >On 02.02.15 20:45:28, Hanjun Guo wrote:
> >>This is the v8 of ACPI core patches for ARM64 based on ACPI 5.1, there are
> >>some updates since v7:
> >>
> >> - Add
On 13.02.15 10:48:18, Hanjun Guo wrote:
On 2015年02月12日 18:02, Robert Richter wrote:
On 02.02.15 20:45:28, Hanjun Guo wrote:
This is the v8 of ACPI core patches for ARM64 based on ACPI 5.1, there are
some updates since v7:
- Add two more documantation to explain why we need ACPI in ARM64
GICv2m are implemented;
>
> - Rebased on top of 3.19-rc7.
Patches tested on Cavium ThunderX. For the whole series:
Tested-by: Robert Richter
Acked-by: Robert Richter
Please apply.
Thanks,
-Robert
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel"
;
- Address some comments from Marc and explicitly state that will
implment statcked irqdomain and GIC init framework when GICv3 and
ITS, GICv2m are implemented;
- Rebased on top of 3.19-rc7.
Patches tested on Cavium ThunderX. For the whole series:
Tested-by: Robert Richter rrich
On 10.11.14 22:51:44, Jiang Liu wrote:
> On 2014/11/10 13:30, Robert Richter wrote:
> > From: Sunil Goutham
> > + /* only enable the first entry (entry.entry = 0) */
> > + rc = pci_enable_msix_exact(pdev, , 1);
> > + if (rc < 0)
> > +
On 10.11.14 22:51:44, Jiang Liu wrote:
On 2014/11/10 13:30, Robert Richter wrote:
From: Sunil Goutham sgout...@cavium.com
+ /* only enable the first entry (entry.entry = 0) */
+ rc = pci_enable_msix_exact(pdev, entry, 1);
+ if (rc 0)
+ return rc;
+
+ pdev-irq
. Otherwise, if a device is not MSI-X capable,
the initialization is skipped and MSI or intx interrupts are
configured.
This patch also enables AHCI for Cavium Thunder SoCs that uses MSI-X.
Signed-off-by: Sunil Goutham
Signed-off-by: Robert Richter
---
arch/arm64/Kconfig | 1 +
drivers/ata/ahci.c | 40
the interrupt. Otherwise, if a device is not MSI-X capable,
the initialization is skipped and MSI or intx interrupts are
configured.
This patch also enables AHCI for Cavium Thunder SoCs that uses MSI-X.
Signed-off-by: Sunil Goutham sgout...@cavium.com
Signed-off-by: Robert Richter rrich...@cavium.com
On 03.11.14 20:47:17, Olof Johansson wrote:
> > > Robert Richter (6):
> > > dts, arm64: Add dtbs_install make target
> > > dts, kbuild: Factor out dtbs install rules to Makefile.dtbinst
> > > dts, arm/arm64: Remove dtbs build rules in sub-makes
> >
On 03.11.14 20:47:17, Olof Johansson wrote:
Robert Richter (6):
dts, arm64: Add dtbs_install make target
dts, kbuild: Factor out dtbs install rules to Makefile.dtbinst
dts, arm/arm64: Remove dtbs build rules in sub-makes
dts, kbuild: Implement support for dtb vendor subdirs
On 03.11.14 10:16:51, Stephen Hemminger wrote:
> On Fri, 31 Oct 2014 22:44:11 +0530
> Sunil Kovvuri wrote:
>
> > On Fri, Oct 31, 2014 at 8:24 AM, Stephen Hemminger
> > wrote:
> > > On Thu, 30 Oct 2014 17:54:34 +0100
> > > Robert Richter wrote:
>
On 03.11.14 10:16:51, Stephen Hemminger wrote:
On Fri, 31 Oct 2014 22:44:11 +0530
Sunil Kovvuri sunil.kovv...@gmail.com wrote:
On Fri, Oct 31, 2014 at 8:24 AM, Stephen Hemminger
step...@networkplumber.org wrote:
On Thu, 30 Oct 2014 17:54:34 +0100
Robert Richter r...@kernel.org wrote
On 30.10.14 19:45:13, Stephen Hemminger wrote:
> On Thu, 30 Oct 2014 17:54:34 +0100
> Robert Richter wrote:
>
> > diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
> > index 1fa99a301817..80bd3336691e 100644
> > --- a/include/linux/pci_ids.h
> &
On 30.10.14 19:45:13, Stephen Hemminger wrote:
On Thu, 30 Oct 2014 17:54:34 +0100
Robert Richter r...@kernel.org wrote:
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 1fa99a301817..80bd3336691e 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
Arnd,
On 21.10.14 20:15:04, Robert Richter wrote:
> please pull this series for inclusion into v3.19 from:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/rric/linux.git
> dts-subdirs-for-arm-soc-v3.19
>
> I have updated and rebased the patches to v3.18-rc1. No changes
Arnd,
On 21.10.14 20:15:04, Robert Richter wrote:
please pull this series for inclusion into v3.19 from:
git://git.kernel.org/pub/scm/linux/kernel/git/rric/linux.git
dts-subdirs-for-arm-soc-v3.19
I have updated and rebased the patches to v3.18-rc1. No changes except
conflict resolution
Arnd,
On 05.09.14 08:48:06, Robert Richter wrote:
> From: Robert Richter
>
> For arm64 we want to put dts files into vendor's subdirectories from
> the beginning. This patch set implements this. As this is a generic
> kbuild implementation, vendor subdirs will be also available
Arnd,
On 05.09.14 08:48:06, Robert Richter wrote:
From: Robert Richter rrich...@cavium.com
For arm64 we want to put dts files into vendor's subdirectories from
the beginning. This patch set implements this. As this is a generic
kbuild implementation, vendor subdirs will be also available
On 20.10.14 19:26:32, Abhilash Kesavan wrote:
> >> > > > > Robert Richter (6):
> >> > > > > dts, arm64: Add dtbs_install make target
> >> > > > > dts, kbuild: Factor out dtbs install rules to Makefile.dtbinst
>
On 20.10.14 19:26:32, Abhilash Kesavan wrote:
Robert Richter (6):
dts, arm64: Add dtbs_install make target
dts, kbuild: Factor out dtbs install rules to Makefile.dtbinst
dts, arm/arm64: Remove dtbs build rules in sub-makes
dts, kbuild: Implement support
On 08.10.14 17:44:32, Liviu Dudau wrote:
> On Wed, Oct 08, 2014 at 09:49:27AM +0100, Robert Richter wrote:
> > On 07.10.14 16:01:49, Liviu Dudau wrote:
> > I am quite confused a bit on which is the latest code base now. I was
> > looking into Bjorn's pci/host-generic and
On 08.10.14 17:44:32, Liviu Dudau wrote:
On Wed, Oct 08, 2014 at 09:49:27AM +0100, Robert Richter wrote:
On 07.10.14 16:01:49, Liviu Dudau wrote:
I am quite confused a bit on which is the latest code base now. I was
looking into Bjorn's pci/host-generic and there is a different
On 08.10.14 10:13:21, Liviu Dudau wrote:
> On Wed, Oct 08, 2014 at 08:44:28AM +0100, Robert Richter wrote:
> > I assume pci/host-generic is the latest now with this issue fixed as
> > the commit date is 2014-10-01 past you message above, right? So is it
> > ok to rebase our h
On 07.10.14 16:01:49, Liviu Dudau wrote:
> On Tue, Oct 07, 2014 at 03:27:44PM +0100, Robert Richter wrote:
> > On 24.09.14 18:06:04, Arnd Bergmann wrote:
> > > > + compatible = "cavium,thunder-pcie";
> > > > + device_type
Liviu, Bjorn,
On 30.09.14 17:54:31, Liviu Dudau wrote:
> On Tue, Sep 30, 2014 at 05:18:05PM +0100, Bjorn Helgaas wrote:
> > OK, I rebuilt pci/host-generic from scratch. It consists of your v13
> > patches + Arnd's build fix for pci_pio_to_address() in !CONFIG_OF configs.
>
> Something went
Liviu, Bjorn,
On 30.09.14 17:54:31, Liviu Dudau wrote:
On Tue, Sep 30, 2014 at 05:18:05PM +0100, Bjorn Helgaas wrote:
OK, I rebuilt pci/host-generic from scratch. It consists of your v13
patches + Arnd's build fix for pci_pio_to_address() in !CONFIG_OF configs.
Something went wrong with
On 07.10.14 16:01:49, Liviu Dudau wrote:
On Tue, Oct 07, 2014 at 03:27:44PM +0100, Robert Richter wrote:
On 24.09.14 18:06:04, Arnd Bergmann wrote:
+ compatible = cavium,thunder-pcie;
+ device_type = pci;
+ msi-parent = its
On 08.10.14 10:13:21, Liviu Dudau wrote:
On Wed, Oct 08, 2014 at 08:44:28AM +0100, Robert Richter wrote:
I assume pci/host-generic is the latest now with this issue fixed as
the commit date is 2014-10-01 past you message above, right? So is it
ok to rebase our host controller driver onto
On 24.09.14 18:06:04, Arnd Bergmann wrote:
> > + compatible = "cavium,thunder-pcie";
> > + device_type = "pci";
> > + msi-parent = <>;
> > + bus-range = <0 255>;
> > + #size-cells = <2>;
> > + #address-cells = <3>;
On 24.09.14 18:06:04, Arnd Bergmann wrote:
+ compatible = cavium,thunder-pcie;
+ device_type = pci;
+ msi-parent = its;
+ bus-range = 0 255;
+ #size-cells = 2;
+ #address-cells = 3;
+
On 30.09.14 10:24:16, Arnaldo Carvalho de Melo wrote:
> Em Tue, Sep 30, 2014 at 11:06:21AM +0200, Jean Pihet escreveu:
> > The plan is to move the small and generic functions first: util,
> > xyarray, cpumap, thread_map etc; then evlist, evsel, trace-event,
> > trace-event-parse; and finally
Arnd,
On 02.10.14 17:44:48, Arnd Bergmann wrote:
> On Thursday 02 October 2014 16:44:52 Robert Richter wrote:
> > The following changes since commit 9e82bf014195d6f0054982c463575cdce24292be:
> >
> > Linux 3.17-rc5 (2014-09-14 17:50:12 -0700)
> >
> > ar
Arnd,
On 02.10.14 17:44:48, Arnd Bergmann wrote:
On Thursday 02 October 2014 16:44:52 Robert Richter wrote:
The following changes since commit 9e82bf014195d6f0054982c463575cdce24292be:
Linux 3.17-rc5 (2014-09-14 17:50:12 -0700)
are available in the git repository at:
git
On 30.09.14 10:24:16, Arnaldo Carvalho de Melo wrote:
Em Tue, Sep 30, 2014 at 11:06:21AM +0200, Jean Pihet escreveu:
The plan is to move the small and generic functions first: util,
xyarray, cpumap, thread_map etc; then evlist, evsel, trace-event,
trace-event-parse; and finally integrate
On 23.09.14 13:26:19, Robert Richter wrote:
> On 19.09.14 15:08:56, Catalin Marinas wrote:
> > On Fri, Sep 19, 2014 at 01:30:56PM +0100, Robert Richter wrote:
> > > On 16.09.14 20:49:18, Andrew Bresticker wrote:
> > > > > Robert Richter (6):
> > > >
([GIT PULL] in the subject)
On 02.10.14 09:29:38, Robert Richter wrote:
> On 23.09.14 16:14:29, Robert Richter wrote:
> > On 23.09.14 12:21:05, Catalin Marinas wrote:
> > > On Tue, Sep 23, 2014 at 11:46:41AM +0100, Will Deacon wrote:
> > > > On Tue, Sep 23, 20
On 23.09.14 16:14:29, Robert Richter wrote:
> On 23.09.14 12:21:05, Catalin Marinas wrote:
> > On Tue, Sep 23, 2014 at 11:46:41AM +0100, Will Deacon wrote:
> > > On Tue, Sep 23, 2014 at 11:41:22AM +0100, Robert Richter wrote:
> > > > On 12.09.14 19:49:43, Robert
On 23.09.14 16:14:29, Robert Richter wrote:
On 23.09.14 12:21:05, Catalin Marinas wrote:
On Tue, Sep 23, 2014 at 11:46:41AM +0100, Will Deacon wrote:
On Tue, Sep 23, 2014 at 11:41:22AM +0100, Robert Richter wrote:
On 12.09.14 19:49:43, Robert Richter wrote:
From: Robert Richter
([GIT PULL] in the subject)
On 02.10.14 09:29:38, Robert Richter wrote:
On 23.09.14 16:14:29, Robert Richter wrote:
On 23.09.14 12:21:05, Catalin Marinas wrote:
On Tue, Sep 23, 2014 at 11:46:41AM +0100, Will Deacon wrote:
On Tue, Sep 23, 2014 at 11:41:22AM +0100, Robert Richter wrote
On 23.09.14 13:26:19, Robert Richter wrote:
On 19.09.14 15:08:56, Catalin Marinas wrote:
On Fri, Sep 19, 2014 at 01:30:56PM +0100, Robert Richter wrote:
On 16.09.14 20:49:18, Andrew Bresticker wrote:
Robert Richter (6):
dts, arm64: Add dtbs_install make target
dts, kbuild
On 24.09.14 18:14:11, Arnd Bergmann wrote:
> On Wednesday 24 September 2014 17:37:47 Robert Richter wrote:
> > config PCI
> > bool "PCI support"
> > + default y
> > help
> > This feature enables support for PCIe
From: Robert Richter
This patches add support for the Cavium Thunder PCIe host controller.
Patches base on following branches:
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci pci/liviu-generic-v11
git://linux-arm.org/linux-ld for-upstream/pci_arm64_v11
Additionally a fix
From: Sunil Goutham
This patch adds documentation for the devicetree bindings used by the
Thunder PCI host controller.
Signed-off-by: Sunil Goutham
Signed-off-by: Robert Richter
---
.../devicetree/bindings/pci/cavium,thunder-pci.txt | 32 ++
1 file changed, 32 insertions
From: Sunil Goutham
This patch adds support for PCI host controller of Cavium Thunder
SoCs.
Signed-off-by: Sunil Goutham
Signed-off-by: Robert Richter
---
drivers/pci/host/Kconfig| 8 ++
drivers/pci/host/Makefile | 1 +
drivers/pci/host/pcie-thunder.c | 246
From: Tirumalesh Chalamarla
The PCIe host controller uses MSIs provided by GICv3 ITS. Enable it on
Thunder SoCs by adding an entry to DT.
Signed-off-by: Tirumalesh Chalamarla
Signed-off-by: Robert Richter
---
arch/arm64/boot/dts/thunder-88xx.dtsi | 9 +
1 file changed, 9 insertions
From: Robert Richter
Enable Cavium Thunder PCIe host controller driver.
IOV is enabled per default if drivers with IOV support are
enabled. IOV can be disabled.
Signed-off-by: Robert Richter
---
arch/arm64/Kconfig | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64
From: Sunil Goutham
This patch adds the PCIe host controller entry for Cavium Thunder SoCs
to the devicetree. There are 4 internal PCI controllers available.
Signed-off-by: Sunil Goutham
Signed-off-by: Robert Richter
---
arch/arm64/boot/dts/thunder-88xx.dtsi | 49
From: Robert Richter
Enable the PCI subsystem in defconfig. There will be more and more
systems with pci support, so default enable it. This also implicitly
enables the MSI feature.
Signed-off-by: Robert Richter
---
arch/arm64/Kconfig | 4
1 file changed, 4 insertions(+)
diff --git
On 23.09.14 19:16:19, Bjorn Helgaas wrote:
> You probably saw the subsequent [pci:pci/host-generic 10/13]
> drivers/of/of_pci.c:202:3: error: implicit declaration of function
> 'of_pci_range_to_resource' error.
>
> I looked at that a bit, but gave up. Apparently drivers/of/of_pci.c
> can be
On 23.09.14 19:16:19, Bjorn Helgaas wrote:
You probably saw the subsequent [pci:pci/host-generic 10/13]
drivers/of/of_pci.c:202:3: error: implicit declaration of function
'of_pci_range_to_resource' error.
I looked at that a bit, but gave up. Apparently drivers/of/of_pci.c
can be compiled
From: Robert Richter rrich...@cavium.com
Enable the PCI subsystem in defconfig. There will be more and more
systems with pci support, so default enable it. This also implicitly
enables the MSI feature.
Signed-off-by: Robert Richter rrich...@cavium.com
---
arch/arm64/Kconfig | 4
1 file
From: Sunil Goutham sgout...@cavium.com
This patch adds the PCIe host controller entry for Cavium Thunder SoCs
to the devicetree. There are 4 internal PCI controllers available.
Signed-off-by: Sunil Goutham sgout...@cavium.com
Signed-off-by: Robert Richter rrich...@cavium.com
---
arch/arm64
From: Tirumalesh Chalamarla tchalama...@cavium.com
The PCIe host controller uses MSIs provided by GICv3 ITS. Enable it on
Thunder SoCs by adding an entry to DT.
Signed-off-by: Tirumalesh Chalamarla tchalama...@cavium.com
Signed-off-by: Robert Richter rrich...@cavium.com
---
arch/arm64/boot/dts
From: Robert Richter rrich...@cavium.com
Enable Cavium Thunder PCIe host controller driver.
IOV is enabled per default if drivers with IOV support are
enabled. IOV can be disabled.
Signed-off-by: Robert Richter rrich...@cavium.com
---
arch/arm64/Kconfig | 11 +++
1 file changed, 11
From: Sunil Goutham sgout...@cavium.com
This patch adds documentation for the devicetree bindings used by the
Thunder PCI host controller.
Signed-off-by: Sunil Goutham sgout...@cavium.com
Signed-off-by: Robert Richter rrich...@cavium.com
---
.../devicetree/bindings/pci/cavium,thunder-pci.txt
From: Sunil Goutham sgout...@cavium.com
This patch adds support for PCI host controller of Cavium Thunder
SoCs.
Signed-off-by: Sunil Goutham sgout...@cavium.com
Signed-off-by: Robert Richter rrich...@cavium.com
---
drivers/pci/host/Kconfig| 8 ++
drivers/pci/host/Makefile | 1
From: Robert Richter rrich...@cavium.com
This patches add support for the Cavium Thunder PCIe host controller.
Patches base on following branches:
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci pci/liviu-generic-v11
git://linux-arm.org/linux-ld for-upstream/pci_arm64_v11
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