On 04/22/2014 10:27 AM, Antoine Ténart wrote:
Enable the SD Card reader and the internal eMMC on the Berlin BG2Q DMP
using two of the SDHCI nodes of the Berlin BG2Q.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
arch/arm/boot/dts/berlin2q-marvell-dmp.dts | 11
On 04/23/2014 07:36 PM, Antoine Ténart wrote:
On Wed, Apr 23, 2014 at 07:26:23PM +0200, Sebastian Hesselbarth wrote:
On 04/22/2014 10:27 AM, Antoine Ténart wrote:
Enable the SD Card reader and the internal eMMC on the Berlin BG2Q DMP
using two of the SDHCI nodes of the Berlin BG2Q.
Signed
On 04/24/2014 02:52 PM, Linus Walleij wrote:
On Wed, Apr 23, 2014 at 5:51 PM, Antoine Ténart
antoine.ten...@free-electrons.com wrote:
This series adds support for the Marvell Berlin pin-controller, allowing
to configure the pin muxing from the device tree.
The Berlin pin-controller support is
cosmetic nits on the pinctrl driver and one fixup for
the dts.
If you resend, feel free to add my
Acked-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
[...]
diff --git a/drivers/pinctrl/berlin/berlin.c b/drivers/pinctrl/berlin/berlin.c
new file mode 100644
index
On 04/23/2014 05:51 PM, Antoine Ténart wrote:
Add the pin-controller driver for the Berlin BG2Q SoC, with definition
of its groups and functions. This uses the core Berlin pinctrl driver.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
[...]
diff --git
On 04/23/2014 05:51 PM, Antoine Ténart wrote:
Add the pin-controller driver for the Berlin BG2 SoC, with definition
of its groups and functions. This uses the core Berlin pinctrl driver.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
[...]
diff --git
On 04/23/2014 05:51 PM, Antoine Ténart wrote:
Add the pin-controller driver for the Berlin BG2CD SoC, with definition
of its groups and functions. This uses the core Berlin pinctrl driver.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
[...]
diff --git
On 04/23/2014 05:51 PM, Antoine Ténart wrote:
Add the documentation related to the Berlin pin-controller driver and
explain how to configure this group based controller.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
.../bindings/pinctrl/marvell,berlin-pinctrl.txt|
On 04/23/2014 05:51 PM, Antoine Ténart wrote:
The uart0 pinmux configuration is in the dtsi because uart0 will always
use uart0-pmux to work, no other possibility. Same thing for uart1.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
arch/arm/boot/dts/berlin2.dtsi |
On 04/25/2014 11:13 AM, Linus Walleij wrote:
On Wed, Apr 23, 2014 at 5:51 PM, Antoine Ténart
antoine.ten...@free-electrons.com wrote:
This series adds support for the Marvell Berlin pin-controller, allowing
to configure the pin muxing from the device tree.
I've looked over the patch
mvsdio reports method of card detection with dev_notice, while for
removable cards it may be sane, for non-removable cards it is not.
Also, as the user cannot do anything about it, silence the message
by reducing it from dev_notice to dev_dbg.
Signed-off-by: Sebastian Hesselbarth
didn't expect any.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Acked-by: Jason Cooper ja...@lakedaemon.net
---
Cc: Nicolas Pitre n...@fluxnic.net
Cc: Chris Ball ch...@printf.net
Cc: Ulf Hansson ulf.hans...@linaro.org
Cc: Jason Cooper ja...@lakedaemon.net
Cc: Andrew Lunn
. Although, not directly related with the described issue, reverse
irq bit handling back to original order by replacing ffs() with fls().
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Acked-by: Jason Cooper ja...@lakedaemon.net
---
Cc: Jason Cooper ja...@lakedaemon.net
Cc
have been fired.
Third patch reverses irq handling priority for irqchip driver to what
non-DT irq did before by using fls() instead of ffs(). The read cause
once, work through all irqs handling is maintained.
[1] https://lkml.org/lkml/2013/11/15/276
Sebastian Hesselbarth (3):
mmc: mvsdio
On 04/22/2014 05:38 PM, Antoine Ténart wrote:
Add support for the Berlin SoCs AHCI SATA controller allowing to
interface with devices like external hard drives.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
drivers/ata/Kconfig | 9 +++
drivers/ata/Makefile
On 04/22/2014 05:38 PM, Antoine Ténart wrote:
The berlin-achi driver allows Berlin SoCs to support their AHCI SATA
controller.
Add the compatible to the device tree bindings documentation.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
On 04/22/2014 06:28 PM, Thomas Petazzoni wrote:
Dear Antoine Ténart,
On Tue, 22 Apr 2014 17:38:22 +0200, Antoine Ténart wrote:
The BG2Q has an AHCI SATA controller. Add the corresponding node
in its device tree.
I believe the commit log should explain why an apparently unrelated
[Added MMC maintainers Chris and Ulf for one question below]
On 04/22/2014 10:27 AM, Antoine Ténart wrote:
Add the SDHCI nodes for the Marvell Berlin BG2Q, using the mrvl,pxav3-mmc
driver.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
arch/arm/boot/dts/berlin2q.dtsi
On 04/17/2014 10:45 AM, Antoine Ténart wrote:
After adding support for the Berlin BG2Q GPIOs, this series uses the
same GPIO dwapb driver to support the Berlin BG2 and BG2CD GPIOs.
Applies on top of Sebastian's for-next branch[1].
[1]
On 04/15/2014 08:48 PM, Sebastian Hesselbarth wrote:
This selects missing CPU_V7 for ARM Cortex-A9 based Marvell Armada
1500-mini (BG2CD).
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Applied to berlin/soc.
---
arch/arm/mach-berlin/Kconfig | 1 +
1 file
On 04/22/2014 08:29 PM, Rob Herring wrote:
On Tue, Apr 22, 2014 at 1:11 PM, Sebastian Hesselbarth
sebastian.hesselba...@gmail.com wrote:
On 04/15/2014 08:48 PM, Sebastian Hesselbarth wrote:
This selects missing CPU_V7 for ARM Cortex-A9 based Marvell Armada
1500-mini (BG2CD).
Signed-off
On 04/22/2014 08:29 PM, Rob Herring wrote:
On Tue, Apr 22, 2014 at 1:11 PM, Sebastian Hesselbarth
sebastian.hesselba...@gmail.com wrote:
On 04/15/2014 08:48 PM, Sebastian Hesselbarth wrote:
This selects missing CPU_V7 for ARM Cortex-A9 based Marvell Armada
1500-mini (BG2CD).
Signed-off
On 03/21/2014 10:42 PM, Sebastian Hesselbarth wrote:
On 03/21/2014 08:39 PM, Alexandre Belloni wrote:
Now that we start supporting the Marvell Berlin BG2Q, add a symbol
allowing to
differentiate that SoC from the other SoCs of the Berlin family.
Signed-off-by: Alexandre Belloni
On 04/15/2014 10:07 AM, Antoine Ténart wrote:
The BG2Q has GPIOs driven by the dwapb GPIO driver. Add the LIBGPIO as a
dependency to be able to support them.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
arch/arm/mach-berlin/Kconfig | 1 +
1 file changed, 1 insertion(+)
in? If I find some time, I'll prepare a patch for
dw-apb-gpio to exploit that (optional) information instead of
using nr-gpios.
Otherwise,
Acked-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
+ reg = 0
On 04/15/2014 12:00 PM, Jisheng Zhang wrote:
On Tue, 15 Apr 2014 02:23:03 -0700
Sebastian Hesselbarth sebastian.hesselba...@gmail.com wrote:
On 04/15/2014 10:07 AM, Antoine Ténart wrote:
The Marvell Berlin BG2Q has 6 GPIO ports compatible with the
snps,dw-apb-gpio driver. This patch add
On 04/15/2014 01:48 PM, Alexandre Belloni wrote:
On 15/04/2014 at 12:26:11 +0200, Sebastian Hesselbarth wrote :
On 04/15/2014 12:00 PM, Jisheng Zhang wrote:
On Tue, 15 Apr 2014 02:23:03 -0700
Sebastian Hesselbarth sebastian.hesselba...@gmail.com wrote:
I am fine with using nr-gpios property
This fixes PJ4 coprocessor init to only expose iWMMXt capabilities,
if the corresponding kernel support for iWMMXt is enabled.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Russell King li...@arm.linux.org.uk
Cc: Arnd Bergmann a...@arndb.de
Cc: Olof Johansson o
Some Marvell PJ4B CPUs also implement iWMMXt extensions. With a
proper check for iWMMXt coprocessors now in place, enable it by
default on PJ4B. While at it, also allow to manually select
the corresponding Kconfig option.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc
boot tested it on Marvell Dove and Marvell Berlin BG2.
Any Tested-by's from XScale and/or non-PJ4[B] architectures are
also appreciated.
Russell, please let me know if/when you are happy with the fixes
and the improvement. I'll be adding them to your patch tracker then.
Sebastian
Sebastian
On 03/27/2014 04:24 PM, Sebastian Hesselbarth wrote:
On 03/04/2014 05:03 AM, Jason Cooper wrote:
On Sat, Mar 01, 2014 at 09:33:20AM +0100, Sebastian Hesselbarth wrote:
DT-enabled Dove will move over from ARCH_DOVE in mach-dove to
MACH_DOVE in
mach-mvebu. As non-DT ARCH_DOVE will stay to rot
is too narrow to catch PJ4 used on
Dove itself and breaks iWMMXt support.
This patch therefore relaxes the cpuid mask to match both PJ4
and PJ4B. Also, rework the given comment about PJ4/PJ4B
modifications to be a little bit more specific about the
differences.
Signed-off-by: Sebastian Hesselbarth
directives to explicitly
check for supported architectures and fail on unsupported ones.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Russell King li...@arm.linux.org.uk
Cc: Arnd Bergmann a...@arndb.de
Cc: Olof Johansson o...@lixom.net
Cc: Kevin Hilman khil
Dove, iWMMXt v2
- PJ4B, CPUID 0x561f5811: Marvell Armada 370, no iWMMXt
- PJ4B, CPUID 0x562f5841, wCID 0x56052001: Marvell Armada 1500, iWMMXt v2
- PJ4B, CPUID 0x562f5842: Marvell Armada XP, no iWMMXt
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Russell King li
This selects missing CPU_V7 for ARM Cortex-A9 based Marvell Armada
1500-mini (BG2CD).
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Russell King li...@arm.linux.org.uk
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
arch/arm/mach
On 03/21/2014 10:43 PM, Sebastian Hesselbarth wrote:
On 03/21/2014 08:39 PM, Alexandre Belloni wrote:
Now that we support Berlin BG2Q, select CONFIG_MACH_BERLIN_BG2Q so
that we can
boot BG2Q based boards like the BG2Q DMP.
Signed-off-by: Alexandre Belloni alexandre.bell...@free-electrons.com
shove this two lines above
right into sdhci_get_of_property()?
Besides the other comments from Joe, this looks good to me,
Reviewed-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
+
+ ret = sdhci_add_host(host);
+ if (ret)
+ goto err_add_host;
+
+ return 0
On 03/20/2014 09:39 PM, Sebastian Hesselbarth wrote:
This adds scu and general purpose registers device nodes required for
SMP on Berlin BG2 and BG2Q SoCs. The secondary CPUs will pick their jump
address from general purpose (SW generic) register 1.
Signed-off-by: Sebastian Hesselbarth
On 03/20/2014 09:39 PM, Sebastian Hesselbarth wrote:
This adds SMP support to Marvell Berlin2 SoCs. Secondary CPUs boot into
BootROM, wait for interrupt, and read SW generic register 1 with actual
boot code address. Synchronization by holding pen is copied from
plat-versatile and mach-prima2
On 04/16/2014 11:11 AM, Jisheng Zhang wrote:
On Wed, 16 Apr 2014 00:46:33 -0700
Antoine Ténart antoine.ten...@free-electrons.com wrote:
This series add the support for the GPIOs of the Berlin BG2Q. We use the
newly integrated dwapb GPIO driver here.
This applies on top of Alexandre's BG2Q
On 04/17/2014 05:33 AM, Jisheng Zhang wrote:
On Wed, 16 Apr 2014 05:40:10 -0700
Antoine Ténart antoine.ten...@free-electrons.com wrote:
Add the SDHCI nodes for the Marvell Berlin BG2Q, using the berlin-sdhci
driver.
[...]
+sdhci0: sdhci@ab {
+compatible =
On 04/17/2014 03:13 PM, Antoine Ténart wrote:
On Fri, Apr 11, 2014 at 11:05:41AM +0200, Sebastian Hesselbarth wrote:
On 04/10/2014 03:07 PM, Antoine Ténart wrote:
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
arch/arm/mach-berlin/Kconfig | 2 ++
1 file changed, 2
On 04/18/2014 12:22 PM, Gregory CLEMENT wrote:
For the armada 38x SoCs which come with an xhci controller, specific
initialization must be done during probe, especially in relation with
the MBus windows initialization. This patch adds this support.
Signed-off-by: Gregory CLEMENT
On 04/18/2014 12:22 PM, Gregory CLEMENT wrote:
The usb3-utmi registers allow to configure the internal USB PHY of the
Armada 380/385 SoCs. A small initialization is needed to be able to use
the USB3 ports.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
On 04/18/2014 12:22 PM, Gregory CLEMENT wrote:
The Marvell Armada 38x SoCs contain two xHCI host. This commit adds
the Device Tree description of those interfaces at the SoC level, and
also enables the two USB3 ports on the Armada 385 DB platform and one
USB3 port on the Armada 385 RD
On 04/18/2014 01:43 PM, Gregory CLEMENT wrote:
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2014 Marvell
+ *
+ * Gregory Clement gregory.clem...@free-electrons.com
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed as is
On 04/10/2014 03:07 PM, Antoine Ténart wrote:
The Marvell Berlin boards have a group based pinmuxing mechanism. This
driver adds the support for the BG2CD, BG2 and BG2Q. We actually do not
need any information about the pins here and only have the definition
of the groups.
Antoine,
as always,
On 04/10/2014 03:07 PM, Antoine Ténart wrote:
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
arch/arm/mach-berlin/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-berlin/Kconfig b/arch/arm/mach-berlin/Kconfig
index d3c5f14dc142..291f1cac6c3d
On 04/10/2014 03:07 PM, Antoine Ténart wrote:
Missing commit message.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
.../bindings/pinctrl/marvell,berlin-pinctrl.txt| 43 ++
1 file changed, 43 insertions(+)
create mode 100644
On 04/11/2014 11:09 AM, Antoine Ténart wrote:
Hi Andrew,
On Fri, Apr 11, 2014 at 10:18:59AM +0200, Andrew Lunn wrote:
On Thu, Apr 10, 2014 at 03:07:54PM +0200, Antoine Ténart wrote:
The uart0 pinmux configuration is in the dtsi because uart0 will always
use uart0-pmux to work, no other
On 04/10/2014 03:07 PM, Antoine Ténart wrote:
When using a group only pinctrl driver, which does not have any
information on the pins it is useless to define a get_group_pins
always returning an empty list of pins.
When not using get_group_pin[1], a driver must implement it so
pins = NULL and
On 04/11/2014 02:37 PM, Antoine Ténart wrote:
On Fri, Apr 11, 2014 at 11:03:48AM +0200, Sebastian Hesselbarth wrote:
On 04/10/2014 03:07 PM, Antoine Ténart wrote:
The Marvell Berlin boards have a group based pinmuxing mechanism. This
driver adds the support for the BG2CD, BG2 and BG2Q. We
On 04/02/2014 09:01 PM, Florian Fainelli wrote:
2014-04-02 2:09 GMT-07:00 Alexander Holler hol...@ahsoftware.de:
Am 02.04.2014 02:57, schrieb Florian Fainelli:
2014-04-01 16:55 GMT-07:00 Alexander Holler hol...@ahsoftware.de:
Commit 7cd1463664c2a15721ff4ccfb61d4d970815cb3d (introduced with
On 04/03/2014 12:12 AM, Alexander Holler wrote:
Am 02.04.2014 22:25, schrieb Sebastian Hesselbarth:
On 04/02/2014 09:01 PM, Florian Fainelli wrote:
2014-04-02 2:09 GMT-07:00 Alexander Holler hol...@ahsoftware.de:
Am 02.04.2014 02:57, schrieb Florian Fainelli:
2014-04-01 16:55 GMT-07:00
On 04/02/2014 11:09 AM, Alexander Holler wrote:
Am 02.04.2014 02:57, schrieb Florian Fainelli:
Could you verify the following two things before your patch gets merged:
- how long does it take for your PHY to clear the BMCR_RESET bit, is
it more than the allowed time out in
On 04/03/2014 09:17 AM, Alexander Holler wrote:
Am 03.04.2014 00:27, schrieb Sebastian Hesselbarth:
On 04/03/2014 12:12 AM, Alexander Holler wrote:
I am curious, how you determined above commit to be the cause of the
regression you are seeing. Can you bisect, if you didn't already
On 04/03/2014 09:14 AM, Antoine Ténart wrote:
On 03/04/2014 10:54, Antoine Ténart wrote:
On 03/04/2014 10:22, Jisheng Zhang wrote:
On Thu, 3 Apr 2014 01:08:15 -0700
Antoine Ténart antoine.ten...@free-electrons.com wrote:
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
Legacy dove_mpp_gpio_mode calls orion_gpio_set_valid which is in
__init section. Offending function is not, so this causes a section
mismatch. To fix the mismatch, also move dove_mpp_gpio_mode to
__init section.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Jason
obsolete functions by
removing those.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Jason Cooper ja...@lakedaemon.net
Cc: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Cc: Kyungmin Park kyungmin.p...@samsung.com
Cc: Andrew Morton a...@linux-foundation.org
Cc: linux
On 07/01/13 17:04, Jason Cooper wrote:
On Mon, Jul 01, 2013 at 04:56:29PM +0200, Sebastian Hesselbarth wrote:
Commit 834cbfe966bece50afded79da8e975d255bf0772
(drivers/dma: remove unused support for MEMSET operations)
removes MEMSET from dmaengine but does not completely removes it from
On 07/01/13 19:24, Bartlomiej Zolnierkiewicz wrote:
On Monday, July 01, 2013 11:17:20 AM Jason Cooper wrote:
On Mon, Jul 01, 2013 at 05:14:25PM +0200, Sebastian Hesselbarth wrote:
On 07/01/13 17:04, Jason Cooper wrote:
On Mon, Jul 01, 2013 at 04:56:29PM +0200, Sebastian Hesselbarth wrote
On 07/01/2013 11:41 PM, Andrew Morton wrote:
On Mon, 1 Jul 2013 17:37:06 -0400 Jason Cooperja...@lakedaemon.net wrote:
Please take a look at the email from lkml I just forwarded to you. I
believe this solves your problem, but I don't have time to look closely
atm.
Unhelpful. Can the rest
DMA API and mv_xor driver.
The second patch fixes compilation of orion5x edmini_v2 by adding a
missing include.
devicetree-discuss is added on Cc for completeness, this is all Marvell
related and should go through Jason Cooper's branch if there are no
objections.
Sebastian Hesselbarth (2):
ARM
edmini_v2-setup is missing an include of linux/mbus.h which causes
compiler error because of missing reference to mvebu_mbus_add_window.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Russell King li...@arm.linux.org.uk
Cc: Jason Cooper ja...@lakedaemon.net
Cc
DMA_MEMSET support has been removed, so update the device tree files
and corresponding binding documentation for Marvell SoCs.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Russell King li...@arm.linux.org.uk
Cc: Jason Cooper ja...@lakedaemon.net
Cc: Andrew Lunn
With DT support for mv643xx_eth we do not need legacy platform_data
based setup for DT enabled boards anymore.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Changelog:
v5-v6:
- rebase for v3.11-rc1
Cc: Russell King li...@arm.linux.org.uk
Cc: Jason Cooper ja
With DT support for mv643xx_eth board specific init for some boards now
is unneccessary. Remove those board files, Kconfig entries, and
corresponding entries in kirkwood_defconfig.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Changelog:
v5-v6:
- rebase for v3.11-rc1
This patch adds mv643xx_eth and mvmdio device tree nodes for DT enabled
Orion5x boards. Phy nodes are also added with reg property set on a
per-board basis.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Changelog:
v5-v6:
- rebase for v3.11-rc1
Cc: Russell King li
This patch adds orion-eth and mvmdio device tree nodes for DT enabled
Dove boards. As there is only one ethernet controller on Dove, a default
phy node is also added with a note to set its reg property on a per-board
basis.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
With all boards converted to DT enabled mv643xx_eth we can now
remove the clock alias for gbe clocks.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Changelog:
v5-v6:
- rebase for v3.11-rc1
Cc: Russell King li...@arm.linux.org.uk
Cc: Jason Cooper ja...@lakedaemon.net
Cc
With DT support for mv643xx_eth we do not need legacy platform_data
based setup for DT enabled boards. This patch removes eth setup
for all orion5x DT board files.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Changelog:
v5-v6:
- rebase for v3.11-rc1
Cc: Russell King
This patch adds mv643xx_eth and mvmdio device tree nodes for DT enabled
Kirkwood boards. Phy nodes are also added with reg property set on a
per-board basis.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Changelog:
v5-v6:
- rebase for v3.11-rc1
- also convert Sheevaplug
if there are no objections.
Sebastian Hesselbarth (7):
ARM: dove: add gigabit ethernet and mvmdio device tree nodes
ARM: kirkwood: add gigabit ethernet and mvmdio device tree nodes
ARM: orion5x: add gigabit ethernet and mvmdio device tree nodes
ARM: dove: remove legacy mv643xx_eth setup
ARM
With recent support for true irqchip and clocksource drivers for Orion
SoCs, now make use of it on DT enabled Kirkwood boards.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Russell King li...@arm.linux.org.uk
Cc: Jason Cooper ja...@lakedaemon.net
Cc: Andrew Lunn
With recent support for true irqchip and clocksource drivers for Orion
SoCs, now make use of it on DT enabled Kirkwood boards.
This also introduces a new Kconfig option for legacy (non-DT) Kirkwood
where old code is moved out to and polishes DT board file a little bit.
Signed-off-by: Sebastian
and just because orion-intc binding documentation already
reflects new reg layout, we convert orion5x DT now.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Russell King li...@arm.linux.org.uk
Cc: Jason Cooper ja...@lakedaemon.net
Cc: Andrew Lunn and...@lunn.ch
Cc: Thomas
With irqchip driver for Orion SoCs, reg layout of orion-intc has changed.
This updates irq driver stub implemented before to the new reg layout by
adding an offset to the base address passed by DT node. As orion5x still
uses this stub, it cannot be removed yet.
Signed-off-by: Sebastian
With recent support for true irqchip and clocksource drivers for Orion
SoCs, now make use of it on DT enabled Dove boards.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Russell King li...@arm.linux.org.uk
Cc: Jason Cooper ja...@lakedaemon.net
Cc: Andrew Lunn
Kirkwood DT boards have been converted to DT SDIO already, we can now
remove the legacy clock gate workaround for SDIO clock.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Russell King li...@arm.linux.org.uk
Cc: Jason Cooper ja...@lakedaemon.net
Cc: Andrew Lunn
the irq driver DT stub in
plat-orion/irq to reflect the changed reg layout. The irq driver DT stub
is still used on Orion5x until proper DT clk provider is available.
The patch set has been tested on Dove, and compile-tested on Kirkwood
and Orion5x defconfig.
Sebastian Hesselbarth (7):
ARM: dove: move
With recent support for true irqchip and clocksource drivers for Orion
SoCs, now make use of it on DT enabled Dove boards.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Russell King li...@arm.linux.org.uk
Cc: Jason Cooper ja...@lakedaemon.net
Cc: Andrew Lunn
On 07/02/13 13:53, Jason Cooper wrote:
On Tue, Jul 02, 2013 at 01:03:41PM +0200, Sebastian Hesselbarth wrote:
With recent support for true irqchip and clocksource drivers for Orion
SoCs, now make use of it on DT enabled Kirkwood boards.
This also introduces a new Kconfig option for legacy (non
With recent support for true irqchip and clocksource drivers for Orion
SoCs, now make use of it on DT enabled Kirkwood boards.
This also introduces a new Kconfig option for legacy (non-DT) Kirkwood
where old code is moved out to and polishes DT board file a little bit.
Signed-off-by: Sebastian
to iwmmxt_task_enable().
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Reported-by: Jean-Francois Moine moin...@free.fr
Fixes: 431a84b1a4f7 (ARM: 8034/1: Disable preemption in iwmmxt_task_enable())
---
The offending commit was intoduced past v3.15-rc1 and the corresponding fix
should
to the correct nodes.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Jason,
this should go in as a fix for v3.16 where above commit appeared first.
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Ian Campbell
On 06/04/2014 06:03 PM, Antoine Ténart wrote:
Adds SMP support for Berlin SoCs. Secondary CPUs are reset, then
execute the instruction we put in the reset exception register, setting
the pc at the address contained in the software reset address register,
which is the physical address of the
On 06/04/2014 06:03 PM, Antoine Ténart wrote:
Document the CPU control compatible, needed for the SMP support on
Marvell Berlin SoCs.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
Applied patches 2-5 to berlin/dt.
Thanks!
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On 07/18/2014 03:57 PM, Tejun Heo wrote:
On Fri, Jul 18, 2014 at 02:29:59PM +0200, Antoine Ténart wrote:
In both cases we do not have time to do this for the next release, as
the request popped up quite late.
So as of now:
- Either the series is merged as is and changes to the AHCI
On 06/29/2014 09:18 AM, Himangi Saraogi wrote:
The failure value of dev_get_regmap is NULL. Hence, the return value is
changed to -ENODEV.
A simplified version of the semantic match that finds this problem is as
follows:
// smpl
@@
expression e1;
@@
* if (!e1)
return PTR_ERR(e1);
// /smpl
On 06/30/2014 11:59 AM, Antoine Ténart wrote:
On Wed, Jun 25, 2014 at 11:03:25PM +0400, Sergei Shtylyov wrote:
On 06/23/2014 05:39 PM, Antoine Ténart wrote:
+ /* set the controller speed */
+ writel(0x31, ctrl_reg + PORT_SCR_CTL);
Value undocumented? Or is this the SATA
On 07/01/2014 02:21 AM, Peter Chen wrote:
On Mon, Jun 30, 2014 at 03:33:13PM +0200, Antoine Ténart wrote:
On Fri, Jun 27, 2014 at 11:25:07AM +0800, Peter Chen wrote:
On Tue, Jun 24, 2014 at 12:35:16PM +0200, Antoine Ténart wrote:
+
+static const struct of_device_id ci_hdrc_generic_of_match[]
From: Russell King rmk+ker...@arm.linux.org.uk
Add the Marvell Dove LCD controller DT binding documentation.
Signed-off-by: Russell King rmk+ker...@arm.linux.org.uk
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m
Thanks to Russell we have Armada DRM driver but currently DT support
for it is stalled in various discussions/improvements. We know there
are issues with the whole DRM chain (si5351,lcd,tda998x) that are not
easy to track down. To get at least some more code testing coverage,
this patch set picks
...@arm.linux.org.uk
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Russell King rmk+ker...@arm.linux.org.uk
Cc: Jason Cooper ja...@lakedaemon.net
Cc: Andrew Lunn and...@lunn.ch
Cc: Gregory Clement gregory.clem...@free-electrons.com
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux
From: Russell King rmk+ker...@arm.linux.org.uk
Add the DT fragment for the Marvell Dove LCD controllers.
Signed-off-by: Russell King rmk+ker...@arm.linux.org.uk
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m
From: Russell King rmk+ker...@arm.linux.org.uk
This enables lcd0 on SolidRun CuBox which is connected to TDA998x
HDMI transmitter. Also, set the external video clock connected to
Si5351 clock generator.
Signed-off-by: Russell King rmk+ker...@arm.linux.org.uk
Signed-off-by: Sebastian Hesselbarth
On 07/01/2014 03:10 PM, Russell King - ARM Linux wrote:
On Tue, Jul 01, 2014 at 03:04:31PM +0200, Sebastian Hesselbarth wrote:
+ pdev = platform_device_register_full(armada_drm_dev_info);
+ /* assign last found lcd node to drm device for clk lookup */
+ pdev-dev.of_node
On 07/01/2014 03:36 PM, Russell King - ARM Linux wrote:
On Tue, Jul 01, 2014 at 03:21:41PM +0200, Sebastian Hesselbarth wrote:
On 07/01/2014 03:10 PM, Russell King - ARM Linux wrote:
On Tue, Jul 01, 2014 at 03:04:31PM +0200, Sebastian Hesselbarth wrote:
If you want to do this then you need
On 07/08/2014 02:29 PM, Kishon Vijay Abraham I wrote:
On Monday 07 July 2014 03:46 PM, Antoine Ténart wrote:
The Berlin SoC has a two SATA ports. Add a PHY driver to handle them.
The mode selection can let us think this PHY can be configured to fit
other purposes. But there are reasons to
to iwmmxt_task_enable().
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Reported-by: Jean-Francois Moine moin...@free.fr
Fixes: 431a84b1a4f7 (ARM: 8034/1: Disable preemption in iwmmxt_task_enable())
---
The offending commit was intoduced past v3.15-rc1 and the corresponding fix
should
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