Add a new macro DWAPB_MAX_GPIOS which defines the maximum possible number
of GPIO lines corresponding to the maximum DW APB GPIO controller port
width. Use the new macro instead of number literal 32 where it's
applicable.
Suggested-by: Andy Shevchenko
Signed-off-by: Serge Semin
---
dr
: Serge Semin
Reviewed-by: Andy Shevchenko
---
Changelog v2:
- This is a new patch detached from commit
"gpio: dwapb: Convert driver to using the GPIO-lib-based IRQ-chip".
---
drivers/gpio/gpio-dwapb.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/drivers/gpio/gpio
It's redundant to have a vendor-specific property describing a number of
GPIOS while there is a generic one. Let's mark the former one as
deprecated and define the "ngpios" property supported with constraints
of being within [1; 32] range.
Signed-off-by: Serge Semin
Revi
be purely managed by the device resources interface.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
---
drivers/gpio/gpio-dwapb.c | 35 +--
1 file changed, 29 insertions(+), 6 deletions(-)
diff --git a/drivers/gpio/gpio-dwapb.c b/drivers/gpio/gpio
27;s.
- Add Andy' Suggested-by to the patch: "gpio: dwapb: Add max GPIOs macro"
- Add blank lines to the IRQ-chip conversion commit message to make it
more readable.
- Dynamically allocate memory for the IRQ-chip-related data.
Signed-off-by: Serge Semin
Cc: Andy Shevchenko
Cc:
osed to be applied on top of the series:
Link:
https://lore.kernel.org/dmaengine/20200723005848.31907-1-sergey.se...@baikalelectronics.ru
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Pavel Parkhomenko
Cc: Peter Ujfalusi
Cc: Andy Shevchenko
Cc: Rob Herring
Cc: dmaeng...@vger.kernel.org
Cc
from the
phandle arguments or the mask is zero, then the allocation will be
performed from a set of all channels provided by the DMA controller.
Signed-off-by: Serge Semin
---
.../devicetree/bindings/dma/snps,dma-spear1340.yaml| 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
roblem has been noticed for the channels synthesized with
max-burst-len=4.
Signed-off-by: Serge Semin
---
drivers/dma/dw/core.c| 4
drivers/dma/dw/of.c | 7 +--
include/linux/platform_data/dma-dw.h | 3 +++
3 files changed, 12 insertions(+), 2 deletions(-)
channel FIFO or
data items required to complete the block transfer, whichever is smaller;
length of burst transfers from memory is always equal to the space
available in a channel FIFO or number of data items required to complete
the block transfer, whichever is smaller.
Signed-off-by: Serge Semi
ialize channel
before each transfer") we can freely do that in the generic
dw_dma_initialize_chan() method.
Signed-off-by: Serge Semin
---
Note the DMA-engine repository git.infradead.org/users/vkoul/slave-dma.git
isn't accessible. So I couldn't find out the Andy' commit
y bus utilization and speed up the DMA-channel performance for
DMA_DEV_TO_MEM DMA-transfers.
Signed-off-by: Serge Semin
---
drivers/dma/dw/core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
index 4700f2e87a62..3da0aea9fe25 1006
On Thu, Jul 30, 2020 at 07:24:28PM +0300, Andy Shevchenko wrote:
> On Thu, Jul 30, 2020 at 06:45:42PM +0300, Serge Semin wrote:
> > CFGx.FIFO_MODE field controls a DMA-controller "FIFO readiness" criterion.
> > In other words it determines when to start pushing data out
On Thu, Jul 30, 2020 at 07:31:22PM +0300, Andy Shevchenko wrote:
> On Thu, Jul 30, 2020 at 06:45:44PM +0300, Serge Semin wrote:
> > According to the DW DMA controller Databook (page 40 "3.5 Memory
>
> Which version of it?
2.18b
>
> > Peripherals") memory
On Thu, Jul 30, 2020 at 07:41:46PM +0300, Andy Shevchenko wrote:
> On Thu, Jul 30, 2020 at 06:45:45PM +0300, Serge Semin wrote:
> > DW DMA IP-core provides a way to synthesize the DMA controller with
> > channels having different parameters like maximum burst-length,
> >
On Thu, Jul 30, 2020 at 07:47:03PM +0300, Andy Shevchenko wrote:
> On Thu, Jul 30, 2020 at 07:31:54PM +0300, Serge Semin wrote:
> > On Thu, Jul 30, 2020 at 07:24:28PM +0300, Andy Shevchenko wrote:
> > > On Thu, Jul 30, 2020 at 06:45:42PM +0300, Serge Semin wrote:
>
> ...
On Fri, Jul 31, 2020 at 12:10:16PM +0800, Jiaxun Yang wrote:
> Requested by downstream distros, a Kconfig option for default
> IEEE754 conformance mode allows them to set their mode to
> relaxed by default.
That's what should have been here in the first place. Thanks!
Reviewed-b
Hello Dinh,
It must be something wrong with your timer2 and timer3 declared in the Arria10
dts because the patch didn't change anything for the first two timers (timer0
and
timer1). It just permits to register all DW APB Timers found in dts.
If those timers are broken, then you should have disabl
river now supports any DMA back-end we must make sure the
DMA device configuration has been successful before proceeding with
further setups.
Signed-off-by: Serge Semin
---
drivers/spi/spi-dw-dma.c | 42 +---
1 file changed, 31 insertions(+), 11 deletions(-)
mainline repo. Alternatively the series could be merged in through the
DMA-engine repo.
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Georgy Vlasov
Cc: Ramil Zaripov
Cc: Pavel Parkhomenko
Cc: Peter Ujfalusi
Cc: Andy Shevchenko
Cc: Andy Shevchenko
Cc: Feng Tang
Cc: Vinod Koul
Cc: lin
unlimited number SG entries or Tx-only SPI transfer is requested. But
currently just use it for any SPI transfer.
Signed-off-by: Serge Semin
---
drivers/spi/spi-dw-dma.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-dw-dma.c b/drivers/spi/spi-dw-dma.c
ution described above is only executed if a full-duplex SPI
transfer is requested and the DMA engine hasn't provided channels with
hardware accelerated SG list traverse capability to handle both SG
lists at once.
Signed-off-by: Serge Semin
Suggested-by: Andy Shevchenko
---
drivers/spi/spi-dw-d
egister cleanup to a single place in the
dw_spi_dma_transfer_all() method.
Signed-off-by: Serge Semin
---
drivers/spi/spi-dw-dma.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/spi/spi-dw-dma.c b/drivers/spi/spi-dw-dma.c
index 32ef7913a73d..f8508
ed
SPI transfer initialization up a bit, particularly if the APB bus is
relatively slow.
Signed-off-by: Serge Semin
---
drivers/spi/spi-dw-dma.c | 29 ++---
1 file changed, 14 insertions(+), 15 deletions(-)
diff --git a/drivers/spi/spi-dw-dma.c b/drivers/spi/spi-dw-dma.c
ind
the DW APB SSI DMA driver code is still left in state as if Tx-buffer
might be optional, which is no longer true. Let's fix it so an error would
be returned if no Tx-buffer detected and DMA Tx would be always
enabled.
Signed-off-by: Serge Semin
---
drivers/spi/spi-dw-dma.c | 27 +--
methods are now responsible for
the DMA transactions submission, we also rename them to
dw_spi_dma_submit_{tx,rx}().
Signed-off-by: Serge Semin
---
drivers/spi/spi-dw-dma.c | 56 ++--
1 file changed, 31 insertions(+), 25 deletions(-)
diff --git a/drivers/spi/spi
: Serge Semin
---
drivers/spi/spi-dw-dma.c | 35 +--
1 file changed, 17 insertions(+), 18 deletions(-)
diff --git a/drivers/spi/spi-dw-dma.c b/drivers/spi/spi-dw-dma.c
index f8508c0c7978..2b42b42b6cf2 100644
--- a/drivers/spi/spi-dw-dma.c
+++ b/drivers/spi/spi-dw-dma.c
On Tue, May 19, 2020 at 05:42:13PM +0200, Thomas Bogendoerfer wrote:
> On Wed, May 06, 2020 at 08:42:30PM +0300, sergey.se...@baikalelectronics.ru
> wrote:
> > From: Serge Semin
> >
> > When XPA mode is enabled the normally 32-bits MAAR pair registers
> > are exte
On Tue, May 19, 2020 at 05:50:53PM +0200, Thomas Bogendoerfer wrote:
> On Mon, May 18, 2020 at 11:57:52PM +0300, Serge Semin wrote:
> > On Mon, May 18, 2020 at 06:32:06PM +0200, Thomas Bogendoerfer wrote:
> > > On Mon, May 18, 2020 at 04:48:20PM +0300, Serge Semin wrote:
>
On Tue, May 19, 2020 at 05:50:53PM +0200, Thomas Bogendoerfer wrote:
> On Mon, May 18, 2020 at 11:57:52PM +0300, Serge Semin wrote:
> > On Mon, May 18, 2020 at 06:32:06PM +0200, Thomas Bogendoerfer wrote:
> > > On Mon, May 18, 2020 at 04:48:20PM +0300, Serge Semin wrote:
>
On Wed, May 20, 2020 at 03:12:02PM +0300, Serge Semin wrote:
> On Tue, May 19, 2020 at 05:50:53PM +0200, Thomas Bogendoerfer wrote:
> > On Mon, May 18, 2020 at 11:57:52PM +0300, Serge Semin wrote:
> > > On Mon, May 18, 2020 at 06:32:06PM +0200, Thomas Bogendoerfer wrote:
>
On Wed, May 20, 2020 at 03:38:27PM +0200, Thomas Bogendoerfer wrote:
> On Wed, May 20, 2020 at 03:12:01PM +0300, Serge Semin wrote:
> > Since you don't like the way I initially fixed it, suppose there we don't
> > have
> > another way but to introduce something lik
On Wed, May 20, 2020 at 02:59:27PM +0300, Serge Semin wrote:
> On Tue, May 19, 2020 at 05:50:53PM +0200, Thomas Bogendoerfer wrote:
> > On Mon, May 18, 2020 at 11:57:52PM +0300, Serge Semin wrote:
> > > On Mon, May 18, 2020 at 06:32:06PM +0200, Thomas Bogendoerfer wrote:
>
On Wed, May 20, 2020 at 08:30:57PM +0200, Thomas Bogendoerfer wrote:
> On Wed, May 20, 2020 at 04:48:26PM +0300, Serge Semin wrote:
> > On Wed, May 20, 2020 at 03:38:27PM +0200, Thomas Bogendoerfer wrote:
> > > On Wed, May 20, 2020 at 03:12:01PM +0300, Serge Semin wrote:
>
On Wed, May 20, 2020 at 08:40:24PM +0200, Thomas Bogendoerfer wrote:
> On Wed, May 20, 2020 at 02:59:26PM +0300, Serge Semin wrote:
> > I think there is a misunderstanding here. In this patch I am not enabling
>
> you are right, I've missed the fact, that this also needs to
It's a Cluster Power Controller embedded into the MIPS IP cores.
Currently the corresponding dts node is supposed to have compatible
and reg properties.
Signed-off-by: Serge Semin
Reviewed-by: Rob Herring
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Paul Burton
Cc: Ralf Baechle
Cc:
lease 5 add MIPS64 Release 5 CPU support.
- Add CONFIG_CPS_NS16550_WIDTH config to select the UART registers accessors.
Co-developed-by: Alexey Malahov
Signed-off-by: Alexey Malahov
Signed-off-by: Serge Semin
Cc: Maxim Kaurkin
Cc: Pavel Parkhomenko
Cc: Ramil Zaripov
Cc: Ekaterina Skachk
It's a Common Device Memory Map controller embedded into the MIPS IP
cores, which dts node is supposed to have compatible and reg properties.
Signed-off-by: Serge Semin
Reviewed-by: Rob Herring
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Arnd Bergman
cific
Revision flag being set.
Fixes: 1aeba347b3a9 ("MIPS: Hardcode cpu_has_mips* where target ISA allows")
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
---
Ch
framework
with care. As soon as CPU frequency changes the clocksource framework
should be notified about this by marking the R4K timer being unstable
(which it really is, since the ticks rate has been changed synchronously
with the CPU frequency).
Signed-off-by: Serge Semin
Cc: Alexey Mala
in the CPU-freq transition event handler. We subscribe to that event
in the MIPS arch time-inititalization method.
Co-developed-by: Alexey Malahov
Signed-off-by: Alexey Malahov
Signed-off-by: Serge Semin
Reviewed-by: Jiaxun Yang
Cc: Thomas Bogendoerfer
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Arn
tial timer
frequency (mips_hpt_frequency) and pass the updated value further to the
clockevent framework.
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Greg Kroah-Hartman
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: devicet...@vger.
ed-by: Alexey Malahov
Signed-off-by: Alexey Malahov
Signed-off-by: Serge Semin
Cc: Thomas Bogendoerfer
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
---
Changelog v3:
- In accordance with MIPS32/64 Privileged Resource Architecture Extend
lahov
Signed-off-by: Alexey Malahov
Signed-off-by: Serge Semin
Cc: Thomas Bogendoerfer
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
---
arch/mips/Kconfig| 37 +++-
arch/mips/Makefile
d. In this case we just
ignore the MM field value.
Co-developed-by: Alexey Malahov
Signed-off-by: Alexey Malahov
Signed-off-by: Serge Semin
Cc: Thomas Bogendoerfer
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
---
Changelog v3:
- Repla
ilized.
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
---
arch/mips/include/asm/mipsregs.h | 19 +++
arch/mips/kernel/spram.c | 4 ++--
2 fi
platforms by default.
Signed-off-by: Serge Semin
Cc: Thomas Bogendoerfer
Cc: Alexey Malahov
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Greg Kroah-Hartman
Cc: Arnd Bergmann
Cc: Olof Johansson
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
---
drivers/bus/mips_cdmm.c
el configs.
Co-developed-by: Alexey Malahov
Signed-off-by: Alexey Malahov
Signed-off-by: Serge Semin
Cc: Thomas Bogendoerfer
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
---
Changelog v3:
- Together with MIPS32 add MIPS64 Release 5 sup
ff-by: Serge Semin
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
---
There might be another problem in cps-vec-ns16550.S connected with the
difference in CPU/devices endinanness on some platforms
CDMM may be available not only MIPS R2 architectures, but also in
newer MIPS R5 chips. For instance our P5600 chip has one. Lets mark
the CDMM bus being supported for that MIPS arch too.
Co-developed-by: Alexey Malahov
Signed-off-by: Alexey Malahov
Signed-off-by: Serge Semin
Reviewed-by
On Thu, May 21, 2020 at 03:34:29AM +0300, Serge Semin wrote:
>
[nip]
>
> This patchset is rebased and tested on the mainline Linux kernel 5.7-rc4:
> base-commit: 0e698dfa2822 ("Linux 5.7-rc4")
> tag: v5.7-rc4
Thomas,
Please note that this patchset is based on the Li
This binding file doesn't belong to the rtc seeing it's a pure timer
with no rtc facilities like days/months/years counting and alarms.
So move the YAML-file to the Documentation/devicetree/bindings/timer/
directory.
Signed-off-by: Serge Semin
Acked-by: Alexandre Belloni
Acked-by: R
Timer indicated by the "snps,dw-apb-timer"
compatible string and to provide a mandatory registers memory range,
one timer interrupt, either reference clock source or a fixed clock
rate value. It may also have an optional APB bus reference clock
phandle specified.
Signed-off-by: Serge Semin
R
led or
the CPU frequency is changed by means of the CPC core clock divider
available on the platforms with CM3 or newer.
Signed-off-by: Paul Burton
Co-developed-by: Serge Semin
[sergey.se...@baikalelectronics.ru: Register sched-clock if CM3 or !CPU-freq]
Signed-off-by: Serge Semin
Cc: Alexey M
ce as unstable instead of lowering its rating.
- Move conditional sched clocks registration to the Paul' patch.
- Add Thomas Gleixner to the patchset To-list to draw his attention to the
patch "dt-bindings: interrupt-controller: Convert mti,gic to DT schema".
Signed-off-by: Serg
evice for
clockevents tracking then it will be selected.
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Alessandro Zummo
Cc: Alexandre Belloni
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: linux-.
rce: dw_apb_timer_of: use clocksource_of_init")
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Alessandro Zummo
Cc: Alexandre Belloni
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: linux-...@vger.kernel.org
.
MIPS GIC also includes a free-running global timer, per-CPU count/compare
timers, and a watchdog. Since currently the GIC Timer is only supported the
DT schema expects an IRQ and clock-phandler charged timer sub-node with
"mti,mips-gic-timer" compatible string.
Signed-off-by: Serge S
why
it gets unstable is due to the ref clock rate change, which event we
detect here in the driver by means of the clocks event notifier.
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Alessandro Zummo
Cc: Alexandre Belloni
Cc: Ar
Co-developed-by: Ramil Zaripov
Signed-off-by: Ramil Zaripov
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Andy Shevchenko
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
---
ned-off-by: Georgy Vlasov
Signed-off-by: Serge Semin
Fixes: 7063c0d942a1 ("spi/dw_spi: add DMA support")
Cc: Ramil Zaripov
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Arnd Bergmann
Cc: Andy Shevchenko
Cc: Rob Herring
Cc: linux-m...@vger.ke
ov
Signed-off-by: Ramil Zaripov
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Arnd Bergmann
Cc: Andy Shevchenko
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
---
Changelog v3:
- Discard the dws
ed-by: Georgy Vlasov
Signed-off-by: Georgy Vlasov
Signed-off-by: Serge Semin
Cc: Ramil Zaripov
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Arnd Bergmann
Cc: Andy Shevchenko
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kerne
s in the debugfs_reg32 structure initializer and after the last
entry of the dw_spi_dbgfs_regs array.
Co-developed-by: Georgy Vlasov
Signed-off-by: Georgy Vlasov
Co-developed-by: Ramil Zaripov
Signed-off-by: Ramil Zaripov
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Maxim Kaurkin
Cc:
, DMA and slave device
sub-nodes are optional.
Signed-off-by: Serge Semin
Cc: Georgy Vlasov
Cc: Ramil Zaripov
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Arnd Bergmann
Cc: Andy Shevchenko
Cc: linux-m...@vger.kernel.org
---
.../bindings/spi/snps,dw-apb
. Especially seeing that we don't use anything DW DMAC
specific in the new driver.
Co-developed-by: Georgy Vlasov
Signed-off-by: Georgy Vlasov
Co-developed-by: Ramil Zaripov
Signed-off-by: Ramil Zaripov
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
Cc: Alexey Malahov
Cc: T
level to be of FIFO depth minus the
maximum burst transactions length. To prevent the Rx buffer underflow
the DMA Rx level should be set to the maximum burst transactions length.
This commit setups the DMA channels and the DW SPI DMA Tx/Rx levels
in accordance with these rules.
Signed-off-by: Serge
ripov
Signed-off-by: Ramil Zaripov
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Arnd Bergmann
Cc: Andy Shevchenko
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
---
dr
generic "snps,dw-apb-ssi" and "snps,dwc-ssi-1.01a"
devices.
Co-developed-by: Georgy Vlasov
Signed-off-by: Georgy Vlasov
Co-developed-by: Ramil Zaripov
Signed-off-by: Ramil Zaripov
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
Cc: Alexey Malahov
Cc: Thomas Bogendoer
On Tue, May 19, 2020 at 10:43:04PM +0530, Vinod Koul wrote:
> On 17-05-20, 20:47, Serge Semin wrote:
> > On Fri, May 15, 2020 at 02:11:13PM +0300, Serge Semin wrote:
> > > On Fri, May 15, 2020 at 04:26:58PM +0530, Vinod Koul wrote:
> > > > On 15-05-20, 13:51, Andy
On Tue, May 19, 2020 at 10:32:46PM +0530, Vinod Koul wrote:
> On 17-05-20, 22:23, Serge Semin wrote:
> > On Fri, May 15, 2020 at 12:00:39PM +0530, Vinod Koul wrote:
> > > Hi Serge,
> > >
> > > On 12-05-20, 15:42, Serge Semin wrote:
> > > > Vinod,
&g
On Tue, May 19, 2020 at 10:37:14PM +0530, Vinod Koul wrote:
> On 17-05-20, 22:38, Serge Semin wrote:
> > On Fri, May 15, 2020 at 12:09:50PM +0530, Vinod Koul wrote:
> > > On 12-05-20, 22:12, Andy Shevchenko wrote:
> > > > On Tue, May 12, 2020 at 05:08:20PM +0300, S
On Wed, May 20, 2020 at 03:16:07PM +0300, Jarkko Nikula wrote:
> On 5/10/20 12:50 PM, Serge Semin wrote:
> > Seeing the DW I2C driver is using flags-based accessors with two
> > conditional clauses it would be better to replace them with the regmap
> > API IO methods and to
On Wed, May 20, 2020 at 03:16:14PM +0300, Jarkko Nikula wrote:
> On 5/10/20 12:50 PM, Serge Semin wrote:
> > Currently Intel Baytrail I2C semaphore is a feature of the DW APB I2C
> > platform driver. It's a bit confusing to see it's config in the menu at
> > some se
On Wed, May 20, 2020 at 03:46:11PM +0300, Jarkko Nikula wrote:
> Hi
>
> On 5/10/20 12:50 PM, Serge Semin wrote:
> > Seeing the DW I2C platform driver is getting overcomplicated with a lot of
> > vendor-specific configs let's introduce a glue-layer interface so new
&g
Hello Feng,
On Thu, May 21, 2020 at 11:09:24AM +0800, Feng Tang wrote:
> Hi Serge,
>
> On Thu, May 21, 2020 at 04:21:51AM +0300, Serge Semin wrote:
[nip]
> > /*
> > * dws->dma_chan_busy is set before the dma transfer starts, callback for
> > rx
> >
On Thu, May 21, 2020 at 01:25:21PM +0300, Sergei Shtylyov wrote:
> Hello!
>
> On 21.05.2020 3:34, Serge Semin wrote:
>
> > CDMM may be available not only MIPS R2 architectures, but also in
> ^ on -re, it's singular
Thanks, S
Hello Arnd.
On Thu, May 21, 2020 at 09:30:08AM +0200, Arnd Bergmann wrote:
> On Thu, May 21, 2020 at 9:18 AM Thomas Bogendoerfer
> wrote:
> > On Thu, May 21, 2020 at 03:42:17AM +0300, Serge Semin wrote:
> > > On Thu, May 21, 2020 at 03:34:29AM +0300, Serge Semin wrote:
On Thu, May 21, 2020 at 09:14:57AM +0200, Thomas Bogendoerfer wrote:
> On Thu, May 21, 2020 at 03:42:17AM +0300, Serge Semin wrote:
> > On Thu, May 21, 2020 at 03:34:29AM +0300, Serge Semin wrote:
> > >
> > > This patchset is rebased and tested on the mainline Linux
e 5 add MIPS64 Release 5 CPU support.
- Add CONFIG_CPS_NS16550_WIDTH config to select the UART registers accessors.
Changelog v4:
- Discard commit 37353ec964e8 ("mips: MAAR: Use more precise address mask")
from the series as a fixup has been integrated into the kernel.
- Rebase o
It's a Cluster Power Controller embedded into the MIPS IP cores.
Currently the corresponding dts node is supposed to have compatible
and reg properties.
Signed-off-by: Serge Semin
Reviewed-by: Rob Herring
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Paul Burton
Cc: Ralf Baechle
Cc:
It's a Common Device Memory Map controller embedded into the MIPS IP
cores, which dts node is supposed to have compatible and reg properties.
Signed-off-by: Serge Semin
Reviewed-by: Rob Herring
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Arnd Bergman
in the CPU-freq transition event handler. We subscribe to that event
in the MIPS arch time-inititalization method.
Co-developed-by: Alexey Malahov
Signed-off-by: Alexey Malahov
Signed-off-by: Serge Semin
Reviewed-by: Jiaxun Yang
Cc: Thomas Bogendoerfer
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Arn
d. In this case we just
ignore the MM field value.
Co-developed-by: Alexey Malahov
Signed-off-by: Alexey Malahov
Signed-off-by: Serge Semin
Cc: Thomas Bogendoerfer
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
---
arch/mips/inclu
CDMM may be available not only on MIPS R2 architectures, but also on
newer MIPS R5 chips. For instance our P5600 chip has one. Let's mark
the CDMM bus being supported for that MIPS arch too.
Co-developed-by: Alexey Malahov
Signed-off-by: Alexey Malahov
Signed-off-by: Serge Semin
Review
el configs.
Co-developed-by: Alexey Malahov
Signed-off-by: Alexey Malahov
Signed-off-by: Serge Semin
Cc: Thomas Bogendoerfer
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
---
arch/mips/Kconfig| 56
platforms by default.
Signed-off-by: Serge Semin
Cc: Thomas Bogendoerfer
Cc: Alexey Malahov
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Greg Kroah-Hartman
Cc: Arnd Bergmann
Cc: Olof Johansson
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
---
drivers/bus/mips_cdmm.c
ff-by: Serge Semin
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
---
arch/mips/Kconfig.debug| 10 ++
arch/mips/kernel/cps-vec-ns16550.S | 18 --
2 files change
ilized.
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
---
arch/mips/include/asm/mipsregs.h | 19 +++
arch/mips/kernel/spram.c | 4 ++--
2 fi
cific
Revision flag being set.
Fixes: 1aeba347b3a9 ("MIPS: Hardcode cpu_has_mips* where target ISA allows")
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
---
a
lahov
Signed-off-by: Alexey Malahov
Signed-off-by: Serge Semin
Cc: Thomas Bogendoerfer
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
---
arch/mips/Kconfig | 37 +-
arch/mips/Makefile
framework
with care. As soon as CPU frequency changes the clocksource framework
should be notified about this by marking the R4K timer being unstable
(which it really is, since the ticks rate has been changed synchronously
with the CPU frequency).
Signed-off-by: Serge Semin
Cc: Alexey Mala
tial timer
frequency (mips_hpt_frequency) and pass the updated value further to the
clockevent framework.
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Greg Kroah-Hartman
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
On Thu, May 21, 2020 at 11:09:50AM +0200, Geert Uytterhoeven wrote:
> Hi Serge,
>
> On Thu, May 21, 2020 at 2:54 AM Serge Semin
> wrote:
> > Currently clocksource framework doesn't support the clocks with variable
> > frequency. Since MIPS GIC timer ticks r
Daniel,
On Thu, May 21, 2020 at 03:53:17AM +0300, Serge Semin wrote:
> Currently the DW APB Timer driver binds all clockevent timers to
> CPU #0. This isn't good for multiple reasons. First of all seeing
> the device is placed on APB bus (which makes it accessible from any
> CPU
On Thu, May 21, 2020 at 08:57:10AM -0600, Rob Herring wrote:
> On Mon, May 18, 2020 at 3:27 PM Serge Semin
> wrote:
> >
> > On Mon, May 18, 2020 at 09:26:59AM -0600, Rob Herring wrote:
> > > On Fri, May 08, 2020 at 12:36:20PM +0300, Serge Semin wrote:
> > > &
On Thu, May 21, 2020 at 10:55:20PM +0800, Feng Tang wrote:
> Hi Serge,
>
> On Thu, May 21, 2020 at 02:47:36PM +0300, Serge Semin wrote:
> > Hello Feng,
> >
> > On Thu, May 21, 2020 at 11:09:24AM +0800, Feng Tang wrote:
> > > Hi Serge,
> > >
> >
On Thu, May 21, 2020 at 04:51:43PM +0100, Mark Brown wrote:
> On Thu, May 21, 2020 at 03:12:28PM +0300, Serge Semin wrote:
>
> > Well, for me both solutions are equal except mine consumes less stack
> > memory.
> > The only reason why your solution might be better
On Thu, May 21, 2020 at 06:12:03PM +0100, Mark Brown wrote:
> On Thu, May 21, 2020 at 12:03:58PM -0500, Dinh Nguyen wrote:
> > Add mechanism to get the reset control and deassert it in order to bring
> > the IP out of reset.
> >
> > Signed-off-by: Liang Jin J
> > Signed-off-by: Dinh Nguyen
>
>
On Thu, May 21, 2020 at 05:39:04PM +0100, Mark Brown wrote:
> On Thu, May 21, 2020 at 07:02:32PM +0300, Andy Shevchenko wrote:
> > On Thu, May 21, 2020 at 6:58 PM Serge Semin
>
> > > Let's leave the patch as is.
>
> > Mark, should I send a partial revert a
registered after the platform-specific one.
So in order to fix all of these issues let's make the DW APB Timer CPU
affinity being optional and deactivated by passing a negative CPU id,
which will effectively set the DW APB clockevent timer cpumask to
'cpu_possible_mask'.
Signed-off-by:
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