[BUG] increased us/sys-load due to tty-layer in 2.6.38+ ?!

Hi! I noticed a problem with the tty subsystem on ARM. Starting with 2.6.38+ load on the serial connection causes a 10-15% increase in system/userspace load. This doesn't change up to v3.9-rc4. The following setup was used: telnet screen microcom -p /dev/ttyUSB0 |

Re: [BUG] increased us/sys-load due to tty-layer in 2.6.38+ ?!

On Mon, Apr 08, 2013 at 08:06:11AM -0700, Greg Kroah-Hartman wrote: On Mon, Apr 08, 2013 at 11:25:58AM +0200, Steffen Trumtrar wrote: Hi! I noticed a problem with the tty subsystem on ARM. Starting with 2.6.38+ load on the serial connection causes a 10-15% increase in system/userspace

Re: [PATCH RESEND] fbmon: use VESA_DMT_VSYNC_HIGH to fix typo

On Fri, Mar 29, 2013 at 01:40:52AM +, Jingoo Han wrote: VESA_DMT_VSYNC_HIGH should be used instead of VESA_DMT_HSYNC_HIGH, because FB_SYNC_VERT_HIGH_ACT is related to vsync, not to hsync. Signed-off-by: Jingoo Han jg1@samsung.com Cc: Steffen Trumtrar s.trumt...@pengutronix.de Cc

Re: [PATCH 08/10] video: da8xx-fb: obtain fb_videomode info from dt

Hi! On Mon, Jan 07, 2013 at 10:41:30AM +0530, Afzal Mohammed wrote: Obtain fb_videomode details for the connected lcd panel using the display timing details present in DT. Signed-off-by: Afzal Mohammed af...@ti.com --- .../devicetree/bindings/video/fb-da8xx.txt | 20

Re: [PATCH v5] regulator: pfuze100: add pfuze100 regulator driver

pfuze_regulator_platform_data { + struct regulator_init_data *init_data[PFUZE100_MAX_REGULATOR]; +}; + +#endif /* __LINUX_REG_PFUZE100_H */ -- 1.7.5.4 Tested-by: Steffen Trumtrar s.trumt...@pengutronix.de Thanks, Steffen -- Pengutronix e.K

Re: [RFC 17/17] clk: zynq: remove call to of_clk_init

Hi! On Thu, Aug 22, 2013 at 05:59:36PM -0700, Sören Brinkmann wrote: On Thu, Aug 22, 2013 at 05:26:47PM -0700, Sören Brinkmann wrote: Hi Sebastian, On Tue, Aug 20, 2013 at 04:04:31AM +0200, Sebastian Hesselbarth wrote: With arch/arm calling of_clk_init(NULL) from time_init(), we can now

Re: [RFC 17/17] clk: zynq: remove call to of_clk_init

On Fri, Aug 23, 2013 at 07:44:03PM +0200, Sebastian Hesselbarth wrote: On 08/23/13 19:19, Sören Brinkmann wrote: On Fri, Aug 23, 2013 at 11:30:18AM +0200, Sebastian Hesselbarth wrote: On 08/23/13 02:59, Sören Brinkmann wrote: On Thu, Aug 22, 2013 at 05:26:47PM -0700, Sören Brinkmann wrote: On

Re: [RFC 17/17] clk: zynq: remove call to of_clk_init

On Fri, Aug 23, 2013 at 09:00:23AM -0700, Sören Brinkmann wrote: Hi Steffen, On Fri, Aug 23, 2013 at 09:32:50AM +0200, Steffen Trumtrar wrote: Hi! On Thu, Aug 22, 2013 at 05:59:36PM -0700, Sören Brinkmann wrote: On Thu, Aug 22, 2013 at 05:26:47PM -0700, Sören Brinkmann wrote

Re: [RFC 17/17] clk: zynq: remove call to of_clk_init

Hi Michal! On Mon, Aug 26, 2013 at 01:15:11PM +0200, Michal Simek wrote: On 08/23/2013 09:32 AM, Steffen Trumtrar wrote: Hi! On Thu, Aug 22, 2013 at 05:59:36PM -0700, Sören Brinkmann wrote: On Thu, Aug 22, 2013 at 05:26:47PM -0700, Sören Brinkmann wrote: Hi Sebastian, On Tue, Aug

Re: [RFC 17/17] clk: zynq: remove call to of_clk_init

Hi Michal, On Mon, Aug 26, 2013 at 05:14:25PM +0200, Michal Simek wrote: Steffen: Can you point me to that floading patches? If they are useful we can try them and help with pushing them to the mainline. I don't think that there is any reasonable solution without using these patches. I was

Re: [RFC 17/17] clk: zynq: remove call to of_clk_init

On Mon, Aug 26, 2013 at 08:16:29AM -0700, Sören Brinkmann wrote: On Mon, Aug 26, 2013 at 02:53:35PM +0200, Sebastian Hesselbarth wrote: On 08/26/13 14:07, Steffen Trumtrar wrote: On Mon, Aug 26, 2013 at 01:15:11PM +0200, Michal Simek wrote: I agree with Soren - let's fix the current problem

Re: MXS persistent bits driver

on that? Where would such a driver fit? Adding Steffen Trumtrar, as I came across his patch: http://permalink.gmane.org/gmane.linux.drivers.devicetree/31370 @Steffen, was there no answer to your questions about these being binary attributes? Hi! I didn't work on the driver after the v2

Re: [PATCH 3/3] arm: zynq: slcr: Use read-modify-write for register writes

On Wed, Jul 17, 2013 at 10:10:15AM -0700, Sören Brinkmann wrote: zynq_slcr_cpu_start/stop() ignored the current register state when writing to a register. Fixing this by implementing proper read-modify-write. Signed-off-by: Soren Brinkmann soren.brinkm...@xilinx.com ---

[PATCH] spi: dw-mmio: add oftree support

Allow probing the dw-mmio from devicetree. Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de --- This was tested on Socfpga and v3.14-rc6 .../devicetree/bindings/spi/spi-dw-mmio.txt| 25 ++ drivers/spi/spi-dw-mmio.c | 19

Re: [PATCH] spi: dw-mmio: add oftree support

Hi! On Fri, Mar 14, 2014 at 04:26:14PM +, Mark Brown wrote: On Fri, Mar 14, 2014 at 04:14:03PM +, Mark Rutland wrote: +Synopsys DesignWare SPI master controller. + +Required properties: +- compatible : snps,dw-spi-mmio Is there not a better name than dw-spi-mmio?

Re: [PATCH] ath6kl: sdio: fix system panic when doing wifi stress test

Hi! On Fri, Nov 29, 2013 at 06:02:11AM +, Hui Liu wrote: -Original Message- From: Kalle Valo [mailto:kv...@qca.qualcomm.com] Sent: Tuesday, November 26, 2013 6:40 PM To: Liu Hui-R64343 Cc: linux-arm-ker...@lists.infradead.org; linvi...@tuxdriver.com; linux-

Re: [PATCH] ath6kl: sdio: fix system panic when doing wifi stress test

On Sat, Mar 08, 2014 at 01:57:36PM +0200, Kalle Valo wrote: Hi Steffen, Steffen Trumtrar s.trumt...@pengutronix.de writes: Does the patch below help? It would also fix the corruption with scat_q_depth. Please note that I have only compile tested it. And I might have also missed

Re: [RFC 2/8] ARM:global_timer: Add ARM global timer support.

On Wed, May 08, 2013 at 04:38:22PM +0200, Arnd Bergmann wrote: On Wednesday 08 May 2013, Srinivas KANDAGATLA wrote: From: Stuart Menefy stuart.men...@st.com This is a simple driver for the global timer module found in the Cortex A9-MP cores from revision r1p0 onwards. This should be able

Re: [PATCH v2 3/3] arm: dt: zynq: Add support for the zed platform

On Wed, Jun 12, 2013 at 09:41:08AM -0700, Soren Brinkmann wrote: Add a DT fragment for the Zed Zynq platform and a corresponding target to the Makefile Signed-off-by: Soren Brinkmann soren.brinkm...@xilinx.com --- I used the 'xlnx,...' compat strings since it seems this is what is used in

Re: [PATCH v2 3/3] arm: dt: zynq: Add support for the zed platform

On Wed, Jun 12, 2013 at 11:26:34AM -0700, Sören Brinkmann wrote: On Wed, Jun 12, 2013 at 08:23:45PM +0200, Steffen Trumtrar wrote: On Wed, Jun 12, 2013 at 09:41:08AM -0700, Soren Brinkmann wrote: Add a DT fragment for the Zed Zynq platform and a corresponding target to the Makefile

Re: [PATCH v3 0/4] Zynq: Support more boards

+++ arch/arm/mach-zynq/common.c | 1 - 6 files changed, 80 insertions(+), 3 deletions(-) create mode 100644 arch/arm/boot/dts/zynq-zc706.dts create mode 100644 arch/arm/boot/dts/zynq-zed.dts -- 1.8.3 Hi! The series looks okay now: Reviewed-by: Steffen Trumtrar s.trumt

Re: [PATCH] net/macb: fix ISR clear-on-write behavior only for some SoC

On Tue, Jun 04, 2013 at 08:15:45AM +0200, Michal Simek wrote: On 05/14/2013 07:52 AM, Jean-Christophe PLAGNIOL-VILLARD wrote: On 08:58 Tue 14 May , Hein Tibosch wrote: On 5/14/2013 12:05 AM, Jean-Christophe PLAGNIOL-VILLARD wrote: On May 14, 2013, at 12:05 AM, Nicolas Ferre

Re: [PATCH] tty: serial: Enable uartlite for ARM zynq

On Tue, Jun 04, 2013 at 02:20:43PM +0200, Michal Simek wrote: Enable it in Kconfig. Signed-off-by: Michal Simek michal.si...@xilinx.com --- drivers/tty/serial/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/tty/serial/Kconfig

Re: [PATCH] tty: serial: Enable uartlite for ARM zynq

On Tue, Jun 04, 2013 at 02:52:34PM +0200, Michal Simek wrote: On 06/04/2013 02:43 PM, Steffen Trumtrar wrote: On Tue, Jun 04, 2013 at 02:20:43PM +0200, Michal Simek wrote: Enable it in Kconfig. Signed-off-by: Michal Simek michal.si...@xilinx.com --- drivers/tty/serial/Kconfig | 2

Re: [PATCH v3] pwm: add pca9685 driver

On Thu, May 30, 2013 at 09:50:12AM +0200, Steffen Trumtrar wrote: Add pwm driver for the NXP pca9685 16 channel pwm-led controller. The driver is really barebones at this stage. E.g. the OE' pin and therefore the corresponding registers are not supported. The driver was tested on a HW where

[PATCH v3] pwm: add pca9685 driver

Add pwm driver for the NXP pca9685 16 channel pwm-led controller. The driver is really barebones at this stage. E.g. the OE' pin and therefore the corresponding registers are not supported. The driver was tested on a HW where this pin is tied to GND. Signed-off-by: Steffen Trumtrar s.trumt

[PATCH] pwm: add pca9685 driver

Add pwm driver for the NXP pca9685 16 channel pwm-led controller. The driver is really barebones at this stage. E.g. the OE' pin and therefore the according registers are not supported. The driver was tested on a HW where this pin is tied to GND. Signed-off-by: Steffen Trumtrar s.trumt

[PATCH v2] pwm: add pca9685 driver

Add pwm driver for the NXP pca9685 16 channel pwm-led controller. The driver is really barebones at this stage. E.g. the OE' pin and therefore the according registers are not supported. The driver was tested on a HW where this pin is tied to GND. Signed-off-by: Steffen Trumtrar s.trumt

Re: [PATCH v2] pwm: add pca9685 driver

Hi! On Mon, May 27, 2013 at 09:13:34PM +0200, Thierry Reding wrote: On Mon, May 27, 2013 at 11:28:27AM +0200, Steffen Trumtrar wrote: Add pwm driver for the NXP pca9685 16 channel pwm-led controller. Please stick to the all-caps spelling of PWM in prose. Also why is this called pwm-led

Re: [PATCH] net/macb: fix ISR clear-on-write behavior only for some SoC

/ethernet/cadence/macb.c| 15 +-- drivers/net/ethernet/cadence/macb.h| 5 + 3 files changed, 20 insertions(+), 2 deletions(-) Looks okay to me: Acked-by: Steffen Trumtrar s.trumt...@pengutronix.de Thanks, Steffen -- Pengutronix e.K

Re: [PATCH v4] regulator: pfuze100: add pfuze100 regulator driver

Hi! I tested your patch and had to change two things to actually make it work. See below... On Sun, Jul 21, 2013 at 05:17:27PM +0800, Robin Gong wrote: Add pfuze100 regulator driver. Signed-off-by: Robin Gong b38...@freescale.com (...) --- diff --git

Re: [PATCH v4] regulator: pfuze100: add pfuze100 regulator driver

On Wed, Jul 24, 2013 at 10:42:28AM +0100, Mark Brown wrote: On Wed, Jul 24, 2013 at 10:30:41AM +0200, Steffen Trumtrar wrote: On Sun, Jul 21, 2013 at 05:17:27PM +0800, Robin Gong wrote: static struct regulator_ops pfuze100_fixed_regulator_ops = { .list_voltage

Re: [PATCH v4] regulator: pfuze100: add pfuze100 regulator driver

On Wed, Jul 24, 2013 at 06:07:18PM +0800, Robin Gong wrote: On Wed, Jul 24, 2013 at 10:30:41AM +0200, Steffen Trumtrar wrote: Hi! I tested your patch and had to change two things to actually make it work. See below... On Sun, Jul 21, 2013 at 05:17:27PM +0800, Robin Gong wrote

[PATCH v3] spi: dw-mmio: add devicetree support

Allow probing the dw-mmio from devicetree. Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de --- Changes since v2: - rebase to spi-v3.16 - add cs-gpios to optional properties Changes since v1: - num-chipselect - num-cs - snps,dw-spi-mmio - snps,dw-apb-ssi

Re: [PATCHv5 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM controller

Hi! On Tue, May 20, 2014 at 09:31:06AM -0500, Alan Tull wrote: On Mon, May 19, 2014 at 2:37 PM, Thor Thayer tthayer.li...@gmail.com wrote: diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt

[PATCH v2] spi: dw-mmio: add oftree support

Allow probing the dw-mmio from devicetree. Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de --- Changes since v1: - num-chipselect - num-cs - snps,dw-spi-mmio - snps,dw-apb-ssi .../devicetree/bindings/spi/snps,dw-apb-ssi.txt| 25 ++ drivers/spi

Re: [PATCHv5 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM controller

Hi! On Thu, May 15, 2014 at 11:04:49AM -0500, ttha...@altera.com wrote: From: Thor Thayer ttha...@altera.com Addition of the Altera SDRAM controller bindings and device tree changes to the Altera SoC project. v2: Changes to SoC SDRAM EDAC code. v3: Implement code suggestions for SDRAM

Re: [PATCHv5 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM controller

Hi Thor! On Mon, May 19, 2014 at 01:36:30PM -0500, Thor Thayer wrote: On Fri, May 16, 2014 at 2:53 AM, Steffen Trumtrar s.trumt...@pengutronix.de wrote: Hi! On Thu, May 15, 2014 at 11:04:49AM -0500, ttha...@altera.com wrote: From: Thor Thayer ttha...@altera.com Addition

Re: [PATCHv5 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM controller

On Wed, May 21, 2014 at 10:38:34AM -0500, Thor Thayer wrote: On Tue, May 20, 2014 at 9:44 AM, Steffen Trumtrar s.trumt...@pengutronix.de wrote: Hi! On Tue, May 20, 2014 at 09:31:06AM -0500, Alan Tull wrote: On Mon, May 19, 2014 at 2:37 PM, Thor Thayer tthayer.li...@gmail.com wrote

Re: [PATCHv5 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM controller

On Tue, May 27, 2014 at 02:12:17PM -0500, Alan Tull wrote: On Tue, May 27, 2014 at 2:11 AM, Steffen Trumtrar s.trumt...@pengutronix.de wrote: On Wed, May 21, 2014 at 10:38:34AM -0500, Thor Thayer wrote: On Tue, May 20, 2014 at 9:44 AM, Steffen Trumtrar s.trumt...@pengutronix.de wrote

Re: [PATCHv5 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM controller

On Tue, May 27, 2014 at 01:00:32PM -0500, Thor Thayer wrote: On Tue, May 27, 2014 at 2:11 AM, Steffen Trumtrar s.trumt...@pengutronix.de wrote: On Wed, May 21, 2014 at 10:38:34AM -0500, Thor Thayer wrote: On Tue, May 20, 2014 at 9:44 AM, Steffen Trumtrar s.trumt...@pengutronix.de wrote

Re: [PATCHv5 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM controller

On Tue, May 27, 2014 at 03:57:47PM -0500, Alan Tull wrote: On Tue, May 27, 2014 at 2:42 PM, Steffen Trumtrar s.trumt...@pengutronix.de wrote: On Tue, May 27, 2014 at 02:12:17PM -0500, Alan Tull wrote: On Tue, May 27, 2014 at 2:11 AM, Steffen Trumtrar s.trumt...@pengutronix.de wrote

Re: [PATCH v9] gpio: add a driver for Synopsys DesignWare APB GPIO

Hi! On Thu, Jan 30, 2014 at 01:40:04PM -0600, delicious quinoa wrote: On Thu, Dec 12, 2013 at 3:08 AM, Steffen Trumtrar s.trumt...@pengutronix.de wrote: Second: The interrupt is registered as GIC 37, which is a real interrupt on the Socfpga. I would expect it to be marked as GPIO 2xx

Re: [PATCH v9] gpio: add a driver for Synopsys DesignWare APB GPIO

On Thu, Jan 30, 2014 at 03:15:11PM -0600, delicious quinoa wrote: On Thu, Jan 30, 2014 at 2:50 PM, Steffen Trumtrar s.trumt...@pengutronix.de wrote: Hi! On Thu, Jan 30, 2014 at 01:40:04PM -0600, delicious quinoa wrote: On Thu, Dec 12, 2013 at 3:08 AM, Steffen Trumtrar s.trumt

Re: [PATCH v9] gpio: add a driver for Synopsys DesignWare APB GPIO

Hi Alan! On Wed, Dec 11, 2013 at 02:15:25PM -0600, delicious quinoa wrote: On Fri, Dec 6, 2013 at 3:09 PM, Alan Tull delicious.qui...@gmail.com wrote: From: Alan Tull at...@altera.com Hi Linus, If you don't have any further comments, can you take this patch? Alan Basically, this

Re: [PATCH RFC] leds: pca9685: Remove leds-pca9685 driver

Hi! On Sun, Apr 06, 2014 at 11:19:41AM +0800, Axel Lin wrote: This driver is replaced by pwm-pca9685 driver and there is no user uses this driver in current tree. So remove it. Signed-off-by: Axel Lin axel@ingics.com --- Hi, I found there is a modalias conflict between leds-pca9685.ko

Re: [PATCH v2 2/5] ARM: zynq: dt: Convert to preprocessor includes

Hi! On Mon, Apr 07, 2014 at 11:10:12AM -0600, Jason Gunthorpe wrote: On Mon, Apr 07, 2014 at 02:24:07PM +0200, Michal Simek wrote: Device-tree BSP and in 2014.01 there will be new BSP which just generate them directly from the Vivado tools which just target your reference design. You

Re: [PATCH 3/3] edac: altera: Add SDRAM EDAC support for CycloneV/ArriaV

On Tue, Apr 08, 2014 at 11:45:25AM +0100, Mark Rutland wrote: On Mon, Apr 07, 2014 at 10:54:09PM +0100, ttha...@altera.com wrote: From: Thor Thayer ttha...@altera.com Added EDAC support for reporting ECC errors of CycloneV and ArriaV SDRAM controller. - The SDRAM Controller registers

Re: [PATCH 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM controller

Hi! On Mon, Apr 07, 2014 at 04:54:07PM -0500, ttha...@altera.com wrote: From: Thor Thayer ttha...@altera.com Addition of the Altera SDRAM controller bindings and device tree changes to the Altera SoC project. Signed-off-by: Thor Thayer ttha...@altera.com To: Rob Herring

Re: [PATCH 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM controller

On Tue, Apr 08, 2014 at 09:29:50AM -0500, Thor Thayer wrote: On Tue, 2014-04-08 at 15:38 +0200, Steffen Trumtrar wrote: Hi! On Mon, Apr 07, 2014 at 04:54:07PM -0500, ttha...@altera.com wrote: From: Thor Thayer ttha...@altera.com Addition of the Altera SDRAM controller bindings

Re: socfpga in 3.15-rc2

...@altera.com Regards, Steffen -- Pengutronix e.K. | Steffen Trumtrar| Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686

Re: [PATCH 1/2] dts: socfpga: Add bindings for Altera SoC SDRAM controller

Hi! On Mon, Mar 31, 2014 at 05:07:06PM -0500, ttha...@altera.com wrote: From: Thor Thayer ttha...@altera.com Addition of the Altera SDRAM controller bindings and device tree changes to the Altera SoC project. Signed-off-by: Thor Thayer ttha...@altera.com To: Rob Herring

Re: [PATCH 2/2] arm: socfpga: Add support for Altera SoC SDRAM controller

On Mon, Mar 31, 2014 at 05:07:07PM -0500, ttha...@altera.com wrote: From: Thor Thayer ttha...@altera.com Addition of the Altera SDRAM controller registers to the Altera SoC project. These registers are shared by future drivers such as ECC and the FPGA bridge. Signed-off-by: Thor Thayer

Re: [PATCH 1/2] dts: socfpga: Add bindings for Altera SoC SDRAM controller

Hi! On Tue, Apr 01, 2014 at 03:11:41PM -0500, Thor Thayer - Sendmail wrote: On Tue, 2014-04-01 at 07:28 +0200, Steffen Trumtrar wrote: Hi! On Mon, Mar 31, 2014 at 05:07:06PM -0500, ttha...@altera.com wrote: From: Thor Thayer ttha...@altera.com Addition of the Altera SDRAM

[PATCH] w1: ds2482: add support for ds2482-101 sleep pin

The ds2482-101 version of the chip has an active-low sleep pin. Add this as a gpio to the probe function and describe the DT binding accordingly. If the pin wouldn't be added and pulled high, the device would not be able to be probed. Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de

Re: [PATCHv6 1/3] devicetree: Addition of the Altera SDRAM controller

Hi! On Fri, Jun 20, 2014 at 06:22:01PM -0500, ttha...@altera.com wrote: From: Thor Thayer ttha...@altera.com Addition of the Altera SDRAM Controller bindings and device tree changes. v2: Changes to SoC SDRAM EDAC code. v3: Implement code suggestions for SDRAM EDAC code. v4: Remove

Re: [PATCHv6 2/3] devicetree: Addition of the Altera SDRAM EDAC

On Fri, Jun 20, 2014 at 06:22:02PM -0500, ttha...@altera.com wrote: From: Thor Thayer ttha...@altera.com Addition of the Altera SDRAM EDAC bindings and device tree changes v2: Changes to SoC EDAC source code. v3: Fix typo in device tree documentation. v4,v5: No changes - bump version

Re: [PATCHv6 1/3] devicetree: Addition of the Altera SDRAM controller

On Sun, Jun 22, 2014 at 01:31:02PM -0500, Thor Thayer wrote: On Sat, Jun 21, 2014 at 4:04 AM, Steffen Trumtrar s.trumt...@pengutronix.de wrote: Hi! On Fri, Jun 20, 2014 at 06:22:01PM -0500, ttha...@altera.com wrote: From: Thor Thayer ttha...@altera.com Addition of the Altera SDRAM

Re: [PATCH 0/3] clk : Fix SOCFPGA clk crash and some clean up

Hi! As you touch clk.c, you should Cc Mike Turquette mturque...@linaro.org He is the maintainer for that code. Regards, Steffen -- Pengutronix e.K. | Steffen Trumtrar| Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner

Re: Power/battery/BQ27xxx: some fixes and hot-plug support

. | Steffen Trumtrar| Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | -- To unsubscribe from this list: send

Re: [PATCHv9 1/3] mfd: altera: Add Altera SDRAM Controller

Hi! On Fri, Aug 01, 2014 at 05:27:57PM -0500, Thor Thayer wrote: On 08/01/2014 03:13 AM, Lee Jones wrote: On Thu, 31 Jul 2014, Thor Thayer wrote: On 07/31/2014 03:26 AM, Lee Jones wrote: On Wed, 30 Jul 2014, ttha...@opensource.altera.com wrote: [...] +u32 altera_sdr_readl(struct

Re: [PATCHv10 2/2] arm: dts: Add Altera SDRAM EDAC bindings devicetree entries.

-- Pengutronix e.K. | Steffen Trumtrar| Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-

Re: [PATCHv10 2/2] arm: dts: Add Altera SDRAM EDAC bindings devicetree entries.

On Fri, Aug 15, 2014 at 11:07:31AM -0500, atull wrote: On Fri, 15 Aug 2014, Steffen Trumtrar wrote: Hi! Hello Thanks for the feedback... ttha...@opensource.altera.com writes: From: Thor Thayer ttha...@opensource.altera.com Add the Altera SDRAM EDAC bindings

Re: [PATCHv10 2/2] arm: dts: Add Altera SDRAM EDAC bindings devicetree entries.

On Fri, Aug 15, 2014 at 11:47:09AM -0500, Thor Thayer wrote: Hi Steffen! Building on Alan's points, I don't see the reference to the child nodes in the syscon.txt binding documentation - can you point out what I'm missing? I based this patch on other examples of syscon, and there aren't

Re: [PATCH v2 2/3] ARM: dts: socfpga: fpga bridges bindings docs

Hi! On Thu, Oct 23, 2014 at 06:51:06PM -0500, at...@opensource.altera.com wrote: From: Alan Tull at...@opensource.altera.com (...) diff --git a/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt b/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt new file

Re: [PATCH v2 2/3] ARM: dts: socfpga: fpga bridges bindings docs

Hi Pantelis! On Fri, Oct 24, 2014 at 12:20:53PM +0300, Pantelis Antoniou wrote: Hi Stefan, Allan, Sorry, haven’t had a chance to review all this yet; will do so in the weekend. Just wanted to pop in and comment on a few things. On Oct 24, 2014, at 10:00 AM, Steffen Trumtrar s.trumt

Re: [PATCH] reset: socfpga: use arch_initcall for early initialization

Hi! On Tue, Oct 14, 2014 at 01:45:29PM -0500, atull wrote: The FPGA bridge driver that I submitted last year handled the following things: * The bridges might have been brought out of reset in the bootloader. Some of the bridges have write-only registers (!) so this information had to

Re: [PATCH] reset: socfpga: use arch_initcall for early initialization

On Thu, Oct 09, 2014 at 08:16:18AM -0500, Dinh Nguyen wrote: Hi Philipp, On 10/9/14, 4:03 AM, Philipp Zabel wrote: Am Mittwoch, den 08.10.2014, 21:44 -0500 schrieb dingu...@opensource.altera.com: From: Dinh Nguyen dingu...@opensource.altera.com There are certain drivers that are

Re: [PATCH] reset: socfpga: use arch_initcall for early initialization

Hi! On Thu, Oct 09, 2014 at 09:57:49AM -0500, atull wrote: On Thu, 9 Oct 2014, Steffen Trumtrar wrote: On Thu, Oct 09, 2014 at 08:16:18AM -0500, Dinh Nguyen wrote: Hi Philipp, On 10/9/14, 4:03 AM, Philipp Zabel wrote: Am Mittwoch, den 08.10.2014, 21:44 -0500 schrieb dingu

[PATCH v2] w1: ds2482: add support for ds2482-101 sleep pin

The ds2482-101 version of the chip has an active-low sleep pin. Add this as a gpio to the probe function and describe the DT binding accordingly. Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de --- Changes since v1: - rebased to next-20141001 Documentation/devicetree/bindings

Re: [PATCH v2 2/3] ARM: dts: socfpga: fpga bridges bindings docs

Hi! On Mon, Oct 27, 2014 at 01:54:20PM +0200, Pantelis Antoniou wrote: Hi Stefen, On Oct 25, 2014, at 17:42 , Steffen Trumtrar s.trumt...@pengutronix.de wrote: Hi Pantelis! On Fri, Oct 24, 2014 at 12:20:53PM +0300, Pantelis Antoniou wrote: Hi Stefan, Allan, Sorry, haven’t

Re: [PATCH v2 2/3] ARM: dts: socfpga: fpga bridges bindings docs

On Mon, Oct 27, 2014 at 05:05:29PM +0200, Pantelis Antoniou wrote: Hi Mark, On Oct 27, 2014, at 17:01 , Mark Brown broo...@kernel.org wrote: On Mon, Oct 27, 2014 at 01:48:02PM +0200, Pantelis Antoniou wrote: On Oct 24, 2014, at 02:51 , at...@opensource.altera.com wrote: + -

Re: [PATCH v2 2/3] ARM: dts: socfpga: fpga bridges bindings docs

On Mon, Oct 27, 2014 at 05:52:02PM +0200, Pantelis Antoniou wrote: Hi Steffen, On Oct 27, 2014, at 17:23 , Steffen Trumtrar s.trumt...@pengutronix.de wrote: Hi! On Mon, Oct 27, 2014 at 01:54:20PM +0200, Pantelis Antoniou wrote: Hi Stefen, On Oct 25, 2014, at 17:42

Re: [PATCH v2 2/3] ARM: dts: socfpga: fpga bridges bindings docs

On Mon, Oct 27, 2014 at 05:45:03PM +0200, Pantelis Antoniou wrote: Hi Stefan, On Oct 27, 2014, at 17:32 , Steffen Trumtrar s.trumt...@pengutronix.de wrote: On Mon, Oct 27, 2014 at 05:05:29PM +0200, Pantelis Antoniou wrote: Hi Mark, On Oct 27, 2014, at 17:01 , Mark Brown broo

Re: [PATCH v2 2/3] ARM: dts: socfpga: fpga bridges bindings docs

Hi! On Tue, Oct 28, 2014 at 04:19:03PM -0500, atull wrote: On Fri, 24 Oct 2014, Steffen Trumtrar wrote: Hi! Hi, I see that my documentation sucks and needs cleanup. I'll try to answer some of the flames and get a more coherent version out soon. On Thu, Oct 23, 2014 at 06:51

Re: [PATCH v2 2/3] ARM: dts: socfpga: fpga bridges bindings docs

On Wed, Oct 29, 2014 at 10:16:32AM +, Mark Brown wrote: On Wed, Oct 29, 2014 at 08:57:01AM +0100, Steffen Trumtrar wrote: So, that shouldn't be a problem though, as I already cooked up a driver for the L3 with all the ranges specified. The only thing I need to figure out before I

Re: [RFC] pinctrl driver for Zynq

Hi! On Wed, Sep 24, 2014 at 02:09:14PM -0700, Sören Brinkmann wrote: Hi, I think I have pinctrl driver that is covering the pinmux options of Zynq and I also figured out how the DT bindings work. But there are a couple of things that probably could be done better. One thing making the

Re: [PATCH 2/2] socfpga: support suspend to ram

Hi! On Wed, Sep 24, 2014 at 03:27:29PM -0500, at...@opensource.altera.com wrote: From: Alan Tull at...@opensource.altera.com Add code that requests that the sdr controller go into self-refresh mode. This code is run from ocram. This patch assumes that u-boot has already configured sdr:

Re: [PATCH] ARM: socfpga: dts: Add adxl34x

Hi! On Tue, Dec 23, 2014 at 10:04:22AM -0300, Walter Lozano wrote: This patch adds the DTS bindings for the adxl34x digital accelerometer. Thanks for doing this. Does the ADXL34 work now? Last time I tried it, I didn't get any interrupts, but as I didn't really care for the accelerometer I

Re: [PATCH v6 4/4] staging: fpga manager: add driver for socfpga fpga manager

Hi! Just a minor nitpick, but... On Thu, Dec 18, 2014 at 04:29:08PM -0600, at...@opensource.altera.com wrote: From: Alan Tull at...@opensource.altera.com Add driver to fpga manager framework to allow configuration of FPGA in Altera SoCFPGA parts. Signed-off-by: Alan Tull

Re: [PATCH v6 4/4] staging: fpga manager: add driver for socfpga fpga manager

On Fri, Dec 19, 2014 at 03:05:50PM +0100, Michal Simek wrote: On 12/19/2014 09:55 AM, Steffen Trumtrar wrote: Hi! Just a minor nitpick, but... On Thu, Dec 18, 2014 at 04:29:08PM -0600, at...@opensource.altera.com wrote: From: Alan Tull at...@opensource.altera.com Add driver

Re: [PATCH v6 4/4] staging: fpga manager: add driver for socfpga fpga manager

On Fri, Dec 19, 2014 at 09:55:34AM -0600, atull wrote: On Fri, 19 Dec 2014, Steffen Trumtrar wrote: On Fri, Dec 19, 2014 at 03:05:50PM +0100, Michal Simek wrote: On 12/19/2014 09:55 AM, Steffen Trumtrar wrote: Hi! Just a minor nitpick, but... On Thu, Dec 18, 2014

[PATCH] drivers: kconfig: fix double include

drivers/Kconfig sources drivers/soc/Kconfig twice. Remove the last include. Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de --- drivers/Kconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/Kconfig b/drivers/Kconfig index 694d5a70d6ce..2683e633c027 100644 --- a/drivers

Re: [PATCH v4 2/6] arm: dts: socfpga: add altera fpga manager

Hi! On Tue, Dec 09, 2014 at 02:14:46PM -0600, at...@opensource.altera.com wrote: From: Alan Tull at...@opensource.altera.com Add Altera FGPA manager to device tree. Signed-off-by: Alan Tull at...@opensource.altera.com --- arch/arm/boot/dts/socfpga.dtsi | 10 ++ 1 file

Re: [PATCH v4 6/6] staging: fpga manager: add driver for altera socfpga manager

On Tue, Dec 09, 2014 at 02:14:50PM -0600, at...@opensource.altera.com wrote: From: Alan Tull at...@opensource.altera.com Add driver to fpga manager framework to allow configuration of FPGA in Altera SoC FPGA parts. Signed-off-by: Alan Tull at...@opensource.altera.com --- v2: fpga_manager

Re: [PATCH v4 2/6] arm: dts: socfpga: add altera fpga manager

On Wed, Dec 10, 2014 at 11:25:59AM -0600, atull wrote: On Wed, 10 Dec 2014, Steffen Trumtrar wrote: Hi! On Tue, Dec 09, 2014 at 02:14:46PM -0600, at...@opensource.altera.com wrote: From: Alan Tull at...@opensource.altera.com Add Altera FGPA manager to device tree. Signed

Re: [PATCH v2] ARM: socfpga: dts: Add adxl34x

{ vmmc-supply = regulator_3_3v; vqmmc-supply = regulator_3_3v; I just gave it a short spin. I get some interrupts and the position property changes, so it seems to work: Acked-by: Steffen Trumtrar s.trumt...@pengutronix.de Regards, Steffen -- Pengutronix e.K

Re: [PATCH 1/3] ARM: socfpga: dts: Fix adxl34x formating

; interrupts = 3 2; }; }; I would personally squash 3/3 into this one, but otherwise: Whole series Acked-by: Steffen Trumtrar s.trumt...@pengutronix.de Thanks, Steffen -- Pengutronix e.K. | | Industrial Linux

Re: [BUG?] crypto: caam: little/big endianness on ARM vs PPC

Hi! On Tue, Jun 16, 2015 at 03:27:54AM +, Victoria Milhoan wrote: All, Freescale has been adding i.MX6 support to the CAAM driver and testing on both i.MX6 and QorIQ platforms. The patch series is now available for review. Your feedback for the provided patches is appreciated.

[BUG?] crypto: caam: little/big endianness on ARM vs PPC

. On the other hand the sizeof(..) solution would only catch little endian on 32bit and not big endian (?!) I however don't know what combinations actually *have* to be caught, as I don't know, which exist. So, what do you think people? Thanks, Steffen Trumtrar -- Pengutronix e.K

Re: [BUG?] crypto: caam: little/big endianness on ARM vs PPC

Hi! On Mon, Jun 15, 2015 at 05:28:16PM +0100, Russell King - ARM Linux wrote: On Mon, Jun 15, 2015 at 05:59:07PM +0200, Steffen Trumtrar wrote: I'm working on CAAM support for the ARM-based i.MX6 SoCs. The current drivers/crypto/caam driver only works for PowerPC AFAIK. Actually

[PATCH] crypto: caam - fix non-64-bit write/read access

...@arm.linux.org.uk Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de --- This patch is only compile-tested for PowerPC and tested on ARM. According to the datasheets for i.MX6 and P1010 this should be correct, though. drivers/crypto/caam/regs.h | 38 +++--- 1 file

Re: [PATCH v9 3/7] staging: add bindings document for simple fpga bus

Hi! On Fri, Jul 17, 2015 at 04:22:07PM -0500, atull wrote: On Fri, 17 Jul 2015, Steffen Trumtrar wrote: Hi! On Fri, Jul 17, 2015 at 10:51:13AM -0500, at...@opensource.altera.com wrote: From: Alan Tull at...@opensource.altera.com New bindings document for simple fpga bus

Re: [PATCH v9 3/7] staging: add bindings document for simple fpga bus

Hi! On Fri, Jul 17, 2015 at 10:51:13AM -0500, at...@opensource.altera.com wrote: From: Alan Tull at...@opensource.altera.com New bindings document for simple fpga bus. Signed-off-by: Alan Tull at...@opensource.altera.com --- .../Documentation/bindings/simple-fpga-bus.txt | 61

Re: [PATCH v12 4/6] fpga: add fpga bridge framework

On Tue, Oct 27, 2015 at 05:09:13PM -0500, at...@opensource.altera.com wrote: > From: Alan Tull > > This framework adds API functions for enabling/ > disabling FPGA bridges under kernel control. > > This allows the Linux kernel to disable FPGA bridges > during FPGA

Re: [PATCH v12 6/6] ARM: socfpga: fpga bridge driver support

On Tue, Oct 27, 2015 at 05:09:15PM -0500, at...@opensource.altera.com wrote: > From: Alan Tull > > Supports Altera SOCFPGA bridges: > * fpga2sdram > * fpga2hps > * hps2fpga > * lwhps2fpga > > Allows enabling/disabling the bridges through the FPGA > Bridge

Re: [PATCH v12 2/6] fpga: add bindings document for simple fpga bus

Hi! On Tue, Oct 27, 2015 at 05:09:11PM -0500, at...@opensource.altera.com wrote: > From: Alan Tull > > New bindings document for simple fpga bus. > > Signed-off-by: Alan Tull > --- > v9: initial version added to this patchset > v10:

Re: [PATCH v12 5/6] ARM: socfpga: add bindings document for fpga bridge drivers

Hi! On Tue, Oct 27, 2015 at 05:09:14PM -0500, at...@opensource.altera.com wrote: > From: Alan Tull > > Add bindings documentation for Altera SOCFPGA bridges: > * fpga2sdram > * fpga2hps > * hps2fpga > * lwhps2fpga > > Signed-off-by: Alan Tull

Re: [PATCH v12 2/6] fpga: add bindings document for simple fpga bus

On Tue, Oct 27, 2015 at 05:09:11PM -0500, at...@opensource.altera.com wrote: > From: Alan Tull > > New bindings document for simple fpga bus. > > Signed-off-by: Alan Tull > --- > v9: initial version added to this patchset > v10:

Re: [PATCH v12 3/6] fpga: add simple-fpga-bus

On Tue, Oct 27, 2015 at 05:09:12PM -0500, at...@opensource.altera.com wrote: > From: Alan Tull > > The Simple FPGA bus uses the FPGA Manager Framework and the > FPGA Bridge Framework to provide a manufactorer-agnostic > interface for reprogramming FPGAs that is

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