On Tue, Oct 27, 2015 at 05:09:11PM -0500, at...@opensource.altera.com wrote:
> From: Alan Tull
>
> New bindings document for simple fpga bus.
>
> Signed-off-by: Alan Tull
> ---
> v9: initial version added to this patchset
> v10: s/fpga/FPGA/g
> replace DT overlay example with slightly
On Tue, Oct 27, 2015 at 05:09:12PM -0500, at...@opensource.altera.com wrote:
> From: Alan Tull
>
> The Simple FPGA bus uses the FPGA Manager Framework and the
> FPGA Bridge Framework to provide a manufactorer-agnostic
> interface for reprogramming FPGAs that is Device Tree
> Overlays-based.
>
>
On Tue, Oct 27, 2015 at 05:09:13PM -0500, at...@opensource.altera.com wrote:
> From: Alan Tull
>
> This framework adds API functions for enabling/
> disabling FPGA bridges under kernel control.
>
> This allows the Linux kernel to disable FPGA bridges
> during FPGA reprogramming and to enable
On Tue, Oct 27, 2015 at 05:09:15PM -0500, at...@opensource.altera.com wrote:
> From: Alan Tull
>
> Supports Altera SOCFPGA bridges:
> * fpga2sdram
> * fpga2hps
> * hps2fpga
> * lwhps2fpga
>
> Allows enabling/disabling the bridges through the FPGA
> Bridge Framework API functions.
>
> The
Hi Alan!
On Tue, Oct 13, 2015 at 01:28:20PM -0500, at...@opensource.altera.com wrote:
> From: Alan Tull
>
> Add FPGA manager to device tree for SoCFPGA.
>
> Signed-off-by: Alan Tull
> ---
> arch/arm/boot/dts/socfpga.dtsi | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git
On Tue, Oct 13, 2015 at 02:18:22PM -0500, Dinh Nguyen wrote:
> On Tue, 13 Oct 2015, Steffen Trumtrar wrote:
>
> > Hi Alan!
> >
> > On Tue, Oct 13, 2015 at 01:28:20PM -0500, at...@opensource.altera.com wrote:
> > > From: Alan Tull
> > >
> &g
On Tue, Oct 13, 2015 at 02:51:28PM -0500, Dinh Nguyen wrote:
> On Tue, 13 Oct 2015, at...@opensource.altera.com wrote:
>
> > From: Alan Tull
> >
> > Add FPGA manager to device tree for SoCFPGA.
> >
> > Signed-off-by: Alan Tull
> > ---
> > v2: Remove 0x after @
> > No caps in hex numbers
>
Hi!
On Tue, Oct 13, 2015 at 09:46:15PM +0200, atull wrote:
> On Tue, 13 Oct 2015, Dinh Nguyen wrote:
>
> > On Tue, 13 Oct 2015, Steffen Trumtrar wrote:
> >
> > > Hi Alan!
> > >
> > > On Tue, Oct 13, 2015 at 01:28:20PM -0500, at...@opensource.alt
Hi Tim!
On Thu, Feb 25, 2016 at 11:05:05AM +0100, Tim Sander wrote:
> From: Tim Sander
>
> Add a more specific compatible string:"terasic,de0-nano-soc" for respective
> board.
> Background: when checking for bootspec entries, some board specific fixups are
> not apropriate for board of the
On Wed, Jun 12, 2013 at 09:41:08AM -0700, Soren Brinkmann wrote:
> Add a DT fragment for the Zed Zynq platform and a corresponding
> target to the Makefile
>
> Signed-off-by: Soren Brinkmann
> ---
> I used the 'xlnx,...' compat strings since it seems this is what is
> used in the Xilinx and
On Wed, Jun 12, 2013 at 11:26:34AM -0700, Sören Brinkmann wrote:
> On Wed, Jun 12, 2013 at 08:23:45PM +0200, Steffen Trumtrar wrote:
> > On Wed, Jun 12, 2013 at 09:41:08AM -0700, Soren Brinkmann wrote:
> > > Add a DT fragment for the Zed Zynq platform and a correspo
Hi!
On Thu, Aug 22, 2013 at 05:59:36PM -0700, Sören Brinkmann wrote:
> On Thu, Aug 22, 2013 at 05:26:47PM -0700, Sören Brinkmann wrote:
> > Hi Sebastian,
> >
> > On Tue, Aug 20, 2013 at 04:04:31AM +0200, Sebastian Hesselbarth wrote:
> > > With arch/arm calling of_clk_init(NULL) from time_init(),
On Fri, Aug 23, 2013 at 07:44:03PM +0200, Sebastian Hesselbarth wrote:
> On 08/23/13 19:19, Sören Brinkmann wrote:
> >On Fri, Aug 23, 2013 at 11:30:18AM +0200, Sebastian Hesselbarth wrote:
> >>On 08/23/13 02:59, Sören Brinkmann wrote:
> >>>On Thu, Aug 22, 2013 at 05:26:47PM -0700, Sören Brinkmann
On Fri, Aug 23, 2013 at 09:00:23AM -0700, Sören Brinkmann wrote:
> Hi Steffen,
>
> On Fri, Aug 23, 2013 at 09:32:50AM +0200, Steffen Trumtrar wrote:
> > Hi!
> >
> > On Thu, Aug 22, 2013 at 05:59:36PM -0700, Sören Brinkmann wrote:
> > > On Thu, Aug 22, 2013
Hi Michal!
On Mon, Aug 26, 2013 at 01:15:11PM +0200, Michal Simek wrote:
> On 08/23/2013 09:32 AM, Steffen Trumtrar wrote:
> > Hi!
> >
> > On Thu, Aug 22, 2013 at 05:59:36PM -0700, Sören Brinkmann wrote:
> >> On Thu, Aug 22, 2013 at 05:26:47PM -0700, Sören Brink
Hi Michal,
On Mon, Aug 26, 2013 at 05:14:25PM +0200, Michal Simek wrote:
> Steffen: Can you point me to that floading patches? If they are useful
> we can try them and help with pushing them to the mainline.
> I don't think that there is any reasonable solution without using these
> patches.
>
On Mon, Aug 26, 2013 at 08:16:29AM -0700, Sören Brinkmann wrote:
> On Mon, Aug 26, 2013 at 02:53:35PM +0200, Sebastian Hesselbarth wrote:
> > On 08/26/13 14:07, Steffen Trumtrar wrote:
> > >On Mon, Aug 26, 2013 at 01:15:11PM +0200, Michal Simek wrote:
> > >>
Allow probing the dw-mmio from devicetree.
Signed-off-by: Steffen Trumtrar
---
This was tested on Socfpga and v3.14-rc6
.../devicetree/bindings/spi/spi-dw-mmio.txt| 25 ++
drivers/spi/spi-dw-mmio.c | 19 +++-
2 files changed, 43
is supported upstream. Is anybody working on that?
> >Where would such a driver fit?
>
> Adding Steffen Trumtrar, as I came across his patch:
> http://permalink.gmane.org/gmane.linux.drivers.devicetree/31370
>
> @Steffen, was there no answer to your questions about
end-email-dingu...@altera.com
Regards,
Steffen
--
Pengutronix e.K. | Steffen Trumtrar|
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
Amtsgericht Hildesheim, HRA 2686
Hi!
On Mon, Apr 07, 2014 at 11:10:12AM -0600, Jason Gunthorpe wrote:
> On Mon, Apr 07, 2014 at 02:24:07PM +0200, Michal Simek wrote:
>
> > Device-tree BSP and in 2014.01 there will be new BSP which just
> > generate them directly from the Vivado tools which just target your
> > reference design.
On Tue, Apr 08, 2014 at 11:45:25AM +0100, Mark Rutland wrote:
> On Mon, Apr 07, 2014 at 10:54:09PM +0100, ttha...@altera.com wrote:
> > From: Thor Thayer
> >
> > Added EDAC support for reporting ECC errors of CycloneV
> > and ArriaV SDRAM controller.
> > - The SDRAM Controller registers are used
Hi!
On Mon, Apr 07, 2014 at 04:54:07PM -0500, ttha...@altera.com wrote:
> From: Thor Thayer
>
> Addition of the Altera SDRAM controller bindings and device
> tree changes to the Altera SoC project.
>
> Signed-off-by: Thor Thayer
> To: Rob Herring
> To: Pawel Moll
> To: Mark Rutland
> To:
On Tue, Apr 08, 2014 at 09:29:50AM -0500, Thor Thayer wrote:
> On Tue, 2014-04-08 at 15:38 +0200, Steffen Trumtrar wrote:
> > Hi!
> >
> > On Mon, Apr 07, 2014 at 04:54:07PM -0500, ttha...@altera.com wrote:
> > > From: Thor Thayer
> > >
> > >
onvert virtioXX_to_cpu to leXX_to_cpu
- convert reserved to __u32
Signed-off-by: Willem de Bruijn
Co-developed-by: Steffen Trumtrar
Signed-off-by: Steffen Trumtrar
--
Changes to original RFCv2
- move virtio_net_hdr_v1 into hash-struct
---
drivers/net/virtio_net.c
= SOF_TIMESTAMPING_RAW_HARDWARE |
+ do_test(family, SOF_TIMESTAMPING_TX_HARDWARE);
Signed-off-by: Willem de Bruijn
Co-developed-by: Steffen Trumtrar
Signed-off-by: Steffen Trumtrar
--
Changes to original RFC v2:
- append write-able descriptor for TX timestamp
Signed-off-by: Steffen Trumtrar
---
drivers
ck and driver is future work.
Changes RFC->RFCv2
- drop unused VIRTIO_NET_HASH_STATE_TIMEOUT_BIT
- convert from cpu_to_virtioXX to cpu_to_leXX
Signed-off-by: Willem de Bruijn
Signed-off-by: Steffen Trumtrar
---
drivers/net/virtio_net.c| 26 +++---
include/uapi/linux/v
-by: Steffen Trumtrar
---
drivers/net/virtio_net.c| 13 -
include/uapi/linux/virtio_net.h | 1 +
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c
index 4065834957fbd..fb3572074e8b8 100644
--- a/drivers/net/virtio_net.c
-by: Steffen Trumtrar
---
Willem de Bruijn (4):
virtio-net: support transmit hash report
virtio-net: support receive timestamp
virtio-net: support transmit timestamp
virtio-net: support future packet transmit time
drivers/net/virtio_net.c| 211
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