From: Suzuki K. Poulose suzuki.poul...@arm.com
Avoid secure transactions while probing the CCI PMU. The
existing code makes use of the Peripheral ID2 (PID2) register
to determine the revision of the CCI400, which requires a
secure transaction. This puts a limitation on the usage of the
driver
From: Suzuki K. Poulose suzuki.poul...@arm.com
This series enables the PMU monitoring support for CCI400 on ARM64.
The existing CCI400 driver code is a mix of PMU driver and the MCPM
driver code. The MCPM driver is only used on ARM(32) and contains
arm32 assembly and hence can't be built on ARM64
On 24/02/15 21:53, Nicolas Pitre wrote:
On Tue, 24 Feb 2015, Suzuki K. Poulose wrote:
From: Suzuki K. Poulose suzuki.poul...@arm.com
Avoid secure transactions while probing the CCI PMU. The
existing code makes use of the Peripheral ID2 (PID2) register
to determine the revision of the CCI400
On 24/02/15 22:17, Nicolas Pitre wrote:
On Tue, 24 Feb 2015, Suzuki K. Poulose wrote:
From: Suzuki K. Poulose suzuki.poul...@arm.com
This patch separates the PMU driver code from the low level
CCI driver code, and enables the CCI400-PMU for ARM64.
Introduces config options for both
On 22/01/15 13:45, Johannes Weiner wrote:
On Wed, Jan 21, 2015 at 04:39:55PM +, Will Deacon wrote:
On Mon, Jan 19, 2015 at 12:51:27PM +, Suzuki K. Poulose wrote:
On 10/01/15 08:55, Vladimir Davydov wrote:
The problem is that the memory cgroup controller takes a css reference
per each
On 21/04/15 00:14, Tyler Baker wrote:
The breakpoints test should only should be executed on x86 targets, so lets
emit a skip and omit the installation when ARCH != x86.
Acked-by: Michael Ellerman m...@ellerman.id.au
Signed-off-by: Tyler Baker tyler.ba...@linaro.org
---
On 13/04/15 13:41, Will Deacon wrote:
On Thu, Apr 09, 2015 at 04:36:29PM +0100, Mark Rutland wrote:
On Thu, Apr 09, 2015 at 03:57:05PM +0100, Mark Salter wrote:
Currently in validate_group(), there is a static initializer
for fake_pmu.used_mask which is based on CPU_BITS_NONE but
the used_mask
From: Mark Salter msal...@redhat.com
Currently in validate_group(), there is a static initializer
for fake_pmu.used_mask which is based on CPU_BITS_NONE but
the used_mask array size is based on CCI_PMU_MAX_HW_EVENTS.
CCI_PMU_MAX_HW_EVENTS is not based on NR_CPUS, so CPU_BITS_NONE
is not correct
From: Suzuki K. Poulose suzuki.poul...@arm.com
This series adds the support for CCI-500 PMU, by
reusing and rearranging the CCI-400 PMU driver code.
CCI-500 (the new Cache Coherent Interconnect IP) has
a PMU with 8 independent event counters and supports
profiling events related to master/slave
From: Suzuki K. Poulose suzuki.poul...@arm.com
Each CCI model have different event/source codes and formats. This
patch exports this information via the sysfs, which includes the
aliases for the events. The aliases are listed by 'perf list', helping
the users to specify the name of the event
From: Suzuki K. Poulose suzuki.poul...@arm.com
Given that each CCI has different set of interfaces and
its associated events, it is good to abstract the validation of the
event codes to make it easier to add support for a new CCI model.
This patch also abstracts the mapping of a given event
From: Suzuki K. Poulose suzuki.poul...@arm.com
CCI-500 provides 8 event counters which can count any of the
supported events independently. The PMU event id is a 9-bit
value made of two parts.
bits [8:5] - Source port
0x0-0x6 Slave Ports
0x8
From: Suzuki K. Poulose suzuki.poul...@arm.com
Rename CCI400 specific defintions from CCI_xxx to CCI400_xxx.
Introduce generic ARM_CCI_PMU to cover common code for handling
the CCI PMU.
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Will Deacon will.dea...@arm.com
Cc: Punit Agrawal punit.agra
From: Suzuki K. Poulose suzuki.poul...@arm.com
Adds the PMU model specific counters to the PMU model
abstraction to make it easier to add a new PMU.
The patch cleans up the naming convention used all over
the code.
e.g, CCI_PMU_MAX_HW_EVENTS = maximum number of events that
can be counted at any
From: Suzuki K. Poulose suzuki.poul...@arm.com
This patch gets rid of the global struct cci_pmu variable and makes
the code use the cci_pmu explicitly. Makes code a bit more robust
and reader friendly.
Cc: Punit Agrawal punit.agra...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Will Deacon
On 15/04/15 12:58, Will Deacon wrote:
On Wed, Apr 15, 2015 at 11:44:06AM +0100, Suzuki K. Poulose wrote:
On 09/04/15 15:57, Mark Salter wrote:
Currently in validate_group(), there is a static initializer
for fake_pmu.used_mask which is based on CPU_BITS_NONE but
the used_mask array size
On 09/04/15 15:57, Mark Salter wrote:
Currently in validate_group(), there is a static initializer
for fake_pmu.used_mask which is based on CPU_BITS_NONE but
the used_mask array size is based on CCI_PMU_MAX_HW_EVENTS.
CCI_PMU_MAX_HW_EVENTS is not based on NR_CPUS, so CPU_BITS_NONE
is not correct
.
Reviewed-by: Suzuki K. Poulose suzuki.poul...@arm.com
Suzuki
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On 26/06/15 10:08, Stephen Rothwell wrote:
Hi all,
Changes since 20150625:
Dropped tree: edac-amd (rebased and merged into Linus' tree)
The arc tree gained a conflict against Linus' tree.
The vfs tree gained a conflict against the ceph tree.
The modules tree still had its build failure so I
On 26/05/15 10:53, Suzuki K. Poulose wrote:
From: Suzuki K. Poulose suzuki.poul...@arm.com
Do not enable CCI-400 PMU by default and fix the dependency on PERF_EVENTS
than HW_PERF_EVENTS.
Reported-by: Russell King rmk+ker...@arm.linux.org.uk
Cc: Will Deacon will.dea...@arm.com
Cc
Hi arm-soc folk,
On 26/05/15 10:53, Suzuki K. Poulose wrote:
From: Suzuki K. Poulose suzuki.poul...@arm.com
Here is the series which adds support for the CCI-500
PMU. Could you please apply this for 4.2 ?
Please let me know if you need a pull request, I could ask Will to
setup one.
Gentle
On 29/05/15 13:49, Arnd Bergmann wrote:
On Friday 29 May 2015 10:29:07 Suzuki K. Poulose wrote:
Hi arm-soc folk,
On 26/05/15 10:53, Suzuki K. Poulose wrote:
From: Suzuki K. Poulose suzuki.poul...@arm.com
Here is the series which adds support for the CCI-500
PMU. Could you please apply
From: Suzuki K. Poulose suzuki.poul...@arm.com
CCI-500 provides 8 event counters which can count any of the
supported events independently. The PMU event id is a 9-bit
value made of two parts.
bits [8:5] - Source port
0x0-0x6 Slave Ports
0x8
From: Suzuki K. Poulose suzuki.poul...@arm.com
This patch gets rid of the global struct cci_pmu variable and makes
the code use the cci_pmu explicitly. Makes code a bit more robust
and reader friendly.
Cc: Punit Agrawal punit.agra...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Will Deacon
From: Suzuki K. Poulose suzuki.poul...@arm.com
Given that each CCI has different set of interfaces and
its associated events, it is good to abstract the validation of the
event codes to make it easier to add support for a new CCI model.
This patch also abstracts the mapping of a given event
From: Suzuki K. Poulose suzuki.poul...@arm.com
Each CCI model have different event/source codes and formats. This
patch exports this information via the sysfs, which includes the
aliases for the events. The aliases are listed by 'perf list', helping
the users to specify the name of the event
From: Suzuki K. Poulose suzuki.poul...@arm.com
Adds the PMU model specific counters to the PMU model
abstraction to make it easier to add a new PMU.
The patch cleans up the naming convention used all over
the code.
e.g, CCI_PMU_MAX_HW_EVENTS = maximum number of events that
can be counted at any
From: Suzuki K. Poulose suzuki.poul...@arm.com
Do not enable CCI-400 PMU by default and fix the dependency on PERF_EVENTS
than HW_PERF_EVENTS.
Reported-by: Russell King rmk+ker...@arm.linux.org.uk
Cc: Will Deacon will.dea...@arm.com
Cc: a...@kernel.org
Cc: Russell King rmk+ker
From: Suzuki K. Poulose suzuki.poul...@arm.com
Hi,
Here is the series which adds support for the CCI-500
PMU. Could you please apply this for 4.2 ?
Please let me know if you need a pull request, I could ask Will to
setup one.
---
This series adds the support for CCI-500 PMU, by
reusing
From: Suzuki K. Poulose suzuki.poul...@arm.com
Rename CCI400 specific defintions from CCI_xxx to CCI400_xxx.
Introduce generic ARM_CCI_PMU to cover common code for handling
the CCI PMU.
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Will Deacon will.dea...@arm.com
Cc: Punit Agrawal punit.agra
From: Suzuki K. Poulose suzuki.poul...@arm.com
Introduce helpers for finding the number of page table
levels required for a given VA width, shift for a particular
page table level.
Convert the existing users to the new helpers. More users
to follow.
Cc: Ard Biesheuvel ard.biesheu...@linaro.org
From: Suzuki K. Poulose suzuki.poul...@arm.com
Move the kernel pagetable (both swapper and idmap) definitions
from the generic asm/page.h to a new file, asm/kernel-pgtable.h.
This is mostly a cosmetic change, to clean up the asm/page.h to
get rid of the arch specific details which are not needed
From: Suzuki K. Poulose suzuki.poul...@arm.com
At the moment, we only support maximum of 3-level page table for
swapper. With 48bit VA, 64K has only 3 levels and 4K uses section
mapping. Add support for 4-level page table for swapper, needed
by 16K pages.
Cc: Ard Biesheuvel ard.biesheu
From: Suzuki K. Poulose suzuki.poul...@arm.com
Now that we can calculate the number of levels required for
mapping a va width, reserve exact number of pages that would
be required to cover the idmap. The idmap should be able to handle
the maximum physical address size supported.
Cc: Ard
From: Suzuki K. Poulose suzuki.poul...@arm.com
We use !CONFIG_ARM64_64K_PAGES for CONFIG_ARM64_4K_PAGES
(and vice versa) in code. It all worked well, so far since
we only had two options. Now, with the introduction of 16K,
these cases will break. This patch cleans up the code to
use the required
From: Suzuki K. Poulose suzuki.poul...@arm.com
The existing fake pgd handling code assumes that the stage-2 entry
level can only be one level down that of the host, which may not be
true always(e.g, with the introduction of 16k pagesize).
e.g.
With 16k page size and 48bit VA and 40bit IPA we
From: Suzuki K. Poulose suzuki.poul...@arm.com
This series enables the 16K page size support on Linux for arm64.
This series adds support for 48bit VA(4 level), 47bit VA(3 level) and
36bit VA(2 level) with 16K. 16K was a late addition to the architecture
and is not implemented by all CPUs. Added
From: Suzuki K. Poulose suzuki.poul...@arm.com
This patch turns on the 16K page support in the kernel. We
support 48bit VA (4 level page tables) and 47bit VA (3 level
page tables).
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Will Deacon will.dea
From: Suzuki K. Poulose suzuki.poul...@arm.com
We use section maps with 4K page size to create the
swapper/idmaps. So far we have used !64K or 4K checks
to handle the case where we use the section maps. This
patch adds a symbol to make it clear those cases.
Cc: Ard Biesheuvel ard.biesheu
From: Suzuki K. Poulose suzuki.poul...@arm.com
36bit VA lets us use 2 level page tables while limiting the
available address space to 64GB.
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Will Deacon will.dea...@arm.com
Signed-off-by: Suzuki K. Poulose
From: Suzuki K. Poulose suzuki.poul...@arm.com
No functional changes. Group the common bits for VCTR_EL2
initialisation for better readability. The granule size
and the entry level are controlled by the page size.
Cc: Christoffer Dall christoffer.d...@linaro.org
Cc: Marc Zyngier marc.zyng
From: Suzuki K. Poulose suzuki.poul...@arm.com
Ensure that the selected page size is supported by the
CPU(s).
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Will Deacon will.dea...@arm.com
Signed-off-by: Suzuki K. Poulose suzuki.poul...@arm.com
---
arch
From: Suzuki K. Poulose suzuki.poul...@arm.com
Rearrange the code for fake pgd handling, which is applicable
to only ARM64. The intention is to keep the common code cleaner,
unaware of the underlying hacks.
Cc: kvm...@lists.cs.columbia.edu
Cc: christoffer.d...@linaro.org
Cc: marc.zyng...@arm.com
From: Suzuki K. Poulose suzuki.poul...@arm.com
{V}TCR_EL2_TG0 is a 2bit wide field, where:
00 - 4K
01 - 64K
10 - 16K
But we use only 1 bit, which has worked well so far since
we never cared about 16K. Fix it for 16K support.
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Will Deacon
From: Suzuki K. Poulose suzuki.poul...@arm.com
Update the help text for ARM64_64K_PAGES to reflect the reality
about AArch32 support.
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Will Deacon will.dea...@arm.com
Signed-off-by: Suzuki K. Poulose suzuki.poul
On 13/08/15 13:28, Steve Capper wrote:
On 13 August 2015 at 12:34, Suzuki K. Poulose suzuki.poul...@arm.com wrote:
From: Suzuki K. Poulose suzuki.poul...@arm.com
Ensure that the selected page size is supported by the
CPU(s).
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Catalin Marinas
From: Suzuki K. Poulose suzuki.poul...@arm.com
Fixes a build break when CONFIG_REGULATOR is not selected.
Signed-off-by: Suzuki K. Poulose suzuki.poul...@arm.com
---
include/linux/regulator/consumer.h |6 ++
1 file changed, 6 insertions(+)
diff --git a/include/linux/regulator
On 24/07/15 10:43, Suzuki K. Poulose wrote:
From: Suzuki K. Poulose suzuki.poul...@arm.com
This patch adds an infrastructure to keep track of the CPU feature
registers on the system. This patch also consolidates the cpuinfo
SANITY checks which ensures that we don't have conflicting feature
On 10/08/15 19:19, Andrew Haley wrote:
On 08/10/2015 06:36 PM, Suzuki K. Poulose wrote:
On 10/08/15 17:06, Catalin Marinas wrote:
Hi Suzuki,
On Fri, Jul 24, 2015 at 10:43:47AM +0100, Suzuki K. Poulose wrote:
From: Suzuki K. Poulose suzuki.poul...@arm.com
Documentation of the infrastructure
On 11/08/15 15:46, Catalin Marinas wrote:
On Mon, Aug 10, 2015 at 06:36:46PM +0100, Suzuki K. Poulose wrote:
On 10/08/15 17:06, Catalin Marinas wrote:
On Fri, Jul 24, 2015 at 10:43:47AM +0100, Suzuki K. Poulose wrote:
From: Suzuki K. Poulose suzuki.poul...@arm.com
Documentation
On 11/08/15 15:23, Catalin Marinas wrote:
On Mon, Aug 10, 2015 at 07:48:48PM +0200, Ard Biesheuvel wrote:
On 10/08/15 17:06, Catalin Marinas wrote:
And to debunk some of the counter arguments:
a) Running out of HWCAP bits - I really doubt this, we can always
introduce 64 more via a new
On 10/08/15 17:06, Catalin Marinas wrote:
Hi Suzuki,
On Fri, Jul 24, 2015 at 10:43:47AM +0100, Suzuki K. Poulose wrote:
From: Suzuki K. Poulose suzuki.poul...@arm.com
Documentation of the infrastructure
Signed-off-by: Suzuki K. Poulose suzuki.poul...@arm.com
The implementation looks fine
From: Suzuki K. Poulose suzuki.poul...@arm.com
This is an early RFC prototype for an API to export ARMv8 CPU
feature registers to AArch64 userspace. The series also
consolidates the CPU info, HWCAPs and the sanity check
infrastructure.
The ARM architecture exposes the system/cpu capabilities via
From: Suzuki K. Poulose suzuki.poul...@arm.com
Add a helper to extract the register field from a given
instruction.
Signed-off-by: Suzuki K. Poulose suzuki.poul...@arm.com
---
arch/arm64/include/asm/insn.h |2 ++
arch/arm64/kernel/insn.c | 29 +
2 files
From: Suzuki K. Poulose suzuki.poul...@arm.com
This patch adds an infrastructure to keep track of the CPU feature
registers on the system. This patch also consolidates the cpuinfo
SANITY checks which ensures that we don't have conflicting feature
supports across the CPUs.
Each register has a set
From: Suzuki K. Poulose suzuki.poul...@arm.com
Now that we track the system-wide safe value of a CPU feature,
make use of that whenever possible, including ELF_HWCAPS.
Cc: Marc Zyngier marc.zyng...@arm.com
Cc: Will Deacon will.dea...@arm.com
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Mark
From: Suzuki K. Poulose suzuki.poul...@arm.com
Add an API for reading a safe CPUID value across the system
Signed-off-by: Suzuki K. Poulose suzuki.poul...@arm.com
---
arch/arm64/include/asm/cpu.h |2 ++
arch/arm64/kernel/cpuinfo.c |9 +
2 files changed, 11 insertions(+)
diff
From: Suzuki K. Poulose suzuki.poul...@arm.com
Attached is a sample program that fetches all the emulated
cpu feature registers and traps on accessing an invalid
id register.
---
/*
* show_sysregs_all: Sample program to retrieve the
* CPU feature registers.
*
* Author: Suzuki K. Poulose
From: Suzuki K. Poulose suzuki.poul...@arm.com
This patch re-arranges the code a little bit to consolidate
the /proc/cpuinfo handling code to arch/arm64/kernel/cpuinfo.c.
No functional changes.
Signed-off-by: Suzuki K. Poulose suzuki.poul...@arm.com
---
arch/arm64/include/asm/cpu.h |1
From: Suzuki K. Poulose suzuki.poul...@arm.com
Delay the ELF HWCAP initialisation untill all the CPUs are up.
This is in preparation for detecting the common features across
the CPUS and creating a consistent ELF HWCAP for the system.
Signed-off-by: Suzuki K. Poulose suzuki.poul...@arm.com
From: Suzuki K. Poulose suzuki.poul...@arm.com
This patch adds the hook for emulating MRS instruction to
export the 'user visible' value of supported system registers.
We emulate only the following id space for system registers:
Op0=0, Op1=0, CRn=0.
The rest will fall back to SIGILL
From: Suzuki K. Poulose suzuki.poul...@arm.com
This patch adds the emulation for the id registers(i,e Op0=0,
Op1=0, CRn=0, CRm=0).
Expose MIDR_EL1 for the current cpu where the 'mrs' instruction
is executed. The users should be aware that, on a heterogeneous
system, there is no guarantee
From: Suzuki K. Poulose suzuki.poul...@arm.com
Documentation of the infrastructure
Signed-off-by: Suzuki K. Poulose suzuki.poul...@arm.com
---
Documentation/arm64/cpu-feature-registers.txt | 185 +
1 file changed, 185 insertions(+)
create mode 100644 Documentation
From: Suzuki K. Poulose suzuki.poul...@arm.com
At early boot, we print the CPU version/revision. On a heterogeneous
system, we could have different types of CPUs. Print the CPU info for
all active cpus.
Also, remove the redundant 'revision' information which doesn't
make any sense without
On 10/07/15 18:41, Kirill A. Shutemov wrote:
With new refcounting we don't need to mark PMDs splitting. Let's drop
code to handle this.
pmdp_splitting_flush() is not needed too: on splitting PMD we will do
pmdp_clear_flush() + set_pte_at(). pmdp_clear_flush() will do IPI as
needed for fast_gup.
.SRE before enabling
ARM64_HAS_SYSREG_GIC_CPUIF")
from the tip tree.
Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com>
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index d413959..a1aea90 100644
--- a/arch/arm64/ker
On Thu, Oct 22, 2015 at 10:00:25AM -0700, Olof Johansson wrote:
> On Tue, Oct 20, 2015 at 02:05:22PM +0100, Suzuki K. Poulose wrote:
> Hi,
>
> Given that CCI-500 is only now showing up in FPGA models, and is new hardware
> support and not a regression, combined with the late time
On 25/10/15 08:06, Siddhesh Poyarekar wrote:
On Tuesday 13 October 2015 10:52 PM, Suzuki K. Poulose wrote:
Apart from the selected feature registers, we expose MIDR_EL1 (Main
ID Register). The user should be aware that, reading MIDR_EL1 can be
tricky on a heterogeneous system (just like getcpu
-by: Suzuki K. Poulose <suzuki.poul...@arm.com>
---
drivers/gpio/gpio-tegra.c | 105 -
1 file changed, 56 insertions(+), 49 deletions(-)
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index 027e5f4..896bf29 100644
--- a/driver
On 13/10/15 09:34, Catalin Marinas wrote:
On Mon, Oct 12, 2015 at 06:52:56PM +0300, Andrey Ryabinin wrote:
Andrey Ryabinin (3):
arm64: move PGD_SIZE definition to pgalloc.h
arm64: add KASAN support
Documentation/features/KASAN: arm64 supports KASAN now
Linus Walleij (1):
ARM64:
On 16/11/15 15:34, Andrey Ryabinin wrote:
On 11/16/2015 02:16 PM, Suzuki K. Poulose wrote:
On 13/10/15 09:34, Catalin Marinas wrote:
On Mon, Oct 12, 2015 at 06:52:56PM +0300, Andrey Ryabinin wrote:
Hi,
I get the following failure with KASAN + 16K_PAGES + 48BIT_VA, with 4.4-rc1:
arch
<punit.agra...@arm.com>
Cc: Mark Rutland <mark.rutl...@arm.com>
Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com>
---
drivers/bus/arm-cci.c | 32 ++--
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/drivers/bus/arm-cci.c b/dri
]
- Address comments on v2.
- Split the introduction of write_counter hook to a separate patch
Changes since V1:
- Choose 4 instead of 3 above, suggested by Mark Rutland
[1]
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-September/373129.html
Suzuki K. Poulose (5):
arm-cci
Add support for model specific methods to write to the PMU
event counter. This will be used by CCI500/550 PMUs.
Cc: Punit Agrawal <punit.agra...@arm.com>
Cc: Mark Rutland <mark.rutl...@arm.com>
Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com>
---
drivers/bu
Adds helper routines to disable the counter controls for
all the counters on the CCI PMU and restore it back, by
preserving the original state in caller provided mask.
Cc: Punit Agrawal <punit.agra...@arm.com>
Cc: Mark Rutland <mark.rutl...@arm.com>
Signed-off-by: Suzuki K. Poulose
<punit.agra...@arm.com>
Cc: Mark Rutland <mark.rutl...@arm.com>
Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com>
---
drivers/bus/arm-cci.c | 47 +++
1 file changed, 47 insertions(+)
diff --git a/drivers/bus/arm-cci.c b/drivers/b
Add helper routines to get the counter status and the event
programmed on it.
Cc: Punit Agrawal <punit.agra...@arm.com>
Cc: Mark Rutland <mark.rutl...@arm.com>
Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com>
---
Changes since V2:
- Rename pmu_counter_get_ctrl => p
symbols to CCI5xx, including the
Kconfig symbol.
No functional changes to the PMU driver.
Cc: Punit Agrawal <punit.agra...@arm.com>
Cc: Mark Rutland <mark.rutl...@arm.com>
Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com>
---
drivers/bus/Kconfig |2 +-
drivers/bu
<punit.agra...@arm.com>
Cc: Mark Rutland <mark.rutl...@arm.com>
Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com>
---
Documentation/devicetree/bindings/arm/cci.txt |2 +
drivers/bus/Kconfig |8 +--
drivers/bus/arm-cci.c
://lists.infradead.org/pipermail/linux-arm-kernel/2015-November/385849.html
Suzuki K. Poulose (2):
arm-cci500: Rearrange PMU driver for code sharing with CCI-550 PMU
arm-cci: CoreLink CCI-550 PMU driver
Documentation/devicetree/bindings/arm/cci.txt |2 +
drivers/bus/Kconfig
On 04/11/15 18:28, Mark Rutland wrote:
On Tue, Oct 20, 2015 at 02:05:25PM +0100, Suzuki K. Poulose wrote:
Adds helper routines to manipulate the counter controls for
all the counters on the CCI PMU.
pmu_disable_counters_ctrl: Iterates over the counters,
checking the status of each counter
On 05/11/15 10:14, Suzuki K. Poulose wrote:
On 04/11/15 18:28, Mark Rutland wrote:
On Tue, Oct 20, 2015 at 02:05:25PM +0100, Suzuki K. Poulose wrote:
Adds helper routines to manipulate the counter controls for
all the counters on the CCI PMU.
+static void pmu_disable_counters_ctrl(struct
On 05/11/15 17:27, Mark Rutland wrote:
Can we not get rid of the mask entirely? The combination of used_mask
and each event's hwc->state tells us which counters are actually in use.
The problem is that neither hwc->state nor the cci_pmu->hw_events->events is
protected by pmu_lock, while
On 04/11/15 18:06, Mark Rutland wrote:
On Tue, Oct 20, 2015 at 02:05:24PM +0100, Suzuki K. Poulose wrote:
Add helper routines to get the counter status and the event
programmed on it.
+static u32 pmu_get_counter_ctrl(struct cci_pmu *cci_pmu, int idx)
+{
+ return pmu_read_register
On 04/11/15 18:01, Mark Rutland wrote:
On Tue, Oct 20, 2015 at 02:05:23PM +0100, Suzuki K. Poulose wrote:
This patch refactors the CCI PMU driver code a little bit to
make it easier share the code for enabling/disabling the CCI
PMU. This will be used by the hooks to work around the special
On 14/10/15 16:40, Jeremy Linton wrote:
On 10/14/2015 06:20 AM, Suzuki K. Poulose wrote:
diff --git a/arch/arm64/include/asm/page.h b/arch/arm64/include/asm/page.h
index da32354..736ed4c 100644
--- a/arch/arm64/include/asm/page.h
+++ b/arch/arm64/include/asm/page.h
@@ -24,6 +24,9 @@
#ifdef
On 14/10/15 15:51, Mark Rutland wrote:
+/* With 4K pages, we use section maps. */
/*
* ARM64 kernel is guaranteed to be loaded at 2M aligned
* address (as per booting requirements). Hence we can use
* section mapping with 4K (section size = 2M) and not with
* 16K(section size = 32M)
Ensure that the selected page size is supported by the CPU(s). If it doesn't
park it.
Cc: Mark Rutland <mark.rutl...@arm.com>
Cc: Catalin Marinas <catalin.mari...@arm.com>
Cc: Will Deacon <will.dea...@arm.com>
Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com>
Rev
y: Ard Biesheuvel <ard.biesheu...@linaro.org>
Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com>
Acked-by: Catalin Marinas <catalin.mari...@arm.com>
Reviewed-by: Christoffer Dall <christoffer.d...@linaro.org>
Acked-by: Mark Rutland <mark.rutl...@arm.com>
---
Do
On 16/10/15 18:06, Suzuki K. Poulose wrote:
This series enables the 16K page size support on Linux for arm64.
Please ignore this series, it contains some errors(with mail ids).
I will send an updated version later.
Sorry for the noise.
Thanks
Suzuki
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Cc: Catalin Marinas <catalin.mari...@arm.com>
Cc: Will Deacon <will.dea...@arm.com>
Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
Acked-by: Mark Rutland <mark.rutl...@arm.com>
---
arch/arm64/inclu
m.com>
Cc: Catalin Marinas <catalin.mari...@arm.com>
Cc: Will Deacon <will.dea...@arm.com>
Cc: Marc Zyngier <marc.zyng...@arm.com>
Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com>
Acked-by: Christoffer Dall <christoffer.d...@linaro.org>
Acked-by: Mark Rutland &l
alin.mari...@arm.com>
Cc: Will Deacon <will.dea...@arm.com>
Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
Tested-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
Acked-by: Mark Rutland <mark.rutl...@arm.co
utland <mark.rutl...@arm.com>
Cc: Catalin Marinas <catalin.mari...@arm.com>
Cc: Will Deacon <will.dea...@arm.com>
Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
Tested-by: Ard Biesheuvel <ard.bieshe
to prevent conflicts. e.g,
BLOCK_SHIFT => SWAPPER_BLOCK_SHIFT
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Cc: Mark Rutland <mark.rutl...@arm.com>
Cc: Catalin Marinas <catalin.mari...@arm.com>
Cc: Will Deacon <will.dea...@arm.com>
Signed-off-by: Suzuki K. Poul
From: Mark Rutland <mark.rutl...@arm.com>
Since NR_FIX_BTMAPS based on the fixed size of 256K, lets use
a formula to derive it for a given page size, rather than defining
for each page size.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Signed-off-by: Suzuki K. Poulose
that !64K => 4K (and vice versa)
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Cc: Catalin Marinas <catalin.mari...@arm.com>
Cc: Will Deacon <will.dea...@arm.com>
Acked-by: Mark Rutland <mark.rutl...@arm.com>
Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.co
Update the help text for ARM64_64K_PAGES to reflect the reality
about AArch32 support.
Cc: Catalin Marinas <catalin.mari...@arm.com>
Cc: Will Deacon <will.dea...@arm.com>
Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheu.
36bit VA lets us use 2 level page tables while limiting the
available address space to 64GB.
Cc: Mark Rutland <mark.rutl...@arm.com>
Cc: Catalin Marinas <catalin.mari...@arm.com>
Cc: Will Deacon <will.dea...@arm.com>
Cc: Steve Capper <steve.cap...@linaro.org>
Signed-o
: Add page size to the kernel image header
Mark Rutland (1):
arm64: Simplify NR_FIX_BTMAPS calculation
Suzuki K. Poulose (10):
arm64: Move swapper pagetable definitions
arm64: Handle section maps for swapper/idmap
arm64: Introduce helpers for page table levels
arm64: Calculate size
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