Re: [PATCHv3 01/11] arm64: Move swapper pagetable definitions

On 14/10/15 12:42, Mark Rutland wrote: On Wed, Oct 14, 2015 at 12:20:24PM +0100, Suzuki K. Poulose wrote: Also renames the symbols to prevent conflicts. e.g, BLOCK_SHIFT => SWAPPER_BLOCK_SHIFT This sounds sensible to be, so FWIW: Acked-by: Mark Rutland <mark.rutl...@arm.c

Re: [PATCHv3 02/11] arm64: Handle section maps for swapper/idmap

On 14/10/15 13:06, Mark Rutland wrote: On Wed, Oct 14, 2015 at 12:20:25PM +0100, Suzuki K. Poulose wrote: We use section maps with 4K page size to create the swapper/idmaps. So far we have used !64K or 4K checks to handle the case where we use the section maps. This patch adds a new symbol

[PATCHv2 2/4] arm-cci: Get the status of a counter

Add helper routines to get the counter status and the event programmed on it. Cc: Punit Agrawal <punit.agra...@arm.com> Cc: Mark Rutland <mark.rutl...@arm.com> Cc: a...@kernel.org Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- drivers/bus/arm-cci.c | 10

[PATCHv2 1/4] arm-cci: Refactor CCI PMU code

<punit.agra...@arm.com> Cc: Mark Rutland <mark.rutl...@arm.com> Cc: a...@kernel.org Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- drivers/bus/arm-cci.c | 94 + 1 file changed, 56 insertions(+), 38 deletions(-) di

[PATCHv2 4/4] arm-cci500: Work around PMU counter writes

: Punit Agrawal <punit.agra...@arm.com> Cc: Mark Rutland <mark.rutl...@arm.com> Cc: a...@kernel.org Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- drivers/bus/arm-cci.c | 54 - 1 file changed, 53 insertions(+), 1 delet

[PATCHv2 3/4] arm-cci: Add routines to enable/disable all counters

the state later using pmu_enable_counters_ctrl. Cc: Punit Agrawal <punit.agra...@arm.com> Cc: Mark Rutland <mark.rutl...@arm.com> Cc: a...@kernel.org Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- drivers/bus/arm-cci.c | 30 ++

[PATCHv2 0/4] arm-cci500: Workaround pmu_event_set_period

this patch profiling on CCI-500 is broken and should be fixed for 4.3. Changes since V1: - Choose 4 instead of 3 above, suggested by Mark Rutland Suzuki K. Poulose (4): arm-cci: Refactor CCI PMU code arm-cci: Get the status of a counter arm-cci: Add routines to enable/disable all counters

Re: [PATCH 03/15] arm64: Introduce helpers for page table levels

On 08/10/15 18:28, Catalin Marinas wrote: On Thu, Oct 08, 2015 at 06:22:34PM +0100, Suzuki K. Poulose wrote: On 08/10/15 15:45, Christoffer Dall wrote: On Wed, Oct 07, 2015 at 10:26:14AM +0100, Marc Zyngier wrote: I just had a chat with Catalin, who did shed some light on this. It all has

Re: [PATCH 13/15] arm64: kvm: Rewrite fake pgd handling

On 10/10/15 15:52, Christoffer Dall wrote: Hi Suzuki, Hi Christoffer, Thanks for being patient enough to review the code :-) without much of the comments. I now realise there needs much more documentation than what I have put in already. I am taking care of this in the next revision already.

Re: [PATCH v2 07/22] arm64: Keep track of CPU feature registers

On 08/10/15 16:03, Catalin Marinas wrote: On Thu, Oct 08, 2015 at 10:55:11AM +0100, Suzuki K. Poulose wrote: ... So we have three types of fields in these registers: a) features defined but not something we care about in Linux b) reserved fields c) features important to Linux I guess

Re: [PATCH 03/15] arm64: Introduce helpers for page table levels

On 07/10/15 09:26, Christoffer Dall wrote: Hi Suzuki, On Tue, Sep 15, 2015 at 04:41:12PM +0100, Suzuki K. Poulose wrote: From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> Introduce helpers for finding the number of page table levels required for a given VA width, shift for a

Re: [PATCH 03/15] arm64: Introduce helpers for page table levels

On 07/10/15 10:26, Marc Zyngier wrote: On 07/10/15 09:26, Christoffer Dall wrote: Hi Suzuki, On Tue, Sep 15, 2015 at 04:41:12PM +0100, Suzuki K. Poulose wrote: From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> Introduce helpers for finding the number of page table

Re: [PATCH 11/15] arm64: Cleanup VTCR_EL2 computation

On 07/10/15 11:11, Marc Zyngier wrote: On 15/09/15 16:41, Suzuki K. Poulose wrote: From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index bdf139e..699554d 100644 --- a/arch/arm64/include/asm

Re: [PATCH 13/15] arm64: kvm: Rewrite fake pgd handling

On 07/10/15 12:13, Marc Zyngier wrote: On 15/09/15 16:41, Suzuki K. Poulose wrote: From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> The existing fake pgd handling code assumes that the stage-2 entry level can only be one level down that of the host, which may not be

Re: [PATCH v2 06/22] arm64: sys_reg: Define System register encoding

On 07/10/15 17:36, Catalin Marinas wrote: On Mon, Oct 05, 2015 at 06:01:55PM +0100, Suzuki K. Poulose wrote: --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -22,11 +22,11 @@ #include -#define SCTLR_EL1_CP15BEN (0x1 << 5) -#define SCTLR_E

Re: [PATCH v2 12/22] arm64: Delay cpu feature checks

On 08/10/15 12:08, Catalin Marinas wrote: On Mon, Oct 05, 2015 at 06:02:01PM +0100, Suzuki K. Poulose wrote: + /* +* second pass allows enable() invoked on active each CPU +* to consider interacting capabilities. +*/ This comment doesn't read properly. Fixed

[PATCH v3 21/24] arm64: Add helper to decode register from instruction

Add a helper to extract the register field from a given instruction. Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/insn.h |2 ++ arch/arm64/kernel/insn.c | 29 + 2 files changed, 31 insertions(+) diff --git

[PATCH v3 18/24] arm64/debug: Make use of the system wide safe value

Use the system wide value of ID_AA64DFR0 to make safer decisions Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/hw_breakpoint.h |9 +++-- arch/arm64/kernel/debug-monitors.c |6 -- 2 files changed, 11 insertions(+), 4 deletions(-)

[PATCH v3 12/24] arm64: Cleanup mixed endian support detection

Make use of the system wide safe register to decide the support for mixed endian. Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/cpufeature.h | 12 ++-- arch/arm64/kernel/cpufeature.c | 22 -- 2 files chang

[PATCH v3 13/24] arm64: Populate cpuinfo after notify_cpu_starting

the system wide feature register status. Also delays advertising that the CPU has booted until we complete the notifiers, when we are ready to mark it online. This would avoid confusing the user if the CPU fails to boot due to a missing capability. Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.

[PATCH v3 04/24] arm64: Move cpu feature detection code

This patch moves the CPU feature detection code from arch/arm64/kernel/{setup.c to cpufeature.c} The plan is to consolidate all the CPU feature handling in cpufeature.c. Changes pr_fmt from "alternatives" to "cpu features" Signed-off-by: Suzuki K. Poulose <suzuki.pou

[PATCH v3 08/24] arm64: Handle width of a cpuid feature

Introduce a helper to extract cpuid feature for any given width. Cc: Catalin Marinas <catalin.mari...@arm.com> Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/cpufeature.h | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff

[PATCH v3 23/24] arm64: Expose feature registers by emulating MRS

HWCAP_CPUID. Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/sysreg.h |6 ++ arch/arm64/include/uapi/asm/hwcap.h |1 + arch/arm64/kernel/cpufeature.c | 106 +++ arch/arm64/kernel/cpuinfo.c |1 + 4

[PATCH v3 03/24] arm64: Delay cpuinfo_store_boot_cpu

. This patch delays the boot cpu store to smp_prepare_boot_cpu(). Also kills the setup_processor() which no longer does meaningful work. Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- arch/arm64/kernel/setup.c | 10 ++ arch/arm64/kernel/smp.c |1 + 2 files chan

[PATCH v3 01/24] arm64: Make the CPU information more clear

At early boot, we print the CPU version/revision. On a heterogeneous system, we could have different types of CPUs. Print the CPU info for all active cpus. Also, remove the redundant 'revision' information which doesn't make any sense without the 'variant' field. Signed-off-by: Suzuki K. Poulose

[PATCH v3 24/24] arm64: cpuinfo: Expose MIDR_EL1 and REVIDR_EL1 to sysfs

string is returned to userspace. Signed-off-by: Steve Capper <steve.cap...@linaro.org> Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- Changes since V2: - Fix errno for failures (Spotted-by: Russell King) - Roll back, if we encounter a missing cpu device - Retur

[PATCH v3 05/24] arm64: Move mixed endian support detection

in later patches. Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/cpu.h|2 ++ arch/arm64/include/asm/cpufeature.h |7 +++ arch/arm64/include/asm/cputype.h| 15 --- arch/arm64/include/asm/sysreg.h |3 +++ arch

[PATCH v3 07/24] arm64: Define helper for sys_reg id manipulation

Define helper macros to extract op0, op1, CRn, CRm & op2 for a given sys_reg id. Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/sysreg.h | 36 +++- 1 file changed, 27 insertions(+), 9 deletions(-) diff --git a/

[PATCH v3 09/24] arm64: Keep track of CPU feature registers

. Cc: Catalin Marinas <catalin.mari...@arm.com> Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- Changes since V2: - Rename the feature types - Use binary search for indexing the feature registers --- arch/arm64/include/asm/cpu.h|1 + arch/arm64/include/asm/

[PATCH v3 10/24] arm64: Consolidate CPU Sanity check to CPU Feature infrastructure

This patch consolidates the CPU Sanity check to the new infrastructure. Cc: Mark Rutland <mark.rutl...@arm.com> Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/cpu.h |3 +- arch/arm64/kernel/cpufeat

Re: [PATCH 13/15] arm64: kvm: Rewrite fake pgd handling

On 13/10/15 16:39, Christoffer Dall wrote: On Mon, Oct 12, 2015 at 10:55:24AM +0100, Suzuki K. Poulose wrote: On 10/10/15 15:52, Christoffer Dall wrote: Hi Suzuki, Hi Christoffer, Thanks for being patient enough to review the code :-) without much of the comments. I now realise there needs

[PATCH v3 00/24] arm64: Consolidate CPU feature handling

into the new infrastructure - Add a new HWCAP 'cpuid' to announce the ABI - Pulled in Steve's patch to expose midr/revidr via sysfs - Changes to documentation. Steve Capper (1): arm64: cpuinfo: Expose MIDR_EL1 and REVIDR_EL1 to sysfs Suzuki K. Poulose (23): arm64: Make the CPU information more

[PATCH v3 02/24] arm64: Delay ELF HWCAP initialisation until all CPUs are up

Delay the ELF HWCAP initialisation untill all the (enabled) CPUs are up, i.e, smp_cpus_done(). This is in preparation for detecting the common features across the CPUS and creating a consistent ELF HWCAP for the system. Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- arch

[PATCH v3 11/24] arm64: Read system wide CPUID value

Add an API for reading the safe CPUID value across the system from the new infrastructure. Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/cpufeature.h |2 ++ arch/arm64/kernel/cpufeature.c |9 + 2 files changed, 11 insertions(+)

[PATCH v3 19/24] arm64/kvm: Make use of the system wide safe values

Use the system wide safe value from the new API for safer decisions Cc: Marc Zyngier <marc.zyng...@arm.com> Cc: Christoffer Dall <christoffer.d...@linaro.org> Cc: kvm...@lists.cs.columbia.edu Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> Acked-by: Christoffer D

[PATCH v3 14/24] arm64: Delay cpu feature capability checks

ity is scheduled on all the CPUs (which is the only use case). If we need a different type of 'enable()' which only needs to be run once on any CPU, we should be able to handle that when needed. Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- Changes since V2: - Invok

[PATCH v3 22/24] arm64: cpufeature: Track the user visible fields

Track the user visible fields of a CPU feature register. This will be used later for exposing the value to the userspace via emulation of MRS instruction. For more information, check the documentation (patch follows). Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- arch

[PATCH v3 20/24] arm64: Documentation - Expose CPU feature registers

Documentation for the infrastructure to expose CPU feature register by emulating MRS. Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- Documentation/arm64/cpu-feature-registers.txt | 225 + 1 file changed, 225 insertions(+) create mode 100644 Documen

[PATCH v3 17/24] arm64: Move FP/ASIMD hwcap handling to common code

The FP/ASIMD is detected in fpsimd_init(), which is built-in unconditionally. Lets move the hwcap handling to the central place. Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- arch/arm64/kernel/cpufeature.c |2 ++ arch/arm64/kernel/fpsimd.c | 16 +--- 2

[PATCH v3 06/24] arm64: Move /proc/cpuinfo handling code

This patch moves the /proc/cpuinfo handling code: arch/arm64/kernel/{setup.c to cpuinfo.c} No functional changes Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- arch/arm64/kernel/cpuinfo.c | 124 +++ arch/arm64/kernel/setup.c

[PATCH v3 15/24] arm64: Make use of system wide capability checks

Now that we can reliably read the system wide safe value for a feature register, use that to compute the system capability. This patch also replaces the 'feature-register-specific' methods with a generic routine to check the capability. Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.

[PATCH v3 16/24] arm64: Cleanup HWCAP handling

Extend struct arm64_cpu_capabilities to handle the HWCAP detection and make use of the system wide value for the feature register. Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/cpufeature.h |2 + arch/arm64/include/asm/hwcap.h |8 ++ arch

Re: [PATCH v2 07/22] arm64: Keep track of CPU feature registers

On 08/10/15 10:55, Suzuki K. Poulose wrote: On 07/10/15 18:16, Catalin Marinas wrote: On Mon, Oct 05, 2015 at 06:01:56PM +0100, Suzuki K. Poulose wrote: diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 1ae8b24..d42ad90 100644 --- a/arch/arm64/kernel

Re: [PATCH v2 07/22] arm64: Keep track of CPU feature registers

On 08/10/15 16:03, Catalin Marinas wrote: On Thu, Oct 08, 2015 at 10:55:11AM +0100, Suzuki K. Poulose wrote: +#define ARM64_FTR_BITS(ftr_strict, ftr_type, ftr_shift, ftr_width, ftr_safe_val) \ You can drop "ftr_" from all the arguments, it makes the macro definition shorter.

Re: [PATCH v2 11/22] arm64: Populate cpuinfo after notify_cpu_starting

On 08/10/15 11:46, Suzuki K. Poulose wrote: On 08/10/15 11:15, Catalin Marinas wrote: On Mon, Oct 05, 2015 at 06:02:00PM +0100, Suzuki K. Poulose wrote: diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index cb3e0d8..6987de4 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64

Re: [PATCH v2 12/22] arm64: Delay cpu feature checks

/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree make.cross ARCH=arm64 Note: the linux-review/Suzuki-K-Poulose/arm64-Consolidate-CPU-feature-handling HEAD bfdef3a10032e84cc7ae186a058443219f110679 builds fine. It only

[PATCHv2] regulators: Add missing dummy definition for regulator_list_voltage

From: Suzuki K. Poulose suzuki.poul...@arm.com Fixes a build break when CONFIG_REGULATOR is not selected. e.g, on linux-next - 07102015: drivers/clk/tegra/clk-dfll.c: In function ‘find_lut_index_for_rate’: drivers/clk/tegra/clk-dfll.c:691:3: error: implicit declaration of function

Re: [PATCH] regulators: Add missing dummy definition for regulator_list_voltage

On 07/07/15 13:38, Mark Brown wrote: On Fri, Jun 26, 2015 at 12:06:50PM +0100, Suzuki K. Poulose wrote: +static inline int regulator_list_voltage(struct regulator *regulator, unsigned selector) +{ + return 0; +} I'd expect this stub to return -EINVAL since the voltage count should

[PATCH 1/5] arm64: cpufeature: Add helpers for extracting unsigned values

AKASHI Takahiro <takahiro.aka...@linaro.org> Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/cpufeature.h | 12 1 file changed, 12 insertions(+) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index

[PATCH 2/5] arm64: cpufeature: Track unsigned fields

g> Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/cpufeature.h | 10 -- arch/arm64/kernel/cpufeature.c | 37 ++- 2 files changed, 31 insertions(+), 16 deletions(-) diff --git a/arch/arm64/include/asm/cp

[PATCH 4/5] arm64: Make fail_incapable_cpu reusable

Refactors the code to get rid of the depenency on the capability for fail_incapable_cpu(), so that it can be used by other checks. Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- arch/arm64/kernel/cpufeature.c | 24 +++- 1 file changed, 15 insertions

[PATCH 5/5] arm64: Ensure the secondary CPUs have safe ASIDBits size

horribly and the usual SANITY check is not good enough to prevent the system from crashing. Prevent this by failing CPUs with ASID smaller than that of the boot CPU. Also moves the fail_incapable_cpu() out of the CONFIG_HOTPLUG_CPU. Cc: Will Deacon <will.dea...@arm.com> Signed-off-by: Suzuki K. P

[PATCH 0/5] arm64: cpufeature: Fixes for 4.4-rc1

This series contains fixes for two issues. Patches 1 - 3: Handling of unsigned feature values, issu reported by AKASHI Takahiro. Patches 4 - 5: Adds a check to make sure all the secondary CPUs have compatible ASIDBits to prevent system crashes. Suzuki K

[PATCH 3/5] arm64: debug: Treat the BRPs/WRPs as unsigned

IDAA64DFR0_EL1: BRPs and WRPs are unsigned values. Use the appropriate helpers to extract those fields. Cc: Ard Biesheuvel <ard.biesheu...@linaro.org> Reported-by: AKASHI Takahiro <takahiro.aka...@linaro.org> Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- arch

Re: [PATCH v7 0/4] KASAN for arm64

On 18/11/15 14:33, Andrey Ryabinin wrote: Is there any way to run 16K pages on emulated environment? I've tried: - ARM V8 Foundation Platformr0p0 (platform build 9.4.59) Have you tried with the following option ? -C cluster.has_16k_granule=1 Thanks Suzuki -- To unsubscribe from this

Re: [PATCH 2/2] arm64: don't load 32-bit binaries if platform has no aarch32_el0

On 01/09/15 17:04, Mark Rutland wrote: On Tue, Sep 01, 2015 at 03:41:12PM +0100, Yury Norov wrote: Kernel option COMPAT defines the ability of executing aarch32 binaries. Some platforms does not support aarch32 mode, and so cannot execute that binaries. But we cannot just disable COMPAT for

Re: [PATCH 1/3] arm64/cpufeature.h: Add macros for a cpu features testing

On 03/09/15 19:11, Alexander Kuleshov wrote: This patch provides a couple of macros for the testing of processor features (crypto and FP/SIMD) like support of SHA1, AES instructions, support for FPU and etc. There is already a couple of places in the arch/arm64/kernel where these processor

Re: [PATCH v3 2/2] arm64: don't load 32-bit binaries if platform has no aarch32_el0

On 02/09/15 16:50, Yury Norov wrote: Kernel option COMPAT defines the ability of executing aarch32 binaries. Some platforms does not support aarch32 mode, and so cannot execute that binaries. But we cannot just disable COMPAT for them because the same kernel binary may be used by multiple

Re: [RFC PATCH] arm64: cpuinfo: reduce cache contention on update_{feature}_support

On 04/09/15 17:04, Yury Norov wrote: This patch is on top of https://lkml.org/lkml/2015/9/2/413 In master, there's only a single function - update_mixed_endian_el0_support And similar function is on review mentioned above. The algorithm for them is like this: - there's system-wide

Re: [PATCH v4 2/5] irqchip, gicv3: Workaround for Cavium ThunderX erratum 23154

On 14/08/15 19:28, Robert Richter wrote: From: Robert Richter This patch implements Cavium ThunderX erratum 23154. The gicv3 of ThunderX requires a modified version for reading the IAR status to ensure data synchronization. Since this is in the fast-path and called with

Re: [PATCH v4 2/5] irqchip, gicv3: Workaround for Cavium ThunderX erratum 23154

On 07/09/15 18:15, Catalin Marinas wrote: On Mon, Sep 07, 2015 at 05:54:06PM +0100, Suzuki K. Poulose wrote: On 14/08/15 19:28, Robert Richter wrote: diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index c52f7ba205b4..4211c39b8744 100644 --- a/drivers/irqchip/irq-gic

Re: [PATCH v4 2/5] irqchip, gicv3: Workaround for Cavium ThunderX erratum 23154

On 08/09/15 10:00, Catalin Marinas wrote: On Mon, Sep 07, 2015 at 06:41:50PM +0100, Suzuki K. Poulose wrote: On 07/09/15 18:15, Catalin Marinas wrote: On Mon, Sep 07, 2015 at 05:54:06PM +0100, Suzuki K. Poulose wrote: On 14/08/15 19:28, Robert Richter wrote: +static void gicv3_enable_quirks

Re: [PATCH v4 2/5] irqchip, gicv3: Workaround for Cavium ThunderX erratum 23154

On 08/09/15 10:37, Catalin Marinas wrote: On Tue, Sep 08, 2015 at 10:09:30AM +0100, Suzuki K. Poulose wrote: On 08/09/15 10:00, Catalin Marinas wrote: On Mon, Sep 07, 2015 at 06:41:50PM +0100, Suzuki K. Poulose wrote: On 07/09/15 18:15, Catalin Marinas wrote: On Mon, Sep 07, 2015 at 05:54

Re: [PATCH 00/14] arm64: 16K translation granule support

On 02/09/15 10:55, Ard Biesheuvel wrote: On 13 August 2015 at 13:33, Suzuki K. Poulose <suzuki.poul...@arm.com> wrote: From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> Patches 1-7 cleans up the kernel page size handling code. Patches 8-11 Fixes some issues wit

Re: [PATCH 02/14] arm64: Handle section maps for swapper/idmap

On 02/09/15 10:38, Ard Biesheuvel wrote: On 13 August 2015 at 13:33, Suzuki K. Poulose <suzuki.poul...@arm.com> wrote: From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> We use section maps with 4K page size to create the swapper/idmaps. So far we have used !64K or 4K che

[PATCHv2] SUNRPC: Fix a race in xs_reset_transport

From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> Encountered the following BUG() with 4.3-rc1 on a fast model for arm64 with NFS root filesystem. [ cut here ] kernel BUG at fs/inode.c:1493! Internal error: Oops - BUG: 0 [#1] PREEMPT SMP Modules linked i

[PATCHv2] SUNRPC: Fix a race in xs_reset_transport

From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> Ignore the previous patch, which was really v1. --- Encountered the following BUG() with 4.3-rc1 on a fast model for arm64 with NFS root filesystem. [ cut here ] kernel BUG at fs/inode.c:1493! Inte

Re: [PATCH] SUNRPC: Fix a race in xs_reset_transport

On 15/09/15 19:52, Jeff Layton wrote: On Tue, 15 Sep 2015 16:49:23 +0100 "Suzuki K. Poulose" <suzuki.poul...@arm.com> wrote: From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> Encountered the following BUG() with 4.3-rc1 on a fast model for arm64 with NFS roo

[PATCH 00/22] arm64: Consolidate CPU feature handling

From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> This is an updated reincarnation of my "arm64: Expose CPU feature registers" series [1], which does much more. This series introduces a new infrastructure to keep track of the CPU feature registers on ARMv8-A for

[PATCH 01/22] arm64: Make the CPU information more clear

From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> At early boot, we print the CPU version/revision. On a heterogeneous system, we could have different types of CPUs. Print the CPU info for all active cpus. Also, remove the redundant 'revision' information which doesn't make a

[PATCH 21/22] arm64: cpuinfo: Expose MIDR_EL1 and REVIDR_EL1 to sysfs

From: Steve Capper It can be useful for JIT software to be aware of MIDR_EL1 and REVIDR_EL1 to ascertain the presence of any core errata that could affect codegen. This patch exposes these registers through sysfs: /sys/devices/system/cpu/cpu$ID/identification/midr

[PATCH 17/22] arm64/kvm: Make use of the system wide safe values

From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> Use the system wide safe value from the new API for safer decisions Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- arch/arm64/kvm/reset.c|2 +- arch/arm64/kvm/sys_regs.c | 12 ++-- 2 files

[PATCH 20/22] arm64: Expose feature registers by emulating MRS

From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> This patch adds the hook for emulating MRS instruction to export the 'user visible' value of supported system registers. We emulate only the following id space for system registers: Op0=0, Op1=0, CRn=0. The rest will fal

[PATCH 10/22] arm64: Cleanup mixed endian support detection

From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> Make use of the system wide safe register to decide the support for mixed endian. Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- arch/arm64/kernel/cpufeature.c | 32 ++

[PATCH 13/22] arm64: Make use of system wide capability checks

From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> Now that we can reliably read the system wide safe value for a feature register, use that to compute the system capability. This patch also replaces the 'feature-register-specific' methods with a generic routine to check the cap

[PATCH 11/22] arm64: Populate cpuinfo after notify_cpu_starting

From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> This patch delays populating the cpuinfo for a new (hotplugged) CPU until the notifiers have executed. This will enable us to verify if the new (hotplugged) CPU has all the capabilities which the system already has. If it d

[PATCH 04/22] arm64: Move mixed endian support detection

From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> Move the mixed endian support detection code to cpufeature.c from cpuinfo.c. This also moves the update_cpu_features() used by mixed endian detection code, which will get more functionality. Also moves the ID register fie

Re: [RFC PATCH] arm64: cpuinfo: reduce cache contention on update_{feature}_support

On 04/09/15 20:52, Yury Norov wrote: On Fri, Sep 04, 2015 at 05:40:57PM +0100, Suzuki K. Poulose wrote: On 04/09/15 17:04, Yury Norov wrote: This patch is on top of https://lkml.org/lkml/2015/9/2/413 In master, there's only a single function - update_mixed_endian_el0_support

[PATCH 15/22] arm64: Move FP/ASIMD hwcap handling to common code

From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> The FP/ASIMD is detected in fpsimd_init(), which is built-in unconditionally. Lets move the hwcap handling to the central place. Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- arch/arm64/kernel/cpufeature.c

[PATCH 14/22] arm64: Cleanup HWCAP handling

From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> Extend struct arm64_cpu_capabilities to handle the HWCAP detection and make use of the system wide value for the feature register. Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/cpufe

[PATCH 09/22] arm64: Read system wide CPUID value

From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> Add an API for reading the safe CPUID value across the system from the new infrastructure. Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/cpufeature.h |2 ++ arch/arm64/kernel/cp

[PATCH 08/22] arm64: Consolidate CPU Sanity check to CPU Feature infrastructure

From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> This patch consolidates the CPU Sanity check to the new infrastructure. Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/cpufeature.h |3 +- arch/arm64/kernel/cp

[PATCH 02/22] arm64: Delay ELF HWCAP initialisation until all CPUs are up

From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> Delay the ELF HWCAP initialisation untill all the (enabled) CPUs are up, i.e, smp_cpus_done(). This is in preparation for detecting the common features across the CPUS and creating a consistent ELF HWCAP for the system. Signed-

[PATCH 03/22] arm64: Move cpu feature detection code

From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> This patch moves the CPU feature detection code from arch/arm64/kernel/{setup.c to cpufeature.c} The plan is to consolidate all the CPU feature handling in cpufeature.c. Changes pr_fmt from "alternatives" to

[PATCH 06/22] arm64: sys_reg: Define System register encoding

From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> sys_reg defines the encoding of a system register as usable in the mrs/msr instructions. i.e, the encoding is shifted to the left by 5bits. Change it to the actual encoding of the register and use shifted encoding in the mrs_s/ms

[PATCH 05/22] arm64: Move /proc/cpuinfo handling code

From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> This patch moves the /proc/cpuinfo handling code: arch/arm64/kernel/{setup.c to cpuinfo.c} No functional changes Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- arch/arm64/k

[PATCH 12/22] arm64: Delay cpu feature checks

From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> At the moment we run through the arm64_features capability list for each CPU and set the capability if one of the CPU supports it. This could be problematic in a heterogeneous system with differing capabilities. Delay the CPU feat

[PATCH 22/22] arm64: feature registers: Documentation

From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> Documentation of the infrastructure Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- Documentation/arm64/cpu-feature-registers.txt | 209 + 1 file changed, 209 insertions(

[PATCH 07/22] arm64: Keep track of CPU feature registers

From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> This patch adds an infrastructure to keep track of the CPU feature registers on the system. For each register, the infrastructure keeps track of the system wide safe value of the feature bits. Also, tracks the which fields of a

[PATCH 19/22] arm64: cpufeature: Track the user visible fields

From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> Track the user visible fields of a CPU feature register. This will be used later for exposing the value to the userspace via emulation of MRS instruction. For more information, check the documentation (patch follows). Signed-

[PATCH 16/22] arm64/debug: Make use of the system wide safe value

From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> Use the system wide value of ID_AA64DFR0 to make safer decisions Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/hw_breakpoint.h | 14 ++ arch/arm64/kernel/debug

[PATCH 18/22] arm64: Add helper to decode register from instruction

From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> Add a helper to extract the register field from a given instruction. Signed-off-by: Suzuki K. Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/insn.h |2 ++ arch/arm64/kernel/insn.c | 29 ++

Re: [PATCH 1/3] arm64/cpufeature.h: Add macros for a cpu features testing

On 04/09/15 13:19, Alexander Kuleshov wrote: 2015-09-04 18:00 GMT+06:00 Suzuki K. Poulose <suzuki.poul...@arm.com>: There is generic CPUID feature helper queued for 4.3, which can extract the feature bits cpuid_feature_extract_field(feature, shift) You might want to use it instead.

[PATCH 05/15] arm64: Handle 4 level page table for swapper

From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> At the moment, we only support maximum of 3-level page table for swapper. With 48bit VA, 64K has only 3 levels and 4K uses section mapping. Add support for 4-level page table for swapper, needed by 16K pages. Cc: Ard Biesheu

[PATCH 09/15] arm64: Add page size to the kernel image header

From: Ard Biesheuvel This patch adds the page size to the arm64 kernel image header so that one can infer the PAGESIZE used by the kernel. This will be helpful to diagnose failures to boot the kernel with page size not supported by the CPU. Signed-off-by: Ard

[PATCH 13/15] arm64: kvm: Rewrite fake pgd handling

From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> The existing fake pgd handling code assumes that the stage-2 entry level can only be one level down that of the host, which may not be true always(e.g, with the introduction of 16k pagesize). e.g. With 16k page size and 48bit VA

[PATCH 12/15] arm: kvm: Move fake PGD handling to arch specific files

From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> Rearrange the code for fake pgd handling, which is applicable to only ARM64. The intention is to keep the common code cleaner, unaware of the underlying hacks. Cc: kvm...@lists.cs.columbia.edu Cc: christoffer.d...@linaro.o

[PATCH 06/15] arm64: Clean config usages for page size

From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> We use !CONFIG_ARM64_64K_PAGES for CONFIG_ARM64_4K_PAGES (and vice versa) in code. It all worked well, so far since we only had two options. Now, with the introduction of 16K, these cases will break. This patch cleans up

[PATCH 15/15] arm64: 36 bit VA

From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> 36bit VA lets us use 2 level page tables while limiting the available address space to 64GB. Cc: Mark Rutland <mark.rutl...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Cc: Will Deacon <will.dea...@a

[PATCH 14/15] arm64: Add 16K page size support

From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> This patch turns on the 16K page support in the kernel. We support 48bit VA (4 level page tables) and 47bit VA (3 level page tables). Cc: Mark Rutland <mark.rutl...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com&g

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