Will, Stephen
On 07/12/2018 12:16, Will Deacon wrote:
On Fri, Dec 07, 2018 at 09:18:47AM +1100, Stephen Rothwell wrote:
Hi all,
Today's linux-next merge of the arm64 tree got a conflict in:
arch/arm64/kernel/cpu_errata.c
between commit:
ce8c80c536da ("arm64: Add workaround for Cortex-
make
the handling better.
- Make the WARNINGs meaningful on duplicate entries
- Added tags from Vladimir
Suzuki K Poulose (7):
arm64: capabilities: Merge entries for ARM64_WORKAROUND_CLEAN_CACHE
arm64: capabilities: Merge duplicate Cavium erratum entries
arm64: capabilities: Merge duplicate e
Make use of the sorted capability list to access the capability
entry in this_cpu_has_cap() to avoid iterating over the two
tables.
Reviewed-by: Vladimiri Murzin
Tested-by: Vladimiri Murzin
Signed-off-by: Suzuki K Poulose
---
arch/arm64/kernel/cpufeature.c | 31
Merge duplicate entries for a single capability using the midr
range list for Cavium errata 30115 and 27456.
Cc: Andrew Pinski
Cc: David Daney
Cc: Will Deacon
Cc: Catalin Marinas
Reviewed-by: Vladimiri Murzin
Tested-by: Vladimiri Murzin
Signed-off-by: Suzuki K Poulose
---
arch/arm64
Remove duplicate entries for Qualcomm erratum 1003. Since the entries
are not purely based on generic MIDR checks, use the multi_cap_entry
type to merge the entries.
Cc: Christopher Covington
Cc: Will Deacon
Reviewed-by: Vladimiri Murzin
Tested-by: Vladimiri Murzin
Signed-off-by: Suzuki K
Use the sorted list of capability entries for the detection and
verification.
Reviewed-by: Vladimiri Murzin
Tested-by: Vladimiri Murzin
Signed-off-by: Suzuki K Poulose
---
arch/arm64/kernel/cpufeature.c | 42 +-
1 file changed, 17 insertions(+), 25
control the "capability" entry to make it easier
to handle combinations of the CONFIGs.
Cc: Will Deacon
Cc: Andre Przywara
Cc: Mark Rutland
Signed-off-by: Suzuki K Poulose
---
arch/arm64/Kconfig | 7 +++
arch/arm64/include/asm/cputype.h | 1 +
arch/arm64/kernel/cp
_errata table.
Reviewed-by: Vladimiri Murzin
Tested-by: Vladimiri Murzin
Signed-off-by: Suzuki K Poulose
---
arch/arm64/kernel/cpufeature.c | 32 ++--
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/
We use a stop_machine call for each available capability to
enable it on all the CPUs available at boot time. Instead
we could batch the cpu_enable callbacks to a single stop_machine()
call to save us some time.
Reviewed-by: Vladimiri Murzin
Tested-by: Vladimiri Murzin
Signed-off-by: Suzuki K
On 11/09/2018 05:59 PM, Mathieu Poirier wrote:
On Thu, 8 Nov 2018 at 10:13, Suzuki K Poulose wrote:
Hi,
On 07/11/2018 23:08, Mathieu Poirier wrote:
This patch moves access to the CLAIM tag so that no modification to the HW
happens before and after the CLAIM operation has been carried
Hi Mark,
On 29/06/18 14:40, Mark Rutland wrote:
On Tue, Jun 19, 2018 at 11:15:39AM +0100, Suzuki K Poulose wrote:
The armpmu uses get_event_idx callback to allocate an event
counter for a given event, which marks the selected counter
as "used". Now, when we delete the counter, t
On 29/06/18 15:01, Mark Rutland wrote:
On Tue, Jun 19, 2018 at 11:15:42AM +0100, Suzuki K Poulose wrote:
Add support for 64bit event by using chained event counters
and 64bit cycle counters.
PMUv3 allows chaining a pair of adjacent 32-bit counters, effectively
forming a 64-bit counter. The low
d() => armpmu_event_max_period()
- For 64bit CPU cycles events, allow chaining if cycle counter is
not available.
Suzuki K Poulose (7):
arm_pmu: Clean up maximum period handling
arm_pmu: Change API to support 64bit counter values
arm_pmu: Add support for 64bit ev
, disable
the PMU while we process the counter overflows and enable it
right back when we are done.
This patch also moves the PMU stop/start routines to avoid a
forward declaration.
Suggested-by: Mark Rutland
Cc: Will Deacon
Acked-by: Mark Rutland
Signed-off-by: Suzuki K Poulose
---
arch/arm64
: Suzuki K Poulose
---
No changes since v2
---
arch/arm/kernel/perf_event_v6.c | 2 --
arch/arm/kernel/perf_event_v7.c | 1 -
arch/arm/kernel/perf_event_xscale.c | 2 --
arch/arm64/kernel/perf_event.c | 1 -
drivers/perf/arm_pmu.c | 16
include/linux
event is removed from the PMU, reset the hw.idx
to indicate that a counter is not allocated for this event,
to help the backends do better checks. This will be also used
for the chain counter support.
Cc: Mark Rutland
Cc: Will Deacon
Reviewed-by: Julien Thierry
Signed-off-by: Suzuki K Poulose
the CHAIN event, taken when the low/even counter overflows.
For CPU cycles, when 64bit mode is requested, the cycle counter
is used in 64bit mode. If the cycle counter is not available,
falls back to chaining.
Cc: Mark Rutland
Cc: Will Deacon
Signed-off-by: Suzuki K Poulose
---
Changes since v3
armv8pmu_select_counter always returns the passed idx. So
let us make that void and get rid of the pointless checks.
Suggested-by: Mark Rutland
Cc: Will Deacon
Acked-by: Mark Rutland
Signed-off-by: Suzuki K Poulose
---
arch/arm64/kernel/perf_event.c | 29 +++--
1 file
a 64bit counter.
Add support for tracking the events that uses 64bit counters.
This only affects the periods set for each counter in the core
driver.
Cc: Will Deacon
Reviewed-by: Julien Thierry
Acked-by: Mark Rutland
Signed-off-by: Suzuki K Poulose
---
Changes since v3:
- Replace ternary
Signed-off-by: Suzuki K Poulose
---
- No changes since v2
---
arch/arm/kernel/perf_event_v6.c | 4 ++--
arch/arm/kernel/perf_event_v7.c | 4 ++--
arch/arm/kernel/perf_event_xscale.c | 8
arch/arm64/kernel/perf_event.c | 9 -
include/linux/perf/arm_pmu.h| 4
Hi Tony,
On 07/03/2018 08:09 AM, Tony Lindgren wrote:
* Suzuki K Poulose [180605 14:48]:
Switch to the new coresight bindings for hardware ports
So is this patch safe for me to pick separately for v4.19?
No. Please ignore this for now. The bindings are still under
discussion. Sorry for
Hi Rob,
On 14/06/18 14:59, Rob Herring wrote:
On Thu, Jun 14, 2018 at 2:53 AM, Suzuki K Poulose
wrote:
On 13/06/18 22:07, Matt Sealey wrote:
-Original Message-
From: Mathieu Poirier
So, if the suggestion is to use an existing property "unit", I am fine
with it, if pe
On 03/07/18 14:00, Mark Rutland wrote:
On Mon, Jul 02, 2018 at 10:59:48PM +0100, Suzuki K Poulose wrote:
Add support for 64bit event by using chained event counters
and 64bit cycle counters.
PMUv3 allows chaining a pair of adjacent 32-bit counters, effectively
forming a 64-bit counter. The low
On 03/07/18 13:49, Mark Rutland wrote:
On Mon, Jul 02, 2018 at 10:59:45PM +0100, Suzuki K Poulose wrote:
The armpmu uses get_event_idx callback to allocate an event
counter for a given event, which marks the selected counter
as "used". Now, when we delete the counter, the arm_pmu goes
: Suzuki K Poulose
---
No changes since v2
---
arch/arm/kernel/perf_event_v6.c | 2 --
arch/arm/kernel/perf_event_v7.c | 1 -
arch/arm/kernel/perf_event_xscale.c | 2 --
arch/arm64/kernel/perf_event.c | 1 -
drivers/perf/arm_pmu.c | 16
include/linux
a 64bit counter.
Add support for tracking the events that uses 64bit counters.
This only affects the periods set for each counter in the core
driver.
Cc: Will Deacon
Reviewed-by: Julien Thierry
Acked-by: Mark Rutland
Signed-off-by: Suzuki K Poulose
---
Changes since v3:
- Replace ternary
event is removed from the PMU, reset the hw.idx
to indicate that a counter is not allocated for this event,
to help the backends do better checks. This will be also used
for the chain counter support.
Cc: Will Deacon
Cc: Mark Rutland
Reviewed-by: Julien Thierry
Signed-off-by: Suzuki K Poulose
armv8pmu_select_counter always returns the passed idx. So
let us make that void and get rid of the pointless checks.
Suggested-by: Mark Rutland
Cc: Will Deacon
Acked-by: Mark Rutland
Signed-off-by: Suzuki K Poulose
---
arch/arm64/kernel/perf_event.c | 29 +++--
1 file
Signed-off-by: Suzuki K Poulose
---
- No changes since v2
---
arch/arm/kernel/perf_event_v6.c | 4 ++--
arch/arm/kernel/perf_event_v7.c | 4 ++--
arch/arm/kernel/perf_event_xscale.c | 8
arch/arm64/kernel/perf_event.c | 9 -
include/linux/perf/arm_pmu.h| 4
the CHAIN event, taken when the low/even counter overflows.
For CPU cycles, when 64bit mode is requested, the cycle counter
is used in 64bit mode. If the cycle counter is not available,
falls back to chaining.
Cc: Mark Rutland
Cc: Will Deacon
Signed-off-by: Suzuki K Poulose
---
Changes since v4
, disable
the PMU while we process the counter overflows and enable it
right back when we are done.
This patch also moves the PMU stop/start routines to avoid a
forward declaration.
Suggested-by: Mark Rutland
Cc: Will Deacon
Acked-by: Mark Rutland
Signed-off-by: Suzuki K Poulose
---
arch/arm64
n't use "64bit"
and I am open for suggestion on a better name)
- Rename armpmu_get_event_max_period() => armpmu_event_max_period()
- For 64bit CPU cycles events, allow chaining if cycle counter is
not available.
Suzuki K Poulose (7):
arm_pmu: Clean up maximum period handlin
On 07/10/2018 03:31 PM, Will Deacon wrote:
Hi Suzuki,
On Tue, Jul 10, 2018 at 09:57:57AM +0100, Suzuki K Poulose wrote:
This series adds support for counting PMU events using 64bit counters
for arm64 PMU.
The Arm v8 PMUv3 supports combining two adjacent 32bit counters
(low even and hig odd
, let's share them across the different pagesizes.
Signed-off-by: Punit Agrawal
Cc: Christoffer Dall
Cc: Marc Zyngier
---
virt/kvm/arm/mmu.c | 67 ++
1 file changed, 38 insertions(+), 29 deletions(-)
Reviewed-by: Suzuki K Poulose
On 26/06/18 10:30, Linus Walleij wrote:
On Tue, Jun 5, 2018 at 11:45 PM Suzuki K Poulose wrote:
Switch to the new coresight bindings
Cc: Linus Walleij
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
I think I was requested in another mail to hold back applying this
patch until it&#
Hi Jun
On 25/06/18 12:39, Jun Yao wrote:
When CONFIG_ARM64_VA_BITS_36/CONFIG_ARM64_VA_BITS_39/
CONFIG_ARM64_VA_BITS_42 are selected, a block-mapping can be
written to swapper_pg_dir. To defend 'KSMA', we move swapper_pg_dir
to .rodata section when these configurations are selected. At the
same t
Clean up our struct a little bit by using a union instead of
a struct for tracking the subtype of a device.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
include/linux/coresight.h | 21 -
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/include/linux
to
indicate the end of the table chain.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-catu.c | 251 +++
1 file changed, 251 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-catu.c
b/drivers/hwtracing/coresi
i.e, TMC-ETR:output_port0 -> CATU:input_port0
Reference manual for CATU component is avilable in version r2p0 of :
"Arm Coresight System-on-Chip SoC-600 Technical Reference Manual".
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/Kconfig
Signed-off-by: Suzuki K Poulose
---
.../devicetree/bindings/arm/coresight.txt | 53 ++
1 file changed, 53 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/coresight.txt
b/Documentation/devicetree/bindings/arm/coresight.txt
index 9aa30a1..5d1ad09 100644
Now that we can use a CATU with a scatter gather table, add support
for the TMC ETR to make use of the connected CATU in translate mode.
This is done by adding CATU as new buffer mode.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-catu.c| 122
thieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight.c | 43 +++--
include/linux/coresight.h | 24 ++
2 files changed, 65 insertions(+), 2 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresig
device_release().
[0] - TMC ETR perf support
- http://lists.infradead.org/pipermail/linux-arm-kernel/2018-May/574875.html
Suzuki K Poulose (6):
coresight: Cleanup device subtype struct
coresight: Add helper device type
coresight: Introduce support for Coresight Address Translation Unit
, rather than silently breaking
the devices.
Cc: "Michael S. Tsirkin"
Cc: Jason Wang
Cc: Marc Zyngier
Cc: Christoffer Dall
Cc: Peter Maydel
Cc: Jean-Philippe Brucker
Signed-off-by: Suzuki K Poulose
---
Changes since v2:
- Change errno to -E2BIG
---
drivers/virtio/virtio_pci_leg
o PFN check patches and address comments.
Kristina Martsenko (1):
vgic: Add support for 52bit guest physical address
Suzuki K Poulose (19):
virtio: mmio-v1: Validate queue PFN
virtio: pci-legacy: Validate queue pfn
arm64: Add a helper for PARange to physical shift conversion
kvm: arm64: Cle
no easy way to solve it
other than
1) Allow late modifications to CPU hwcaps
OR
2) Penalise the fastpath to always check per-cpu setting.
Regardless,
Reviewed-by: Suzuki K Poulose
On 24/05/18 12:39, Will Deacon wrote:
On Thu, May 24, 2018 at 10:58:43AM +0100, Suzuki K Poulose wrote:
On 22/05/18 16:06, Marc Zyngier wrote:
As for Spectre variant-2, we rely on SMCCC 1.1 to provide the
discovery mechanism for detecting the SSBD mitigation.
A new capability is also
BOOT_SCOPE feature early in boot]
Signed-off-by: Julien Thierry
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Christoffer Dall
Cc: Suzuki K Poulose
---
arch/arm64/include/asm/alternative.h | 3 +--
arch/arm64/include/asm/cpufeature.h | 2 ++
arch/arm64/kernel/alternative.c | 30
On 25/05/18 10:49, Julien Thierry wrote:
Add a cpufeature indicating whether a cpu supports masking interrupts
by priority.
How is this different from the SYSREG_GIC_CPUIF cap ? Is it just
the description ?
Suzuki
On 25/05/18 11:17, Julien Thierry wrote:
On 25/05/18 11:04, Suzuki K Poulose wrote:
On 25/05/18 10:49, Julien Thierry wrote:
Add a cpufeature indicating whether a cpu supports masking interrupts
by priority.
How is this different from the SYSREG_GIC_CPUIF cap ? Is it just
the description
On 25/05/18 11:39, Julien Thierry wrote:
On 25/05/18 11:36, Suzuki K Poulose wrote:
On 25/05/18 11:17, Julien Thierry wrote:
On 25/05/18 11:04, Suzuki K Poulose wrote:
On 25/05/18 10:49, Julien Thierry wrote:
Add a cpufeature indicating whether a cpu supports masking interrupts
by
On 23/05/18 21:25, Mathieu Poirier wrote:
On Fri, May 18, 2018 at 05:39:24PM +0100, Suzuki K Poulose wrote:
This patch introduces a generic sg table data structure and
associated operations. An SG table can be used to map a set
of Data pages where the trace data could be stored by the TMC
ETR
On 25/05/18 17:43, Mathieu Poirier wrote:
On Fri, May 25, 2018 at 05:07:07PM +0100, Suzuki K Poulose wrote:
On 23/05/18 21:25, Mathieu Poirier wrote:
On Fri, May 18, 2018 at 05:39:24PM +0100, Suzuki K Poulose wrote:
This patch introduces a generic sg table data structure and
associated
On 18/05/18 02:20, Kim Phillips wrote:
Allow to build coresight as modules. This greatly enhances developer
efficiency by allowing the development to take place exclusively on the
target, and without needing to reboot in between changes.
- Kconfig bools become tristates, to allow =m
- use -obj
: Mark Rutland
Cc: Will Deacon
Signed-off-by: Suzuki K Poulose
---
Note: The upstream commit is on top of a reworked capability
infrastructure for arm64 heterogeneous systems, which allows
delaying the CPU model checks. This backport is based on the
original version of the patch [0], which checks
Marc
Thanks for looping me in. Comments below.
On 03/05/18 03:02, Jia He wrote:
Hi Marc
Thanks for the review
On 5/2/2018 10:26 PM, Marc Zyngier Wrote:
[+ Suzuki]
On 02/05/18 08:08, Jia He wrote:
From: Jia He
In our armv8a server (QDF2400), I noticed a WARN_ON as follows:
[ 800.20285
: Mark Rutland
Cc: Will Deacon
Signed-off-by: Suzuki K Poulose
---
Note: The upstream commit is on top of a reworked capability
infrastructure for arm64 heterogeneous systems, which allows
delaying the CPU model checks. This backport is based on the
original version of the patch [0], which checks
On 11/05/18 16:47, Greg KH wrote:
On Fri, May 11, 2018 at 02:51:15PM +0100, Suzuki K Poulose wrote:
commit ece1397cbc89c51914fae1aec729539cfd8bd62b upstream
Some variants of the Arm Cortex-55 cores (r0p0, r0p1, r1p0) suffer
from an erratum 1024718, which causes incorrect updates when DBM/AP
On 08/05/18 20:42, Mathieu Poirier wrote:
On Tue, May 01, 2018 at 10:10:56AM +0100, Suzuki K Poulose wrote:
Right now we issue an update_buffer() and reset_buffer() call backs
in succession when we stop tracing an event. The update_buffer is
supposed to check the status of the buffer and make
On 10/05/18 02:26, Jia He wrote:
Hi Andrew
On 5/10/2018 7:31 AM, Andrew Morton Wrote:
On Fri, 4 May 2018 11:11:46 +0800 Jia He wrote:
In our armv8a server(QDF2400), I noticed lots of WARN_ON caused by PAGE_SIZE
unaligned for rmap_item->address under memory pressure tests(start 20 guests
an
On 10/05/18 00:31, Andrew Morton wrote:
On Fri, 4 May 2018 11:11:46 +0800 Jia He wrote:
In our armv8a server(QDF2400), I noticed lots of WARN_ON caused by PAGE_SIZE
unaligned for rmap_item->address under memory pressure tests(start 20 guests
and run memhog in the host).
...
In rmap_walk_ksm
On 14/05/18 03:30, Jia He wrote:
On 5/11/2018 9:39 PM, Suzuki K Poulose Wrote:
Marc
Thanks for looping me in. Comments below.
On 03/05/18 03:02, Jia He wrote:
Hi Marc
Thanks for the review
On 5/2/2018 10:26 PM, Marc Zyngier Wrote:
[+ Suzuki]
On 02/05/18 08:08, Jia He wrote:
From
: Mark Rutland
Cc: Will Deacon
Signed-off-by: Suzuki K Poulose
---
Note: The upstream commit is on top of a reworked capability
infrastructure for arm64 heterogeneous systems, which allows
delaying the CPU model checks. This backport is based on the
original version of the patch [0], which checks
-by: Ard Biesheuvel
Signed-off-by: Will Deacon
Signed-off-by: Suzuki K Poulose
---
Cherry picked for backport of
"commit ece1397cbc89c51914fae1aec729539cfd8bd62b upstream"
---
arch/arm64/include/asm/assembler.h | 20
1 file changed, 20 insertions(+)
diff --
thieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight.c | 43 +++--
include/linux/coresight.h | 24 ++
2 files changed, 65 insertions(+), 2 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresig
Now that we can use a CATU with a scatter gather table, add support
for the TMC ETR to make use of the connected CATU in translate mode.
This is done by adding CATU as new buffer mode.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-catu.c| 122
, TMC-ETR:output_port0 -> CATU:input_port0
Reference manual for CATU component is avilable in version r2p0 of :
"Arm Coresight System-on-Chip SoC-600 Technical Reference Manual".
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/Kconfig
Clean up our struct a little bit by using a union instead of
a struct for tracking the subtype of a device.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
include/linux/coresight.h | 21 -
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/include/linux
-by: Suzuki K Poulose
---
.../devicetree/bindings/arm/coresight.txt | 53 ++
1 file changed, 53 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/coresight.txt
b/Documentation/devicetree/bindings/arm/coresight.txt
index 9aa30a1..5d1ad09 100644
--- a
org/pipermail/linux-arm-kernel/2018-May/574875.html
Suzuki K Poulose (6):
coresight: Cleanup device subtype struct
coresight: Add helper device type
coresight: Introduce support for Coresight Address Translation Unit
dts: bindings: Document device tree binding for CATU
coresight: catu
to
indicate the end of the table chain.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-catu.c | 249 +++
1 file changed, 249 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-catu.c
b/drivers/hwtracing/coresi
a 64bit counter.
Add support for tracking the events that uses 64bit counters.
This only affects the periods set for each counter in the core
driver.
Cc: Mark Rutland
Cc: Will Deacon
Reviewed-by: Julien Thierry
Signed-off-by: Suzuki K Poulose
---
Changes since v2:
- None
---
drivers/perf
K Poulose
---
No changes since v2
---
arch/arm/kernel/perf_event_v6.c | 2 --
arch/arm/kernel/perf_event_v7.c | 1 -
arch/arm/kernel/perf_event_xscale.c | 2 --
arch/arm64/kernel/perf_event.c | 1 -
drivers/perf/arm_pmu.c | 16
include/linux/perf
viewed-by: Julien Thierry
Signed-off-by: Suzuki K Poulose
---
Changes since v2:
- Reset the event counter after an event is removed.
---
arch/arm/kernel/perf_event_v7.c | 2 ++
drivers/perf/arm_pmu.c | 17 +
2 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/ar
armv8pmu_select_counter always returns the passed idx. So
let us make that void and get rid of the pointless checks.
Suggested-by: Mark Rutland
Cc: Will Deacon
Signed-off-by: Suzuki K Poulose
---
arch/arm64/kernel/perf_event.c | 29 +++--
1 file changed, 19 insertions
, disable
the PMU while we process the counter overflows and enable it
right back when we are done.
This patch also moves the PMU stop/start routines to avoid a
forward declaration.
Suggested-by: Mark Rutland
Cc: Will Deacon
Signed-off-by: Suzuki K Poulose
---
arch/arm64/kernel/perf_event.c
the CHAIN event, taken when the low/even counter overflows.
For CPU cycles, when 64bit mode is requested, the cycle counter
is used in 64bit mode. If the cycle counter is not available,
falls back to chaining.
Cc: Mark Rutland
Cc: Will Deacon
Signed-off-by: Suzuki K Poulose
---
Changes sinec v2
n't use "64bit"
and I am open for suggestion on a better name)
- Rename armpmu_get_event_max_period() => armpmu_event_max_period()
- For 64bit CPU cycles events, allow chaining if cycle counter is
not available.
Suzuki K Poulose (7):
arm_pmu: Clean up maximum period handling
Convert the {read/write}_counter APIs to handle 64bit values
to enable supporting chained event counters.
Cc: Mark Rutland
Cc: Will Deacon
Reviewed-by: Julien Thierry
Signed-off-by: Suzuki K Poulose
---
- No changes since v2
---
arch/arm/kernel/perf_event_v6.c | 4 ++--
arch/arm/kernel
On 19/06/18 22:24, Alexandre Belloni wrote:
On 05/06/2018 22:43:29+0100, Suzuki K Poulose wrote:
Switch to the new coresight bindings for hardware ports
Cc: Nicolas Ferre
Cc: Alexandre Belloni
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
arch/arm/boot/dts/sama5d2.dtsi | 5
On 05/06/18 22:43, Suzuki K Poulose wrote:
Coresight uses DT graph bindings to describe the connections of the
components. However we have some undocumented usage of the bindings
to describe some of the properties of the connections.
The coresight driver needs to know the hardware ports
On 31/05/18 16:36, Mathieu Poirier wrote:
On 29 May 2018 at 07:15, Suzuki K Poulose wrote:
Suzuki K Poulose (12):
coresight: ETM: Add support for Arm Cortex-A73 and Cortex-A35
coresight: tmc: Hide trace buffer handling for file read
coresight: tmc-etr: Do not clean trace buffer
We request for "CORESIGHT_BARRIER_PKT_SIZE" length and we should
be happy when we get that size.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
Mathieu,
Please could you pull this patch, if you are happy with it ?
This fixes a problem in the ETR buf series, which I just
not
Switch to updated coresight bindings for hw ports.
Cc: Sudeep Holla
Cc: Liviu Dudau
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
arch/arm64/boot/dts/arm/juno-base.dtsi | 82 +-
arch/arm64/boot/dts/arm/juno.dts | 5 ++-
2 files changed, 63
reusing the platform description. The series also includes the
changes for Juno platform as an example. If there are no objections
to the approach, I could post the series, converting all the
in-kernel DTS to the new binding.
Suzuki K Poulose (8):
dts: binding: coresight: Document graph bindings
ber
as the port number. Let us fix it and optimise a bit as:
remote_ep = of_graph_get_remote_endpoint(ep);
if (remote_ep)
remote_parent = of_graph_get_port_parent(remote_ep);
and then, parse the remote_ep for the port/endpoint details.
Cc: Mathieu Poirier
Signed-off-by: Suzuki
Nobody uses the "clk" field in struct coresight_platform_data.
Remove it.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
include/linux/coresight.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index d950dad..32aa
oint must define the following property.
- "direction" : 0 => Port is input
1 => Port is output
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/of_coresight.c | 20
1 file changed, 16 insertions(+), 4 deletion
Before we updat the bindings, document the current graph bindings
and usage of additional properties.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
.../devicetree/bindings/arm/coresight.txt | 28 ++
1 file changed, 24 insertions(+), 4 deletions(-)
diff
If we fail to find the input / output port for a LINK component
while enabling a path, we should fail gracefully rather than
assuming port "0".
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight.c | 7 +--
1 file changed, 5 insert
eu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight.c| 21 +---
drivers/hwtracing/coresight/of_coresight.c | 40 +++---
include/linux/coresight.h | 9 ++-
3 files changed, 17 insertions(+), 53 deletions(-)
di
possible to use the port address
field for the hardware port number. Hence, we add an explicit
property to denote the hardware port number, "coresight,hwid"
which must be specified for each "endpoint".
Cc: Mathieu Poirier
Cc: Sudeep Holla
Cc: Rob Herring
Signed-off-b
hing if there is no minline
size mismatch. This series fixes this issue by splitting the
checks to :
1) Mismatch on D/I minline sizes
2) Everything "strict" except (1).
Applies on 4.18-rc2
Suzuki K Poulose (2):
arm64: Fix mismatched cache line size detection
arm64: Handle mismatched ca
Signed-off-by: Suzuki K Poulose
---
arch/arm64/include/asm/cache.h | 4
arch/arm64/kernel/cpu_errata.c | 6 --
arch/arm64/kernel/cpufeature.c | 2 +-
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h
index
Track mismatches in the cache type register (CTR_EL0), other
than the D/I min line sizes and trap user accesses if there are any.
Cc: Mark Rutland
Cc: Will Deacon
Cc: Catalin Marinas
Signed-off-by: Suzuki K Poulose
---
arch/arm64/include/asm/cpucaps.h | 3 ++-
arch/arm64/kernel/cpu_errata.c
le thread stack, but a set of temporary page tables.
*/
-asmlinkage void secondary_start_kernel(void)
+notrace asmlinkage void secondary_start_kernel(void)
{
u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
struct mm_struct *mm = &init_mm;
Tested-by: Suzuki K Poulo
On 08/06/18 22:52, Mathieu Poirier wrote:
On 8 June 2018 at 15:49, Mathieu Poirier wrote:
On Tue, Jun 05, 2018 at 10:43:21PM +0100, Suzuki K Poulose wrote:
Switch to updated coresight bindings for hw ports.
Cc: Sudeep Holla
Cc: Liviu Dudau
Cc: Mathieu Poirier
Signed-off-by: Suzuki K
Hi Rob,
On 12/06/18 21:48, Rob Herring wrote:
On Fri, Jun 01, 2018 at 02:16:05PM +0100, Suzuki K Poulose wrote:
The coresight drivers relied on default bindings for graph
in DT, while reusing the "reg" field of the "ports" to indicate
the actual hardware port number
to sinks).
Coming back to your suggestion of "unit", what does it imply ?
Its too generic a term for something as concrete as a port number.
Cheers
Suzuki
Ta,
Matt
Sent from my iPhone
On Jun 13, 2018, at 04:45, Suzuki K Poulose wrote:
Hi Rob,
On 12/06/18 21:48, Rob Herring wro
Hi Matt,
On 13/06/18 16:47, Matt Sealey wrote:
Hi Suzuki,
Why not use “unit”?
I believe we had this discussion years ago about numbering serial ports
and sdhci (i.e. how do you know it’s UART0 or UART1 from just the address?
Some SoC’s don’t address sequentially *or* in a forward direction) -
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