From: Thor Thayer
Add qspi_clock
The qspi_clk frequency is updated by U-Boot before starting Linux.
Add QSPI interface node.
Add QSPI flash memory child node.
Setup the QSPI memory in 2 partitions.
Signed-off-by: Thor Thayer
---
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 22
From: Thor Thayer
Add qspi_clock
The qspi_clk frequency is updated by U-Boot before starting Linux.
Add QSPI interface node.
Add QSPI flash memory child node.
Setup the QSPI memory in 2 partitions.
Signed-off-by: Thor Thayer
---
v2 s/_/-/ in qspi-clk
rename flash node.
use
;data = of_match_node(altr_edac_device_of_match, np)->data;
Thank you for this patch!
Acked-by: Thor Thayer
gentle ping...
On 09/29/2017 11:07 AM, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
Allow ARM64 support for the Cadence QSPI interface by
adding ARM64 as a dependency.
Signed-off-by: Thor Thayer
---
drivers/mtd/spi-nor/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion
On 10/06/2017 10:00 AM, Marek Vasut wrote:
On 10/06/2017 04:56 PM, Thor Thayer wrote:
gentle ping...
On 09/29/2017 11:07 AM, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
Allow ARM64 support for the Cadence QSPI interface by
adding ARM64 as a dependency.
Signed-off-by: Thor Thayer
Hi Wolfram,
Thank you for reviewing.
On 07/31/2017 08:31 AM, Wolfram Sang wrote:
Hi Thor,
thanks for the patches! A few comments and questions from me.
On Mon, Jul 17, 2017 at 11:35:14AM -0500, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
Add driver support for the Altera I2C
From: Thor Thayer
Allow ARM64 support for the Cadence QSPI interface by
adding ARM64 as a dependency.
Signed-off-by: Thor Thayer
---
drivers/mtd/spi-nor/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index
On 09/13/2017 03:50 PM, Wolfram Sang wrote:
On Mon, Sep 11, 2017 at 04:17:20PM -0500, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
Add driver support for the Altera I2C Controller. The I2C
controller is soft IP for use in FPGAs.
Signed-off-by: Thor Thayer
Reviewed-by: Andy
Hi.
On 08/14/2017 11:28 AM, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
Add driver support for the Altera I2C Controller. The I2C
controller is soft IP for use in FPGAs.
Signed-off-by: Thor Thayer
Reviewed-by: Andy Shevchenko
---
v2 Remove altr, from fifo-size to agree
-altera.c | 3 +++
For the Altera GPIO files:
Acked-by: Thor Thayer
From: Thor Thayer
Add the documentation to support the Altera synthesizable
logic I2C Controller in FPGA.
Signed-off-by: Thor Thayer
Acked-by: Rob Herring
---
v2 Change the subject to identify dt-bindings
Add synthesizable logic to description.
Change compatible string to "
From: Thor Thayer
Add driver support for the Altera I2C Controller. The I2C
controller is soft IP for use in FPGAs.
Signed-off-by: Thor Thayer
---
v2 Remove altr, from fifo-size to agree with bindings.
Change compatible string to "altr,softip-i2c"
v3 Add version to compati
On 08/14/2017 03:43 PM, Andy Shevchenko wrote:
On Mon, Aug 14, 2017 at 7:28 PM, wrote:
From: Thor Thayer
Add driver support for the Altera I2C Controller. The I2C
controller is soft IP for use in FPGAs.
Hmm...
Could you remind me if I reviewed this and gave a tag?
If yes, where is the tag
Hi Sudeep,
On 04/04/2018 05:47 AM, Sudeep Holla wrote:
On 30/03/18 00:00, Thor Thayer wrote:
Hi,
I'm working on an ARM64 architecture that needs to manipulate some
protected registers that are only accessible in EL3. Linux is running at
EL1 which doesn't have the proper permissions
Hi. Any comments on this patch?
On 03/26/2018 09:12 AM, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
The current Cadence QSPI driver caused a kernel panic when loading
a Root Filesystem from QSPI. The problem was caused by reading more
bytes than needed because the QSPI operated on 4
Hi. Any comments on this patch?
On 03/26/2018 02:50 PM, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
Remove QSPI Sector 4K size force which is causing QSPI boot
problems with the JFFS2 root filesystem.
Fixes the following error:
"Magic bitmask 0x1985 not found at ...&quo
From: Thor Thayer
The current Cadence QSPI driver caused a kernel panic when loading
a Root Filesystem from QSPI. The problem was caused by reading more
bytes than needed because the QSPI operated on 4 bytes at a time.
[7.947754] spi_nor_read[1048]:from 0x037cad74, len 1 [bfe07fff
Hi Andy,
On 07/08/2017 04:41 PM, Andy Shevchenko wrote:
On Sat, Jul 8, 2017 at 12:08 AM, Thor Thayer
wrote:
On 07/07/2017 11:25 AM, Andy Shevchenko wrote:
On Mon, Jun 19, 2017 at 11:36 PM, wrote:
+ while (bytes_to_transfer-- > 0) {
+ *idev->buf++ = readl(idev
gpio_chip altr_a10sr_gc = {
+static const struct gpio_chip altr_a10sr_gc = {
.label = "altr_a10sr_gpio",
.owner = THIS_MODULE,
.get = altr_a10sr_gpio_get,
Reviewed-by: Thor Thayer
Hi Andy,
On 07/07/2017 11:25 AM, Andy Shevchenko wrote:
On Mon, Jun 19, 2017 at 11:36 PM, wrote:
Either...
+#include
...or...
+#include
...choose one.
+#define ALTR_I2C_THRESHOLD 0 /*IRQ Threshold at 1 element */
Space missed.
Got it. Thanks!
+/**
+ *
On 06/29/2017 05:03 AM, Borislav Petkov wrote:
Hi,
any objections?
---
It is a write-only variable so get rid of it.
Signed-off-by: Borislav Petkov
Cc: Thor Thayer
Cc: Mark Gross
Cc: Robert Richter
Cc: Tim Small
Cc: Ranganathan Desikan
Cc: "Arvind R."
Cc: Jason Baron
Cc: Ton
Hi,
On 06/19/2017 03:36 PM, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
Add driver support for the Altera I2C Controller. The I2C
controller is soft IP for use in FPGAs.
Signed-off-by: Thor Thayer
---
v2 Remove altr, from fifo-size to agree with bindings.
Change compatible
From: Thor Thayer
This patch series adds the Altera I2C Controller driver for use in FPGAs.
This version includes cleanup and a bug fix noticed by the Linux
community.
Thor Thayer (3):
MAINTAINERS: Add Altera I2C Controller Driver
dt-bindings: i2c: Add Altera I2C Controller
i2c: altera
From: Thor Thayer
Add the documentation to support the Altera synthesizable
logic I2C Controller in FPGA.
Signed-off-by: Thor Thayer
Acked-by: Rob Herring
---
v2 Change the subject to identify dt-bindings
Add synthesizable logic to description.
Change compatible string to "
From: Thor Thayer
Add driver support for the Altera I2C Controller. The I2C
controller is soft IP for use in FPGAs.
Signed-off-by: Thor Thayer
---
v2 Remove altr, from fifo-size to agree with bindings.
Change compatible string to "altr,softip-i2c"
v3 Add version to compati
From: Thor Thayer
Add maintainer for the Altera I2C Controller Driver.
Signed-off-by: Thor Thayer
---
v2-5 No change
---
MAINTAINERS | 5 +
1 file changed, 5 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 6f08ce7..5ee85d8a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -636,6
From: Thor Thayer
Add the documentation to support the Altera synthesizable
logic I2C Controller in FPGA.
Signed-off-by: Thor Thayer
---
v2 Change the subject to identify dt-bindings
Add synthesizable logic to description.
Change compatible string to "altr,softip-i2c"
From: Thor Thayer
Add maintainer for the Altera I2C Controller Driver.
Signed-off-by: Thor Thayer
---
v2&3 No change
---
MAINTAINERS | 5 +
1 file changed, 5 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 9609ca6..86053d6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6
From: Thor Thayer
Add driver support for the Altera I2C Controller. The I2C
controller is soft IP for use in FPGAs.
Signed-off-by: Thor Thayer
---
v2 Remove altr, from fifo-size to agree with bindings.
Change compatible string to "altr,softip-i2c"
v3 Add version to compati
From: Thor Thayer
This patch seris add the Altera I2C Controller driver for use in FPGAs.
Thor Thayer (4):
ARM: dts: socfpga: Add Altera I2C Controller to CycloneV
MAINTAINERS: Add Altera I2C Controller Driver
dt-bindings: i2c: Add Altera I2C Controller
i2c: altera: Add Altera I2C
From: Thor Thayer
Add the Altera I2C Controller to the CycloneV SoCFPGA device tree.
Signed-off-by: Thor Thayer
---
v2 Remove altr, from fifo-size.
Rename compatible string to "altr,softip-i2c"
v3 Add version to commpatible string "altr,softip-i2c-v1.0"
--
From: Thor Thayer
Add the documentation to support the Altera synthesizable
logic I2C Controller in FPGA.
Signed-off-by: Thor Thayer
Acked-by: Rob Herring
---
v2 Change the subject to identify dt-bindings
Add synthesizable logic to description.
Change compatible string to "
From: Thor Thayer
Add driver support for the Altera I2C Controller. The I2C
controller is soft IP for use in FPGAs.
Signed-off-by: Thor Thayer
Reviewed-by: Andy Shevchenko
---
v2 Remove altr, from fifo-size to agree with bindings.
Change compatible string to "altr,softip-i2c&quo
+ WRITE_ONCE(E1, E2)
@ depends on patch @
expression E;
@@
- ACCESS_ONCE(E)
+ READ_ONCE(E)
Signed-off-by: Mark Rutland
Cc: Borislav Petkov
Cc: Thor Thayer
---
drivers/edac/altera_edac.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/edac/altera_edac.c b
From: Thor Thayer
Newer versions (V2) of Altera/Intel FPGAs CvP have different PCI
Vendor Specific Capability offsets than the older (V1) Altera/FPGAs.
Most of the CvP registers and their bitfields remain the same
between both the older parts and the newer parts.
This patchset implements
From: Thor Thayer
In preparation for adding newer V2 parts that use a FIFO,
reorganize altera_cvp_chk_error() and change the write
function to block based.
V2 parts have a block size matching the FIFO while older
V1 parts write a 32 bit word at a time.
Signed-off-by: Thor Thayer
---
v2 Remove
From: Thor Thayer
Newer Intel FPGAs have different Vendor Specific offsets than
legacy parts. Use PCI discovery to find the CvP registers.
Since the register positions remain the same, change the hard
coded address to a more flexible way of indexing registers
from the offset.
Adding new PCI read
From: Thor Thayer
Add Stratix10 specific functions that use a credit mechanism
to throttle data to the CvP FIFOs. Add a private structure
with function pointers for V1 vs V2 functions.
Signed-off-by: Thor Thayer
---
v2 Remove inline function declaration
Reverse Christmas Tree format
From: Thor Thayer
The current Cadence QSPI driver sometimes caused a
"rcu_sched self-detected stall" while writing large files.
Stall Report:
'# mtd_debug write /dev/mtd1 0 48816464 blob.img
[ 1815.454227] rcu: INFO: rcu_sched self-detected stall on CPU
[ 1815.459789] rcu: 0-.
Hi Moritz,
On 7/21/19 7:56 PM, Moritz Fischer wrote:
Hi Thor,
looks mostly good.
On Tue, Jul 16, 2019 at 05:48:07PM -0500, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
Add Stratix10 specific functions that use a credit mechanism
to throttle data to the CvP FIFOs. Add a private
Hi Moritz,
On 7/21/19 7:59 PM, Moritz Fischer wrote:
Thor,
On Tue, Jul 16, 2019 at 05:48:06PM -0500, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
In preparation for adding newer V2 parts that use a FIFO,
reorganize altera_cvp_chk_error() and change the write
function to block based
From: Thor Thayer
The current Cadence QSPI driver sometimes caused a
"rcu_sched self-detected stall" while writing large files.
Stall Report:
'# mtd_debug write /dev/mtd1 0 48816464 blob.img
[ 1815.454227] rcu: INFO: rcu_sched self-detected stall on CPU
[ 1815.459789] rcu: 0-.
Hi Moritz,
On 7/24/19 9:57 AM, Moritz Fischer wrote:
On Tue, Jul 23, 2019 at 09:40:51AM -0500, Thor Thayer wrote:
Hi Moritz,
On 7/21/19 7:59 PM, Moritz Fischer wrote:
Thor,
On Tue, Jul 16, 2019 at 05:48:06PM -0500, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
In preparation
On 7/14/19 1:46 PM, Moritz Fischer wrote:
Hi Thor,
On Thu, Jul 11, 2019 at 03:32:49PM -0500, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
In preparation for adding newer V2 parts that use a FIFO,
reorganize altera_cvp_chk_error() and change the write
function to block based.
V2 parts
Hi Moritz,
On 7/14/19 1:55 PM, Moritz Fischer wrote:
Hi Thor,
On Thu, Jul 11, 2019 at 03:32:50PM -0500, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
Add Stratix10 specific functions that use a credit mechanism
to throttle data to the CvP FIFOs. Add a private structure
with function
From: Thor Thayer
Newer versions (V2) of Altera/Intel FPGAs CvP have different PCI
Vendor Specific Capability offsets than the older (V1) Altera/FPGAs.
Most of the CvP registers and their bitfields remain the same
between both the older parts and the newer parts.
This patchset implements
From: Thor Thayer
Newer Intel FPGAs have different Vendor Specific offsets than
legacy parts. Use PCI discovery to find the CvP registers.
Since the register positions remain the same, change the hard
coded address to a more flexible way of indexing registers
from the offset.
Adding new PCI read
From: Thor Thayer
Add Stratix10 specific functions that use a credit mechanism
to throttle data to the CvP FIFOs. Add a private structure
with function pointers for V1 vs V2 functions.
Signed-off-by: Thor Thayer
---
v2 Remove inline function declaration
Reverse Christmas Tree format
From: Thor Thayer
In preparation for adding newer V2 parts that use a FIFO,
reorganize altera_cvp_chk_error() and change the write
function to block based.
V2 parts have a block size matching the FIFO while older
V1 parts write a 32 bit word at a time.
Signed-off-by: Thor Thayer
---
v2 Remove
From: Thor Thayer
Newer versions (V2) of Altera/Intel FPGAs CvP have different PCI
Vendor Specific Capability offsets than the older (V1) Altera/FPGAs.
Most of the CvP registers and their bitfields remain the same
between both the older parts and the newer parts.
This patchset implements
From: Thor Thayer
In preparation for adding newer V2 parts that use a FIFO,
reorganize altera_cvp_chk_error() and change the write
function to block based.
V2 parts have a block size matching the FIFO while older
V1 parts write a 32 bit word at a time.
Signed-off-by: Thor Thayer
---
drivers
From: Thor Thayer
Add Stratix10 specific functions that use a credit mechanism
to throttle data to the CvP FIFOs. Add a private structure
with function pointers for V1 vs V2 functions.
Signed-off-by: Thor Thayer
---
drivers/fpga/altera-cvp.c | 173
From: Thor Thayer
Newer Intel FPGAs have different Vendor Specific offsets than
legacy parts. Use PCI discovery to find the CvP registers.
Since the register positions remain the same, change the hard
coded address to a more flexible way of indexing registers
from the offset.
Adding new PCI read
From: Thor Thayer
ARM32 SoCFPGAs had separate IRQs for SDRAM. ARM64 SoCFPGAs
send all DBEs to SError so filtering by source is necessary.
The Stratix10 SDRAM ECC is a better match with the generic
Altera peripheral ECC framework because the linked list can
be searched to find the ECC block
Hi Moritz,
On 7/14/19 1:40 PM, Moritz Fischer wrote:
On Thu, Jul 11, 2019 at 03:32:48PM -0500, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
Newer Intel FPGAs have different Vendor Specific offsets than
legacy parts. Use PCI discovery to find the CvP registers.
Since the register
From: Thor Thayer
Newer versions (V2) of Altera/Intel FPGAs CvP have different PCI
Vendor Specific Capability offsets than the older (V1) Altera/FPGAs.
Most of the CvP registers and their bitfields remain the same
between both the older parts and the newer parts.
This patchset implements
From: Thor Thayer
Add Stratix10 specific functions that use a credit mechanism
to throttle data to the CvP FIFOs. Add a private structure
with function pointers for V1 vs V2 functions.
Signed-off-by: Thor Thayer
---
v2 Remove inline function declaration
Reverse Christmas Tree format
From: Thor Thayer
Newer Intel FPGAs have different Vendor Specific offsets than
legacy parts. Use PCI discovery to find the CvP registers.
Since the register positions remain the same, change the hard
coded address to a more flexible way of indexing registers
from the offset.
Adding new PCI read
From: Thor Thayer
In preparation for adding newer V2 parts that use a FIFO,
reorganize altera_cvp_chk_error() and change the write
function to block based.
V2 parts have a block size matching the FIFO while older
V1 parts write a 32 bit word at a time.
Signed-off-by: Thor Thayer
---
v2 Remove
Hi James,
On 7/25/19 7:46 AM, James Morse wrote:
Hi Thor,
On 12/07/2019 19:28, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
ARM32 SoCFPGAs had separate IRQs for SDRAM. ARM64 SoCFPGAs
send all DBEs to SError so filtering by source is necessary.
The Stratix10 SDRAM ECC is a better
From: Thor Thayer
Newer versions (V2) of Altera/Intel FPGAs CvP have different PCI
Vendor Specific Capability offsets than the older (V1) Altera/FPGAs.
Most of the CvP registers and their bitfields remain the same
between both the older parts and the newer parts.
This patchset implements
From: Thor Thayer
Newer Intel FPGAs have different Vendor Specific offsets than
legacy parts. Use PCI discovery to find the CvP registers.
Since the register positions remain the same, change the hard
coded address to a more flexible way of indexing registers
from the offset.
Adding new PCI read
From: Thor Thayer
Add Stratix10 specific functions that use a credit mechanism
to throttle data to the CvP FIFOs. Add a private structure
with function pointers for V1 vs V2 functions.
Signed-off-by: Thor Thayer
---
v2 Remove inline function declaration
Reverse Christmas Tree format
From: Thor Thayer
In preparation for adding newer V2 parts that use a FIFO,
reorganize altera_cvp_chk_error() and change the write
function to block based.
V2 parts have a block size matching the FIFO while older
V1 parts write a 32 bit word at a time.
Signed-off-by: Thor Thayer
---
v2 Remove
Hi Kedar & Moritz,
On 9/27/19 12:13 AM, Appana Durga Kedareswara Rao wrote:
Hi Alan,
Did you get a chance to send your framework changes to upstream?
@Moritz Fischer: If Alan couldn't send his patch series, Can we take this patch
series??
Please let me know your thoughts on this.
Regards,
Hi Moritz,
On 9/27/19 1:23 PM, Moritz Fischer wrote:
Thor,
On Fri, Sep 27, 2019 at 09:32:11AM -0500, Thor Thayer wrote:
Hi Kedar & Moritz,
On 9/27/19 12:13 AM, Appana Durga Kedareswara Rao wrote:
Hi Alan,
Did you get a chance to send your framework changes to upstream?
No they wer
Hi Moritz,
On 10/7/19 4:20 PM, Moritz Fischer wrote:
Hi Thor,
On Mon, Oct 07, 2019 at 01:06:51PM -0500, Thor Thayer wrote:
Hi Moritz,
On 9/27/19 1:23 PM, Moritz Fischer wrote:
Thor,
On Fri, Sep 27, 2019 at 09:32:11AM -0500, Thor Thayer wrote:
Hi Kedar & Moritz,
On 9/27/19 12:1
= devm_clk_get(>dev, NULL);
if (IS_ERR(idev->i2c_clk)) {
Reviewed-by: Thor Thayer
On 7/29/20 12:45 PM, Dinh Nguyen wrote:
Thor Thayer is leaving Intel and will no longer be able to maintain the
EDAC for SoCFPGA, thus transfer maintainership to Dinh Nguyen.
Signed-off-by: Dinh Nguyen
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On 7/27/20 4:46 AM, Ooi, Joyce wrote:
From: Joyce Ooi
This patch is to replace Thor Thayer as Altera Triple Speed Ethernet
maintainer as he is moving to a different role.
Signed-off-by: Joyce Ooi
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
_buffer(priv, buffer);
+ if (ret)
+ goto out;
skb_tx_timestamp(skb);
Reviewed-by: Thor Thayer
. */
- priv->rx_ring_size = dma_rx_num;
- priv->tx_ring_size = dma_tx_num;
ret = alloc_init_skbufs(priv);
if (ret) {
netdev_err(dev, "DMA descriptors initialization failed\n");
Reviewed-by: Thor Thayer
(*get_rx_status)(struct altera_tse_private *priv);
+ int (*init_dma)(struct altera_tse_private *priv);
+ void (*uninit_dma)(struct altera_tse_private *priv);
+ void (*start_rxdma)(struct altera_tse_private *priv);
};
/* This structure is private to each device.
Reviewed-by: Thor
static const struct of_device_id altera_tse_ids[] = {
Reviewed-by: Thor Thayer
tic inline
+void csrwr8(u8 val, void __iomem *mac, size_t offs)
+{
+ void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
+
+ writeb(val, paddr);
+}
#endif /* __ALTERA_UTILS_H__*/
Reviewed-by: Thor Thayer
/* __ALTERA_SGDMA_H__ */
Reviewed-by: Thor Thayer
_tse_private *priv,
+struct tse_buffer *buffer);
u32 (*tx_completions)(struct altera_tse_private *priv);
void (*add_rx_desc)(struct altera_tse_private *priv,
struct tse_buffer *buffer);
Reviewed-by: Thor Thayer
On 7/8/20 2:23 AM, Ooi, Joyce wrote:
From: Dalon Westergreen
Add support for the ptp clock used with the tse, and update
the driver to support timestamping when enabled. We also
enable debugfs entries for the ptp clock to allow some user
control and interaction with the ptp clock.
Cc:
System Manager driver
3. Altera System Resource driver
Signed-off-by: Richard Gong
No ack from Thor?
:(
I was too slow... :)
Acked-by: Thor Thayer
From: Thor Thayer
The Stratix10 peripheral FIFO memories can recover from double
bit errors with a warm reset instead of a cold reset.
Add the option of a warm reset for peripheral (USB, Ethernet)
memories.
CPU memories such as SDRAM and OCRAM require a cold reset for
DBEs.
Filter on whether
On 6/3/19 10:50 AM, Suzuki K Poulose wrote:
Use the new helper to find device by of_node.
Cc: Thor Thayer
Cc: Lee Jones
Signed-off-by: Suzuki K Poulose
Acked-by: Thor Thayer
my patch and bringing in additional expertise.
On 03/06/2019 21:37, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
The Stratix10 peripheral FIFO memories can recover from double
bit errors with a warm reset instead of a cold reset.
Add the option of a warm reset for peripheral (USB
21:37, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
The Stratix10 peripheral FIFO memories can recover from double
bit errors with a warm reset instead of a cold reset.
Add the option of a warm reset for peripheral (USB, Ethernet)
memories.
CPU memories such as SDRAM and OCRAM require
From: Thor Thayer
ARM32 SoCFPGAs had separate IRQs for SDRAM. ARM64 SoCFPGAs
send all DBEs to SError so filtering by source is necessary.
The Stratix10 SDRAM ECC is a better match with the generic
Altera peripheral ECC framework because the linked list can
be searched to find the ECC block
Hi Moritz,
On 7/26/19 3:42 PM, Moritz Fischer wrote:
On Thu, Jul 25, 2019 at 10:16:48AM -0500, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
Add Stratix10 specific functions that use a credit mechanism
to throttle data to the CvP FIFOs. Add a private structure
with function pointers
-by: Thor Thayer
From: Thor Thayer
The SOCFPGA System Manager register block aggregates different
peripheral functions into one area.
On 32 bit ARM parts, handle in the same way as syscon.
On 64 bit ARM parts, the System Manager can only be accessed by
EL3 secure mode. Since a SMC call to EL3 is required
From: Thor Thayer
Enable the Stratix10 System Manager by default.
Signed-off-by: Thor Thayer
---
v2-4 No change
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index c8432e24207e..48a312126cf7
From: Thor Thayer
Add MFD driver for SOCFPGA System Manager to handle
System Manager calls differently for ARM32 vs ARM64.
The SOCFPGA System Manager includes registers from several
SOC peripherals.
On ARM32, syscon handles this aggregated register grouping.
Implement System Manager calls
From: Thor Thayer
Add the device tree bindings for the Stratix10 System Manager.
Signed-off-by: Thor Thayer
Reviewed-by: Rob Herring
---
v2 New compatible string and usage for Stratix10
v3 No change
v4 Add Reviewed-by from v2.
---
.../devicetree/bindings/arm/altera/socfpga-system.txt
From: Thor Thayer
The ARM64 System Manager requires a different method of reading
the System Manager than ARM32. A new System Manager driver was
created to steer ARM32 System Manager calls to regmap_mmio and
ARM64 System Manager calls to the new access method.
Convert from syscon to the shared
From: Thor Thayer
Use the new compatible string defined for the Stratix10
System Manager. Remove syscon since it is not correct
on this platform.
Signed-off-by: Thor Thayer
---
v2 New. Use new Stratix10 System Manager compatible
v3 Use "altr,sys-mgr" as the non-specific comp
From: Thor Thayer
Add System Manager driver by default for SOCFPGA ARM32 platforms.
Signed-off-by: Thor Thayer
---
v2-4 No change
---
arch/arm/configs/socfpga_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/socfpga_defconfig
b/arch/arm/configs/socfpga_defconfig
From: Thor Thayer
Add MFD driver for SOCFPGA System Manager to handle
System Manager calls differently for ARM32 vs ARM64.
The SOCFPGA System Manager includes registers from several
SOC peripherals.
On ARM32, syscon handles this aggregated register grouping.
Implement System Manager calls
From: Thor Thayer
The SOCFPGA System Manager register block aggregates different
peripheral functions into one area.
On 32 bit ARM parts, handle in the same way as syscon.
On 64 bit ARM parts, the System Manager can only be accessed by
EL3 secure mode. Since a SMC call to EL3 is required
From: Thor Thayer
Add System Manager driver by default for SOCFPGA ARM32 platforms.
Signed-off-by: Thor Thayer
---
v2-3 No change
---
arch/arm/configs/socfpga_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/socfpga_defconfig
b/arch/arm/configs/socfpga_defconfig
From: Thor Thayer
Add the device tree bindings for the Stratix10 System Manager.
Signed-off-by: Thor Thayer
---
v2 New compatible string and usage for Stratix10
v3 No change
---
.../devicetree/bindings/arm/altera/socfpga-system.txt| 12
1 file changed, 12 insertions
From: Thor Thayer
Use the new compatible string defined for the Stratix10
System Manager. Remove syscon since it is not correct
on this platform. Use "altr,sys-mgr" as the non-specific
fallback compatible.
Signed-off-by: Thor Thayer
---
v2 New. Use new Stratix10 System Manager com
From: Thor Thayer
Enable the Stratix10 System Manager by default.
Signed-off-by: Thor Thayer
---
v2-3 No change
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index c8432e24207e..48a312126cf7
From: Thor Thayer
The ARM64 System Manager requires a different method of reading
the System Manager than ARM32. A new System Manager driver was
created to steer ARM32 System Manager calls to regmap_mmio and
ARM64 System Manager calls to the new access method.
Convert from syscon to the shared
201 - 300 of 463 matches
Mail list logo
