e has been inserted, which is not the case here.
Signed-off-by: Tudor Ambarus <tudor-dan.amba...@nxp.com>
---
lib/asn1_decoder.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/lib/asn1_decoder.c b/lib/asn1_decoder.c
index 2b3f46c..b1ffcab 100644
--- a/lib/asn1_decoder.c
+++ b/lib/asn1_de
symbol 'atmel_ecc_i2c_client_alloc' was not declared. Should it be static?
symbol 'atmel_ecc_i2c_client_free' was not declared. Should it be static?
Signed-off-by: Colin Ian King <colin.k...@canonical.com>
Acked-by: Tudor Ambarus <tudor.amba...@microchip.com>
Thanks,
ta
uest_set_callback(skreq, pctx->flags,
crypto_ccm_decrypt_done, req);
Reviewed-by: Tudor Ambarus <tudor.amba...@microchip.com>
Hi, Romain,
On 10/31/2017 05:25 PM, Romain Izard wrote:
When using the rfc4543(gcm(aes))) mode, the registers of the hardware
engine are not empty after use. If the engine is not reset before its
next use, the following results will be invalid.
Always reset the hardware engine.
Thanks for
On 05/07/2018 08:14 PM, Marek Vasut wrote:
But indeed there are -- to my knowledge -- no flashes with interleaved
erase blocks. And yes, there could be improvement in erasing exactly the
required chunk of flash with a fitting opcode:)
Thanks Marek.
Other improvement would be to minimize the
Hi, Marek, all,
I'm studying Cyrille's patch for non-uniform SPI NOR flash memories:
https://lkml.org/lkml/2017/4/15/70.
It's not clear to me whether interleaved regions are possible or not. I
read the JEDEC Standard No. 216B and it looks like each region is well
delimited, there is no such
ed-by: Cristian Birsan <cristian.bir...@microchip.com>
Signed-off-by: Tudor Ambarus <tudor.amba...@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 281 +++---
include/linux/mtd/spi-nor.h | 89 +
2 files changed, 356 insertions(+),
Hi, Marek,
On 05/21/2018 02:35 PM, Marek Vasut wrote:
On 05/18/2018 11:32 AM, Tudor Ambarus wrote:
From: Cyrille Pitchen <cyrille.pitc...@microchip.com>
This patch is a first step in introducing the support of SPI memories
with non-uniform erase sizes like Spansion s25fs512s.
It intr
Hi, Marek,
On 05/21/2018 07:59 PM, Marek Vasut wrote:
On 05/21/2018 06:42 PM, Tudor Ambarus wrote:
Hi, Marek,
[...]
This is a transitional patch: non-uniform erase maps will be used later
when initialized based on the SFDP data.
What about non-SFDP non-linear flashes ?
Non-SFDP non
Hi, Marek,
On 05/23/2018 12:56 PM, Marek Vasut wrote:
[...]
[...]
+while (len) {
+cmd = spi_nor_find_best_erase_cmd(map, region, addr, len);
+if (!cmd)
+return -EINVAL;
What would happen if you realize mid-way that you cannot erase some
sector , do you end up
Hi, Marek,
On 05/23/2018 03:54 PM, Marek Vasut wrote:
On 05/23/2018 02:52 PM, Tudor Ambarus wrote:
Hi, Marek,
Hi,
On 05/23/2018 12:56 PM, Marek Vasut wrote:
[...]
[...]
+while (len) {
+cmd = spi_nor_find_best_erase_cmd(map, region, addr, len);
+if (!cmd
Hi, Peter,
On 04/11/2018 06:34 PM, Nicolas Ferre wrote:
I'll try to move forward with your detailed explanation and with my
contacts within the "product" team internally.
We have talked with the hardware team, looks like there is an error in
the description of the Master to Slave Access
back to the uniform case.
The 'erase with the best command, move forward and repeat' approach was
suggested by Cristian Birsan in a brainstorm session, so:
Suggested-by: Cristian Birsan
Signed-off-by: Tudor Ambarus
---
drivers/mtd/spi-nor/spi-nor.c | 357
that the erase can be performed
- fix walking through the address space in overlaid regions
- drop wall-of-text description commit message, change author
Tudor Ambarus (1):
mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memories
drivers/mtd/spi-nor/spi-nor.c | 357
Hi, Peter,
On 05/28/2018 01:10 PM, Peter Rosin wrote:
[cut]
So, I think I want either
A) the NAND controller to use master 1 DMAC0/IF0 (i.e. slave 8 DDR2 port 2) and
the LCDC to use master 9 (i.e. slave 9 DDR2 Port 3)
or
B) the NAND controller to use master 2 DMAC0/IF1 (i.e. slave 7
Hi, Piotr,
General things to consider for the limitation in performance:
- is the serial flash memory operating in Quad SPI?
- QSCLK should be as high as possible
- transfer delays - I checked them, they have default values, we should be good.
- use DMA, as you suggested
On 06/22/2018 10:39 AM,
Markus Elfring<elfr...@users.sourceforge.net>
Reviewed-by: Tudor Ambarus <tudor.amba...@microchip.com>
assumption of the clock frequency.
Spare the i2c clients of making wrong assumptions of the i2c bus clock
frequency and enable the buses to save their clock frequency in adapter.
since rfc:
- reword commit messages
Tudor Ambarus (2):
i2c: enable buses to save their clock frequency in adapter
i2c
assumption of the clock frequency.
Spare the i2c clients of making wrong assumptions of the i2c bus clock
frequency and provide the bus clock frequency in adapter.
Signed-off-by: Tudor Ambarus
Acked-by: Ludovic Desroches
---
drivers/i2c/busses/i2c-at91.c | 1 +
1 file changed, 1 insertion(+)
diff
assumption of the clock frequency.
Spare the i2c clients of making wrong assumptions of the i2c bus clock
frequency and enable the buses to save their clock frequency in adapter.
Signed-off-by: Tudor Ambarus
---
include/linux/i2c.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux
As a side note, the SFDP code increases its size, it would make sense to move
all SFDP logic into a spi-nor-sfdp.c file. I'm volunteering to do this after
this patch set gets applied.
Best,
ta
Hi, Marek,
Did you have the chance to look over these patches? Please advise how can I move
forward with the non-uniform erase support.
Thanks,
ta
On 07/12/2018 08:32 PM, Tudor Ambarus wrote:
> Backward compatibility test done on mx25l3273fm2i-08g.
> Non-uniform erase test done on sst26
the Base Address Register (BAR).
Signed-off-by: Cyrille Pitchen
Signed-off-by: Tudor Ambarus
---
drivers/mtd/spi-nor/spi-nor.c | 148 ++
1 file changed, 148 insertions(+)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index
entire
memory
- fix support for overlaid regions.
Cyrille Pitchen (1):
mtd: spi-nor: parse SFDP 4-byte Address Instruction Table
Tudor Ambarus (2):
mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memories
mtd: spi-nor: parse SFDP Sector Map Parameter Table
drivers/mtd/sp
back to the uniform case.
The 'erase with the best command, move forward and repeat' approach was
suggested by Cristian Birsan in a brainstorm session, so:
Suggested-by: Cristian Birsan
Signed-off-by: Tudor Ambarus
---
drivers/mtd/spi-nor/spi-nor.c | 475
-by: Tudor Ambarus
---
drivers/mtd/spi-nor/spi-nor.c | 269 +++---
include/linux/mtd/spi-nor.h | 11 ++
2 files changed, 264 insertions(+), 16 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index c1e8169..522d5aa 100644
MX25U12835F names it Gang Block Unlock,
Winbound's W25Q128FV names it Global Block Unlock and
Microchip's SST26VF064B names it Global Block Protection Unlock.
Based on initial work done by Anurag Kumar Vulisha:
https://patchwork.kernel.org/patch/7611271/
Signed-off-by: Tudor Ambarus
---
drivers
The flash memories are write-protected by default at power-on and
must be unlocked first, before being erased, then programmed.
The erase block sizes are not uniform. The memory layout is uniform
just for the 4K sector blocks.
Based on initial work done by Cyrille Pitchen.
Signed-off-by: Tudor
To avoid inadvertent writes during power-up, sst26vf064b is
write-protected by default after a power-on reset cycle.
Unlock the serial flash memory by using the Global Block Protection
Unlock command - it offers a single command cycle that unlocks
the entire memory array.
Signed-off-by: Tudor
Thanks Marek,
On 09/03/2018 08:37 PM, Marek Vasut wrote:
> On 08/27/2018 12:26 PM, Tudor Ambarus wrote:
> [...]
>
>> +/* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */
>> +static inline u64
>> +spi_nor_div_by_erase_size(const struc
On 09/03/2018 08:40 PM, Marek Vasut wrote:
> On 08/27/2018 12:26 PM, Tudor Ambarus wrote:
> [...]
>> +static const u32 *spi_nor_get_map_in_use(struct spi_nor *nor, const u32
>> *smpt)
>> +{
>> +const u32 *ret = NULL;
>> +u32 i, addr;
>> +i
Marek,
On 09/07/2018 11:31 PM, Marek Vasut wrote:
> On 09/07/2018 10:51 AM, Tudor Ambarus wrote:
>> Thanks Marek,
>>
>> On 09/03/2018 08:37 PM, Marek Vasut wrote:
>>> On 08/27/2018 12:26 PM, Tudor Ambarus wrote:
>>> [...]
>>>
>>>> +/*
Cyrille's reviewed-by tag
- add cover letter
- fix link to initial work done by Anurag Kumar Vulisha
Tudor Ambarus (3):
mtd: spi-nor: add Global Block Unlock support
mtd: spi-nor: unlock global block protection on sst26vf064b
mtd: spi-nor: add support for Microchip SST26 QSPI flash memories
To avoid inadvertent writes during power-up, sst26vf064b is
write-protected by default after a power-on reset cycle.
Unlock the serial flash memory by using the Global Block Protection
Unlock command - it offers a single command cycle that unlocks
the entire memory array.
Signed-off-by: Tudor
MX25U12835F names it Gang Block Unlock,
Winbound's W25Q128FV names it Global Block Unlock and
Microchip's SST26VF064B names it Global Block Protection Unlock.
Based on initial work done by Anurag Kumar Vulisha:
https://lkml.org/lkml/2015/11/13/307
Signed-off-by: Tudor Ambarus
Reviewed-by: Cyrille
The flash memories are write-protected by default at power-on and
must be unlocked first, before being erased, then programmed.
The erase block sizes are not uniform. The memory layout is uniform
just for the 4K sector blocks.
Signed-off-by: Tudor Ambarus
---
drivers/mtd/spi-nor/spi-nor.c | 20
. Otherwise looks
good. I've also looked over the test with suspending while copying on a ubifs
mounted on QSPI NOR, looks good too.
After checking the return value, please add:
Reviewed-by: Tudor Ambarus
Best,
ta
> +
> + return atmel_qspi_init(aq);
> +}
> +
> +static SI
Hi, Arnd,
On 07/09/2018 06:57 PM, Arnd Bergmann wrote:
> + nc->ebi_csa_offs = (uintptr_t)match->data;
I guess we should declare ebi_csa_offs as size_t, right?
Best,
ta
back to the uniform case.
The 'erase with the best command, move forward and repeat' approach was
suggested by Cristian Birsan in a brainstorm session, so:
Suggested-by: Cristian Birsan
Signed-off-by: Tudor Ambarus
---
drivers/mtd/spi-nor/spi-nor.c | 475
-by: Tudor Ambarus
---
drivers/mtd/spi-nor/spi-nor.c | 269 +++---
include/linux/mtd/spi-nor.h | 11 ++
2 files changed, 264 insertions(+), 16 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 899b8c1..7c6291c 100644
erate them from the biggest to the smallest and stop when best
fitted command is found.
- determine at init if there are erase types that can erase the entire
memory
- fix support for overlaid regions.
Cyrille Pitchen (1):
mtd: spi-nor: parse SFDP 4-byte Address Instruction Table
Tudor Amb
the Base Address Register (BAR).
Signed-off-by: Cyrille Pitchen
Signed-off-by: Tudor Ambarus
---
drivers/mtd/spi-nor/spi-nor.c | 148 ++
1 file changed, 148 insertions(+)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index
Hi,
I will send a v2 in few days, together with the parsers for the optional SFDP
tables: Sector Map Parameter table and 4-byte Address Instruction table.
Below I detail what I'll change in v2 for this patch.
On 06/08/2018 04:48 PM, Tudor Ambarus wrote:
> Based on Cyrille Pitchen's patch ht
back to the uniform case.
The 'erase with the best command, move forward and repeat' approach was
suggested by Cristian Birsan in a brainstorm session, so:
Suggested-by: Cristian Birsan
Signed-off-by: Tudor Ambarus
---
drivers/mtd/spi-nor/spi-nor.c | 594
-by: Tudor Ambarus
---
drivers/mtd/spi-nor/spi-nor.c | 316 +++---
include/linux/mtd/spi-nor.h | 12 ++
2 files changed, 312 insertions(+), 16 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 4687345..fbefcdb 100644
there are erase types that can erase the entire
memory
- fix support for overlaid regions.
Tudor Ambarus (2):
mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memories
mtd: spi-nor: parse SFDP Sector Map Parameter Table
drivers/mtd/spi-nor/spi-nor.c | 910 ++
Hi, Kees,
On 03/07/2018 11:56 PM, Kees Cook wrote:
On the quest to remove all VLAs from the kernel[1], this switches to
a pair of kmalloc regions instead of using the stack. This also moves
the get_random_bytes() after all allocations (and drops the needless
"nbytes" variable).
[1]
On 03/08/2018 11:55 PM, Kees Cook wrote:
Looks like there are few intermediate buffers in ecc
that should be zeroized as well.
Can you send a patch for those?
Yeah, I'll take a look.
Best,
ta
l.org/lkml/2018/3/7/621
Signed-off-by: Kees Cook<keesc...@chromium.org>
Reviewed-by: Tudor Ambarus <tudor.amba...@microchip.com>
Hi, Gilad,
On 04/23/2018 10:25 AM, Gilad Ben-Yossef wrote:
Enable CryptoCell support for hardware keys.
Hardware keys are regular AES keys loaded into CryptoCell internal memory
via firmware, often from secure boot ROM or hardware fuses at boot time.
As such, they can be used for enc/dec
Hi, Piotr,
On 06/27/2018 10:52 AM, Piotr Bugalski wrote:
>
>> General things to consider for the limitation in performance:
>> - is the serial flash memory operating in Quad SPI?
>
> Yes, I've checked signal using logic analyzer, data is transferred using
> all four lines.
>
>> - QSCLK should
ECT_4K | USE_FSR | SPI_NOR_4B_OPCODES) },
> +
The style is slightly different from what Brian proposed back in
9648388fc7737365be7a8092e77df78ccc2cd1a4. For consistency reasons, I think we
should use the same style in all entries.
Since I verified the correctness of the patch and my comment targets just a
cosmetic change, I'll let the maintainers decide:
Reviewed-by: Tudor Ambarus
Hi,
Please amend this as well. Thanks!
---
drivers/mtd/spi-nor/spi-nor.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 3a9b69e9ba6d..3019708696cd 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++
Hi, Yogesh,
On 10/17/2018 10:46 AM, Yogesh Narayan Gaur wrote:
> Hi Boris,
>
>> -Original Message-
>> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
>> Sent: Wednesday, October 17, 2018 1:00 PM
>> To: Yogesh Narayan Gaur
>> Cc: Cyrille P
h Gaur
>
>> -Original Message-
>> From: linux-mtd [mailto:linux-mtd-boun...@lists.infradead.org] On Behalf Of
>> Tudor Ambarus
>> Sent: Tuesday, September 11, 2018 9:10 PM
>> To: marek.va...@gmail.com; dw...@infradead.org;
>> computersfor
On 09/19/2018 07:50 AM, Yogesh Gaur wrote:
> Some MICRON related macros in spi-nor domain were ST.
> Rename entries related to STMicroelectronics under macro SNOR_MFR_ST.
>
> Added entry of MFR Id for Micron flashes, 0x002C.
>
> Signed-off-by: Yogesh Gaur
Reviewed
at91sam9x5cm comes with a 2Gb NAND flash. Fix the rootfs size to
match this limit.
Signed-off-by: Tudor Ambarus
Acked-by: Ludovic Desroches
---
v2:
- collect Ludovic's Acked-by
arch/arm/boot/dts/at91sam9x5cm.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm
sama5d4_xplained, ssam9x5cm, sama5d2_ptc_ek and sama5d3_xplained nand
flashes have a common memory map. Even the nand memory partitions to
match our NAND flash map available at:
http://www.at91.com/linux4sam/pub/Linux4SAM/SambaSubsections//demo_nandflash_map_lnx4sam5x.png
Signed-off-by: Tudor
sama5d4_xplained comes with a 4Gb NAND flash. Increase the rootfs
size to match this limit.
Signed-off-by: Tudor Ambarus
Acked-by: Ludovic Desroches
---
v2:
- fix typo in subject line
- collect Ludovic's Acked-by
arch/arm/boot/dts/at91-sama5d4_xplained.dts | 2 +-
1 file changed, 1 insertion
sam9x5cm, sama5d2_ptc_ek, sama5d3_xplained and sama5d4_xplained nand
flashes have a common memory map. Even the nand memory partitions to
match our nand flash map available at:
http://www.at91.com/linux4sam/pub/Linux4SAM/SambaSubsections//demo_nandflash_map_lnx4sam5x.png
Signed-off-by: Tudor
The offsets for the bootloader environment and its redundant partition
were inverted. Fix the addresses to match our nand flash map available at:
http://www.at91.com/linux4sam/pub/Linux4SAM/SambaSubsections//demo_nandflash_map_lnx4sam5x.png
Signed-off-by: Tudor Ambarus
---
arch/arm/boot/dts
sam9x5cm, sama5d2_ptc_ek, sama5d3_xplained and sama5d4_xplained nand
flashes have a common memory map. Even the nand memory partitions to
match our NAND flash map available at:
http://www.at91.com/linux4sam/pub/Linux4SAM/SambaSubsections//demo_nandflash_map_lnx4sam5x.png
Tudor Ambarus (4):
ARM
sama5d3_xplained, sam9x5cm, sama5d2_ptc_ek and sama5d4_xplained nand
flashes have a common memory map. Even the nand memory partitions to
match our nand flash map available at:
http://www.at91.com/linux4sam/pub/Linux4SAM/SambaSubsections//demo_nandflash_map_lnx4sam5x.png
Signed-off-by: Tudor
at91sam9x5cm comes with a 2Gb NAND flash. Fix the rootfs size to
match this limit.
Signed-off-by: Tudor Ambarus
---
arch/arm/boot/dts/at91sam9x5cm.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi
b/arch/arm/boot/dts/at91sam9x5cm.dtsi
sama5d4_xplained comes with a 4Gb NAND flash. Increase the rootfs
size to match this limit.
Signed-off-by: Tudor Ambarus
---
arch/arm/boot/dts/at91-sama5d4_xplained.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/at91-sama5d4_xplained.dts
b/arch/arm
Hi,
On 09/19/2018 07:50 AM, Yogesh Gaur wrote:
> Add entry for mt35xu512aba Micron NOR flash.
> This flash is having uniform sector erase size of 128KB, have
> support of FSR(flag status register), flash size is 64MB and
> supports 4-byte commands.
>
Seems that the datasheet for mt35xu512aba is
Hi,
On 09/19/2018 07:50 AM, Yogesh Gaur wrote:
> Some MICRON related macros in spi-nor domain were ST.
> Rename entries related to STMicroelectronics under macro SNOR_MFR_ST.
>
> Added entry of MFR Id for Micron flashes, 0x002C.
>
> Signed-off-by: Yogesh Gaur
> ---
>
Hi, Nathan,
On 09/21/2018 01:29 PM, Nathan Chancellor wrote:
> Clang warns when one enumerated type is converted implicitly to another.
>
> drivers/mtd/spi-nor/cadence-quadspi.c:962:47: warning: implicit
> conversion from enumeration type 'enum dma_transfer_direction' to
> different enumeration
On 09/25/2018 10:34 AM, Nathan Chancellor wrote:
> On Tue, Sep 25, 2018 at 10:24:04AM +0300, Tudor Ambarus wrote:
>> Hi, Nathan,
>>
>> On 09/21/2018 01:29 PM, Nathan Chancellor wrote:
>>> Clang warns when one enumerated type is converted implicitly to anothe
>>> diff --git a/drivers/mtd/spi-nor/spi-nor.c
>>> @@ -271,6 +271,7 @@ static inline int set_4byte(struct spi_nor *nor, const
>> struct flash_info *info,
>>> u8 cmd;
>>>
>>> switch (JEDEC_MFR(info)) {
>>> + case SNOR_MFR_ST:
>>
>> We should mark switch cases where we are expecting to
Hi, Boris,
On 09/11/2018 06:40 PM, Tudor Ambarus wrote:
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
[cut]
> /*
I missed to use the opening comment mark for kernel-doc comments: "/**". This
observation applies to all newly introduced funct
o, we better don't take any chances and fix this by null
> checking pointer *nfc_np* before calling of_clk_get().
>
> Addresses-Coverity-ID: 1473052 ("Dereference null return value")
> Fixes: f88fc122cc34 ("mtd: nand: Cleanup/rework the atmel_nand driver")
>
On 02/15/2018 02:24 PM, SF Markus Elfring wrote:
From: Markus Elfring
Date: Thu, 15 Feb 2018 11:38:30 +0100
Omit extra messages for a memory allocation failure in these functions.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring
Reviewed-by: Tudor
Hi, Kees,
On 03/07/2018 11:56 PM, Kees Cook wrote:
On the quest to remove all VLAs from the kernel[1], this switches to
a pair of kmalloc regions instead of using the stack. This also moves
the get_random_bytes() after all allocations (and drops the needless
"nbytes" variable).
[1]
On 03/08/2018 11:55 PM, Kees Cook wrote:
Looks like there are few intermediate buffers in ecc
that should be zeroized as well.
Can you send a patch for those?
Yeah, I'll take a look.
Best,
ta
l.org/lkml/2018/3/7/621
Signed-off-by: Kees Cook
Reviewed-by: Tudor Ambarus
Hi, Gilad,
On 04/23/2018 10:25 AM, Gilad Ben-Yossef wrote:
Enable CryptoCell support for hardware keys.
Hardware keys are regular AES keys loaded into CryptoCell internal memory
via firmware, often from secure boot ROM or hardware fuses at boot time.
As such, they can be used for enc/dec
Hi, Marek, all,
I'm studying Cyrille's patch for non-uniform SPI NOR flash memories:
https://lkml.org/lkml/2017/4/15/70.
It's not clear to me whether interleaved regions are possible or not. I
read the JEDEC Standard No. 216B and it looks like each region is well
delimited, there is no such
On 05/07/2018 08:14 PM, Marek Vasut wrote:
But indeed there are -- to my knowledge -- no flashes with interleaved
erase blocks. And yes, there could be improvement in erasing exactly the
required chunk of flash with a fitting opcode:)
Thanks Marek.
Other improvement would be to minimize the
ata
when traversing the regions.
- backward compatibility test done on MX25L25673G.
The 'erase with the best command, move forward and repeat' approach was
suggested by Cristian Birsan in a brainstorm session, so:
]
Suggested-by: Cristian Birsan
Signed-off-by: Tudor Ambarus
---
drivers/mtd/spi-
m_decrypt_done, req);
Reviewed-by: Tudor Ambarus
Hi, Romain,
On 10/31/2017 05:25 PM, Romain Izard wrote:
When using the rfc4543(gcm(aes))) mode, the registers of the hardware
engine are not empty after use. If the engine is not reset before its
next use, the following results will be invalid.
Always reset the hardware engine.
Thanks for
' was not declared. Should it be static?
symbol 'atmel_ecc_i2c_client_free' was not declared. Should it be static?
Signed-off-by: Colin Ian King
Acked-by: Tudor Ambarus
Thanks,
ta
MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y.
Signed-off-by: Tudor Ambarus
---
v3:
- s/Winbound/Winbond/
- read CR.BPNV and check if we can really unlock the entire flash array
- sst26vf_unlock: return -EINVAL instead of -EOPNOTSUPP when caller
asks to unlock a range/granularity that we can't unlock
v2: v2: s/!ofs
in the Individual Block Protection mode, which is mutually
exclusive with the Block Protection mode (BP0-3).
Signed-off-by: Tudor Ambarus
Reviewed-by: Pratyush Yadav
Reviewed-by: Michael Walle
---
v3:
- s/Winbound/Winbond
- Add Michael's R-b tag
v2:
- s/mutual/mutually/
- set the GBULK cmd
MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y.
Signed-off-by: Tudor Ambarus
---
drivers/mtd/spi-nor/sst.c | 38 --
1 file changed, 36 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi-nor/sst.c b/drivers/mtd/spi-nor/sst.c
index 00e48da0744a..1cd2a360c41e 100644
.
Used in the Individual Block Protection mode, which is mutual
exclusive with the Block Protection mode (BP0-3).
Signed-off-by: Tudor Ambarus
---
drivers/mtd/spi-nor/core.c | 35 +++
drivers/mtd/spi-nor/core.h | 1 +
include/linux/mtd/spi-nor.h | 1 +
3 files
On Thu, 21 Jan 2021 01:18:47 -0800, Pan Bian wrote:
> Put the child node np when it fails to get or register device.
Applied to spi-nor/next, thanks!
[1/1] mtd: spi-nor: hisi-sfc: Put child node np on error path
https://git.kernel.org/mtd/c/fe6653460ee7
Best regards,
--
Tudor Ambarus
that are set via a non-volatile bit.
SPI_NOR_IO_MODE_EN_VOLATILE should be set just for the flashes that
don't define the optional SFDP SCCR Map, so that we don't pollute the
flash info flags.
Signed-off-by: Tudor Ambarus
---
drivers/mtd/spi-nor/core.c | 6 ++
drivers/mtd/spi-nor/core.h | 6 ++
2
polluting the flash flags when declaring
one.
Signed-off-by: Tudor Ambarus
---
drivers/mtd/spi-nor/sfdp.c | 52 ++
1 file changed, 52 insertions(+)
diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c
index f192710aca31..7bca64cbba02 100644
My biggest concern with Pratyush's patches is that the stateful modes case
(X-X-X modes that are entered via a non-volatile bit) is not handled.
This is an attempt to tackle this problem. Reasons and explanations in
the commit messages.
Tudor Ambarus (3):
mtd: spi-nor: Introduce
a stateful
mode in kernel, entering the stateful mode is still dangerous if one's
bootloader can't handle it. We need a way to pass the responsibility
to the user and let him decide conciously about the risks of allowing
stateful modes.
Signed-off-by: Tudor Ambarus
---
drivers/mtd/spi-nor
: NAND scan failed: -22
atmel-nand-controller: probe of 1000.ebi:nand-controller failed with error
-22
Tudor Ambarus (3):
mtd: rawnand: Fix wrongful fallthrough NAND_ECC_SOFT
mtd: rawnand: Introduce nand_set_ecc_on_host_ops()
mtd: rawnand: Don't overwrite the error code from
quot;switch (ecc->mode)" statement, and when a fallback to SW ECC is
needed, we fallthrough "case NAND_ECC_SOFT".
Fixes: d3f8ec8e979b ("mtd: rawnand: Separate the ECC engine type and the ECC
byte placement")
Reported-by: Santiago Esteban
Signed-off-by: Tudor Ambarus
---
There were too many levels of indentation and the code was
hard to read. Introduce a new function, similar to
nand_set_ecc_soft_ops().
Signed-off-by: Tudor Ambarus
---
drivers/mtd/nand/raw/nand_base.c | 114 +--
1 file changed, 61 insertions(+), 53 deletions(-)
diff
The error code received from nand_set_ecc_soft_ops() was overwritten,
drop this redundant assignment and use the error code received from
the callee.
Signed-off-by: Tudor Ambarus
---
drivers/mtd/nand/raw/nand_base.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers
Make sure the max_speed_hz of spi_device does not override
the max_speed_hz of controller.
Signed-off-by: Tudor Ambarus
---
drivers/spi/spi.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index cd3c395b4e90..51d7c004fbab 100644
avoid a superfluous init to zero when both spi->max_speed_hz
and spi->controller->max_speed_hz are zero.
Fixes: 9326e4f1e5dd ("spi: Limit the spi device max speed to controller's max
speed")
Reported-by: Geert Uytterhoeven
Suggested-by: Geert Uytterhoeven
Signed-off-by: Tudor Ambaru
.
Fixes: e590474768f1cc04 ("driver core: Set fw_devlink=on by default")
Signed-off-by: Tudor Ambarus
---
I'll be out of office, will check the rest of the at91 SoCs
at the begining of next week.
drivers/clk/at91/sama5d2.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/driver
ers caused the fail at boot.
Signed-off-by: Tudor Ambarus
---
Tested on sama5d2_xplained.
drivers/clk/at91/at91rm9200.c | 3 +--
drivers/clk/at91/at91sam9260.c | 16
drivers/clk/at91/at91sam9g45.c | 3 +--
drivers/clk/at91/at91sam9n12.c | 3 +--
drivers/clk/at91/at91sam9
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