On 10/1/20 12:12 PM, Peter Ujfalusi wrote:
> Hi Grygorii,
>
> On 30/09/2020 16.56, Grygorii Strashko wrote:
>>
>>
>> On 28/09/2020 11:34, Peter Ujfalusi wrote:
>>> It's JTAG PARTNO is 0xBB38.
>>>
>>> Signed-off-by: Peter Ujfalusi
>>> ---
>>> drivers/soc/ti/k3-socinfo.c | 1 +
>>> 1 file
On 9/30/20 6:37 PM, Ivan Mikhaylov wrote:
> On Wed, 2020-09-30 at 15:06 +0530, Vignesh Raghavendra wrote:
>>
>> On 9/21/20 4:54 PM, Ivan Mikhaylov wrote:
>>> Some chips like macronix don't have TB(Top/Bottom protection)
>>> bit in the status register. D
On 3/27/20 9:29 PM, Michael Walle wrote:
> Traditionally, linux unlocks the whole flash because there are legacy
> devices which has the write protections bits set by default at startup.
> If you actually want to use the flash protection bits, eg. because there
> is a read-only part for a
Hi,
On 9/21/20 4:54 PM, Ivan Mikhaylov wrote:
> Add locks for whole macronix chip series with BP0-2 and BP0-3 bits.
>
> Tested with mx25l51245g(BP0-3).
Since you have only tested on flash that have 4bit BP, please don't
modify flashes that have 3bit BP. Lets be conservative and enable only
On 9/21/20 4:54 PM, Ivan Mikhaylov wrote:
> Some chips like macronix don't have TB(Top/Bottom protection)
> bit in the status register. Do not write tb_mask inside status
> register, unless SPI_NOR_HAS_TB is present for the chip.
>
Not entirely accurate.. Macronix chips have TB bit in config
On Wed, 2 Sep 2020 16:00:40 -0700, Douglas Anderson wrote:
> On my system the spi_nor_probe() took ~6 ms at bootup. That's not a
> lot, but every little bit adds up to a slow bootup. While we can get
> this out of the boot path by making it a module, there are times where
> it is convenient (or
On Mon, 28 Sep 2020 14:06:31 +0800, Ikjoon Jang wrote:
> Add support Winbond w25q{64,128,256}jwm which are identical to existing
> w25q32jwm except for their sizes.
>
> This was tested with w25q64jwm, basic erase/write/readback and
> lock/unlock both lower/upper blocks were okay.
>
>
On Tue, 15 Sep 2020 12:06:23 +0200, Robert Marko wrote:
> According to the mx25l12805d datasheet it supports using 4K or 64K sectors.
> So lets add the SECT_4K to enable 4K sector usage.
>
> Datasheet:
>
On Thu, 24 Sep 2020 13:42:10 +0530, Vignesh Raghavendra wrote:
> This series add DMA support for reading data from HyperBus memory
> devices for TI's AM654/J721e SoCs
>
> With DMA there is ~5x improvement in read througput.
>
> v2:
> Fix DMAengine APIs usage issues
On 9/29/20 9:12 PM, tudor.amba...@microchip.com wrote:
> Hi, Pratyush,
>
> I'm replying to v10 so that we continue the discussion, but this applies to
> v13 as well.
>
> On 7/21/20 2:29 PM, Pratyush Yadav wrote:
>
@@ -2368,12 +2517,16 @@ spi_nor_spimem_adjust_hwcaps(struct spi_nor
On 9/29/20 3:29 PM, Tudor Ambarus wrote:
> Some users may teach their bootloaders to discover and recover a
> flash even when left in a statefull mode (a X-X-X I/O mode that is
> configured via a non-volatile bit).
>
> Provide a way for those users to enter in stateful modes. A reset
> or a
On 9/29/20 3:29 PM, Tudor Ambarus wrote:
> We don't want to enter a stateful mode, where a X-X-X I/O mode
> is entered by setting a non-volatile bit, because in case of a
> reset or a crash, once in the non-volatile mode, we may not be able
> to recover in bootloaders and we may break the SPI
Hi,
On 9/15/20 3:36 PM, Robert Marko wrote:
> According to the mx25l12805d datasheet it supports using 4K or 64K sectors.
> So lets add the SECT_4K to enable 4K sector usage.
>
> Datasheet:
> https://www.mxic.com.tw/Lists/Datasheet/Attachments/7321/MX25L12805D,%203V,%20128Mb,%20v1.2.pdf
Have
On 4/17/20 9:37 PM, Mika Westerberg wrote:
> On Fri, Apr 17, 2020 at 08:26:11AM -0700, Ronald G. Minnich wrote:
>> On Intel platforms, the usable SPI area is located several
>> MiB in from the start, to leave room for descriptors and
>> the Management Engine binary. Further, not all the
8 ++
> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 37 +++
> 2 files changed, 65 insertions(+)
>
For the series:
Tested-by: Vignesh Raghavendra
[1.678263] mmc0: Command Queue Engine enabled
[1.682727] mmc0: new HS200 MMC card at address
rd: Add USB support
>
> .../dts/ti/k3-j7200-common-proc-board.dts | 28 ++
> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 51 +++
> include/dt-bindings/mux/ti-serdes.h | 22
> 3 files changed, 101 insertions(+)
>
For the series:
Reviewed-by: Vignesh Raghavendra
AM654 HyperBus controller provides MMIO interface to read data from
flash. So add DMA memcpy support for reading data over MMIO interface.
This provides 5x improvement in throughput and reduces CPU usage as
well.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Peter Ujfalusi
---
drivers/mtd
This series add DMA support for reading data from HyperBus memory
devices for TI's AM654/J721e SoCs
With DMA there is ~5x improvement in read througput.
v2:
Fix DMAengine APIs usage issues pointed out by Peter.
Vignesh Raghavendra (4):
mtd: hyperbus: Provide per device private pointer
mtd
Recent genpd changes for K3 platform ensure device is ON before driver
probe is called. Therefore, drop redundant pm_runtime_* calls from
driver to simplify the code.
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/hyperbus/hbmc-am654.c | 16 ++--
1 file changed, 2 insertions
Setting up of direct mapping should be done with flash node's IO
address space and not with controller's IO region.
Fixes: b6fe8bc67d2d3 ("mtd: hyperbus: move direct mapping setup to AM654 HBMC
driver")
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/hyperbus/hbmc-am654.c | 4 ++
Provide per device private pointer that can be used by controller
drivers to store device specific private data.
Signed-off-by: Vignesh Raghavendra
---
include/linux/mtd/hyperbus.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/mtd/hyperbus.h b/include/linux/mtd/hyperbus.h
J7200 SoM has a HyperFlash connected to HyperBus memory controller. But
HyperBus is muxed with OSPI, therefore keep HyperBus node disabled.
Bootloader will detect the mux and enable the node as required.
Signed-off-by: Vignesh Raghavendra
---
arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 36
J7200 has a Flash SubSystem that has one OSPI and one HyperBus.. Add
DT nodes for HyperBus controller for now.
Signed-off-by: Vignesh Raghavendra
---
.../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3
This series adds HyperBus and HyperFlash nodes for TI's J7200 SoC
v2:
Rebase on latest ti-k3-next + I2C series
Align reg address format with this file's convention
Vignesh Raghavendra (2):
arm64: dts: ti: k3-j7200-mcu-wakeup: Add HyperBus node
arm64: dts: ti: k3-j7200-som-p0: Add HyperFlash
Add I2C and I2C IO expanders nodes for J7200
v2:
Align reg address format with that of file's (s/0x0/0x00)
Vignesh Raghavendra (2):
arm64: dts: ti: j7200: Add I2C nodes
arm64: dts: ti: k3-j7200-common-proc-board: Add I2C IO expanders
.../dts/ti/k3-j7200-common-proc-board.dts | 49
Add DT nodes for I2C GPIO expanders on main_i2c0 and main_i2c1 and
also add the pinmux corresponding to these I2C instances.
Signed-off-by: Vignesh Raghavendra
---
.../dts/ti/k3-j7200-common-proc-board.dts | 49 +++
1 file changed, 49 insertions(+)
diff --git a/arch/arm64
J7200 has 7 I2Cs in main domain, 2 I2Cs in MCU and 1 in wakeup domain.
Add DT nodes for the same.
Signed-off-by: Vignesh Raghavendra
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 77 +++
.../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 33
2 files changed, 110
Hello Linus,
Please pull the MTD changes for v5.9-rc6.
I am sending this on behalf of MTD maintainers group this time around.
Miquel/Richard,
Could you please ACK the PR?
Regards
Vignesh
The following changes since commit 856deb866d16e29bd65952e0289066f6078af773:
Linux 5.9-rc5
Recent genpd changes for K3 platform ensure device is ON before driver
probe is called. Therefore, drop redundant pm_runtime_* calls from
driver to simplify the code.
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/hyperbus/hbmc-am654.c | 16 ++--
1 file changed, 2 insertions
Setting up of direct mapping should be done with flash node's IO
address space and not with controller's IO region.
Fixes: b6fe8bc67d2d3 ("mtd: hyperbus: move direct mapping setup to AM654 HBMC
driver")
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/hyperbus/hbmc-am654.c | 4 ++
AM654 HyperBus controller provides MMIO interface to read data from
flash. So add DMA memcpy support for reading data over MMIO interface.
This provides 5x improvement in throughput and reduces CPU usage as
well.
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/hyperbus/hbmc-am654.c | 130
This series add DMA support for reading data from HyperBus memory
devices for TI's AM654/J721e SoCs
With DMA there is ~5x improvement in read througput.
Vignesh Raghavendra (4):
mtd: hyperbus: Provide per device private pointer
mtd: hyperbus: hbmc-am654: Fix direct mapping setup flash access
Provide per device private pointer that can be used by controller
drivers to store device specific private data.
Signed-off-by: Vignesh Raghavendra
---
include/linux/mtd/hyperbus.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/mtd/hyperbus.h b/include/linux/mtd/hyperbus.h
On 9/15/20 1:17 PM, Pratyush Yadav wrote:
> On 15/09/20 12:16PM, Vignesh Raghavendra wrote:
>>
>>
>> On 9/3/20 10:42 PM, Pratyush Yadav wrote:
>>> Hi,
>>>
>>> This series adds support for Octal DTR flashes in the SPI NOR framework,
>>&
On 9/3/20 10:42 PM, Pratyush Yadav wrote:
> Hi,
>
> This series adds support for Octal DTR flashes in the SPI NOR framework,
> and then adds hooks for the Cypress Semper and Micron Xcella flashes to
> allow running them in Octal DTR mode. This series assumes that the flash
> is handed to the
On 9/11/20 8:17 PM, Marco Felsch wrote:
> The sst write support for devices using the special SST_WRITE routine
> is broken since commit commit df5c21002cf4 ("mtd: spi-nor: use spi-mem
> dirmap API") because the spi_nor_create_write_dirmap() function checks
> SPINOR_OP_AAI_WP and
Hi,
On 9/3/20 9:48 PM, Daniel Gutson wrote:
> This patch exports information about the platform integrity
> firmware configuration in the sysfs filesystem.
> In this initial patch, I include some configuration attributes
> for the system SPI chip.
>
Please avoid first-person singular pronouns
t;;
> reg = <0x4090 0x4>;
> };
> @@ -349,7 +349,7 @@
> reg = <0x041e0 0x14>;
> };
>
> - ehrpwm_tbclk: syscon@4140 {
> + ehrpwm_tbclk: clock@4140 {
> compatible = "ti,am654-ehrpwm-tbclk", "syscon";
> reg = <0x4140 0x18>;
> #clock-cells = <1>;
>
Acked-by: Vignesh Raghavendra
gested-by: Suman Anna
> Suggested-by: Vignesh Raghavendra
> Signed-off-by: Nishanth Menon
> Reviewed-by: Lokesh Vutla
> Reviewed-by: Suman Anna
Acked-by: Vignesh Raghavendra
> ---
> Changes:
> v2: None (picked acks/reviews)
> v1: https://lore.kernel.org/linu
Hi Nishanth,
On 9/2/20 11:48 PM, Nishanth Menon wrote:
> On 11:51-20200902, Suman Anna wrote:
>> On 9/1/20 5:30 PM, Nishanth Menon wrote:
>>> Use adc@ naming for nodes following standard conventions of device
>>> tree (section 2.2.2 Generic Names recommendation in [1]).
>>>
>>> [1]
d DMA support for direct
mode reads")
Signed-off-by: Vignesh Raghavendra
Tested-by: Jan Kiszka
---
v2:
Update the Fixes tag and add collect tested-by
drivers/spi/spi-cadence-quadspi.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/spi-cadence-quadspi.c
On 8/28/20 1:56 PM, Jan Kiszka wrote:
> On 28.08.20 09:47, Vignesh Raghavendra wrote:
>> Buffers need to mapped to DMA channel's device pointer instead of SPI
>> controller's device pointer as its system DMA that actually does data
>> transfer.
>> Data inconsistenc
river to drivers/spi/")
Signed-off-by: Vignesh Raghavendra
---
This issue was present in the original driver under SPI NOR framework as well.
But only got exposed as driver started handling probe deferral for DMA channel
request and thus uses DMA almost always unlike before.
drivers/spi/spi-cadence
On 8/26/20 7:01 PM, Jan Kiszka wrote:
> On 26.08.20 14:18, Vignesh Raghavendra wrote:
>> On 8/26/20 3:42 PM, Jan Kiszka wrote:
>>> On 24.08.20 19:20, Jan Kiszka wrote:
>>>> On 24.08.20 14:49, Jan Kiszka wrote:
>>>>> On 24.08.20 13:45, Vignesh Raghave
On 8/26/20 3:42 PM, Jan Kiszka wrote:
> On 24.08.20 19:20, Jan Kiszka wrote:
>> On 24.08.20 14:49, Jan Kiszka wrote:
>>> On 24.08.20 13:45, Vignesh Raghavendra wrote:
>>>>
>>>>
>>>> On 8/22/20 11:35 PM, Jan Kiszka wro
pi: Move cadence-quadspi driver to drivers/spi/")
Reported-by: Jan Kiszka
Suggested-by: Boris Brezillon
Signed-off-by: Vignesh Raghavendra
---
drivers/spi/spi-cadence-quadspi.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/spi/spi-cadence-quadspi.c
b/drivers/sp
Hi Jan,
On 8/24/20 11:25 AM, Jan Kiszka wrote:
[...]
>> +MODULE_AUTHOR("Vignesh Raghavendra ");
>>
> On the AM65x, this changes mtd->name (thus mtd-id for
> parser/cmdlinepart) from 4704.spi.0 to spi7.0. The besides having to
> deal with both names now,
On 8/22/20 11:35 PM, Jan Kiszka wrote:
> On 01.06.20 09:04, Vignesh Raghavendra wrote:
>> dma_request_chan_by_mask() can throw EPROBE_DEFER if DMA provider
>> is not yet probed. Currently driver just falls back to using PIO mode
>> (which is less efficient) in this case.
J7200 has a Flash SubSystem that has one OSPI and one HyperBus.. Add
DT nodes for HyperBus controller for now.
Signed-off-by: Vignesh Raghavendra
---
.../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 27 +++
arch/arm64/boot/dts/ti/k3-j7200.dtsi | 8 --
2 files
This series adds HyperBus and HyperFlash nodes for TI's J7200 SoC
Based on top of
https://lore.kernel.org/linux-arm-kernel/20200723084628.19241-1-lokeshvu...@ti.com/
And earlier I2C DT patches:
https://lore.kernel.org/linux-arm-kernel/20200730192600.1872-1-vigne...@ti.com/
Vignesh Raghavendra
J7200 SoM has a HyperFlash connected to HyperBus memory controller. But
HyperBus is muxed with OSPI, therefore keep HyperBus node disabled.
Bootloader will detect the mux and enable the node as required.
Signed-off-by: Vignesh Raghavendra
---
arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 36
Add I2C and I2C IO expanders nodes for J7200
Based on top of
https://lore.kernel.org/linux-arm-kernel/20200723084628.19241-1-lokeshvu...@ti.com/
Vignesh Raghavendra (2):
arm64: dts: ti: j7200: Add I2C nodes
arm64: dts: ti: k3-j7200-common-proc-board: Add I2C IO expanders
.../dts/ti/k3
Add DT nodes for I2C GPIO expanders on main_i2c0 and main_i2c1 and
also add the pinmux corresponding to these I2C instances.
Signed-off-by: Vignesh Raghavendra
---
.../dts/ti/k3-j7200-common-proc-board.dts | 49 +++
1 file changed, 49 insertions(+)
diff --git a/arch/arm64
J7200 has 7 I2Cs main domain, 2 I2Cs in MCU and one in wakeup domain.
Add DT nodes of the same.
Signed-off-by: Vignesh Raghavendra
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 77 +++
.../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 33
2 files changed, 110
On 01/06/20 12:30 pm, tudor.amba...@microchip.com wrote:
> Hi, Mark,
>
> On Monday, June 1, 2020 8:47:25 AM EEST Vignesh Raghavendra wrote:
>> From: Ramuthevar Vadivel Murugan
>>
>>
>> Now that cadence-quadspi has been converted to use spi-mem framew
From: Ramuthevar Vadivel Murugan
Now that cadence-quadspi has been converted to use spi-mem framework,
move it under drivers/spi/
Update license header to match SPI subsystem style
Signed-off-by: Ramuthevar Vadivel Murugan
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Tudor Ambarus
9,17 +1318,14 @@ static int cqspi_probe(struct platform_device *pdev)
probe_clk_failed:
pm_runtime_put_sync(dev);
pm_runtime_disable(dev);
+probe_master_put:
+ spi_master_put(master);
return ret;
}
static int cqspi_remove(struct platform_device *pdev)
{
struct cqspi_st *cqspi = platform_get_drvdata(pdev);
- int i;
-
- for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
- if (cqspi->f_pdata[i].registered)
- mtd_device_unregister(>f_pdata[i].nor.mtd);
cqspi_controller_enable(cqspi, 0);
@@ -1462,17 +1368,15 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {
#endif
static const struct cqspi_driver_platdata cdns_qspi = {
- .hwcaps_mask = CQSPI_BASE_HWCAPS_MASK,
.quirks = CQSPI_DISABLE_DAC_MODE,
};
static const struct cqspi_driver_platdata k2g_qspi = {
- .hwcaps_mask = CQSPI_BASE_HWCAPS_MASK,
.quirks = CQSPI_NEEDS_WR_DELAY,
};
static const struct cqspi_driver_platdata am654_ospi = {
- .hwcaps_mask = CQSPI_BASE_HWCAPS_MASK | SNOR_HWCAPS_READ_1_1_8,
+ .hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
.quirks = CQSPI_NEEDS_WR_DELAY,
};
@@ -1511,3 +1415,5 @@ MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" CQSPI_NAME);
MODULE_AUTHOR("Ley Foon Tan ");
MODULE_AUTHOR("Graham Moore ");
+MODULE_AUTHOR("Vadivel Murugan R ");
+MODULE_AUTHOR("Vignesh Raghavendra ");
--
2.26.2
If driver fails to acquire DMA channel then don't initialize
rx_dma_complete struct as it won't be used.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Tudor Ambarus
---
drivers/mtd/spi-nor/controllers/cadence-quadspi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/spi-nor
les. This is in preparation to move to spi-mem framework
where flash geometry cannot be known.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Tudor Ambarus
---
drivers/mtd/spi-nor/controllers/cadence-quadspi.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-
Drop redundant WREN command in cqspi_erase() as SPI NOR core takes care
of sending WREN command before sending erase command.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Tudor Ambarus
---
drivers/mtd/spi-nor/controllers/cadence-quadspi.c | 5 -
1 file changed, 5 deletions(-)
diff
-by: Vignesh Raghavendra
Reviewed-by: Tudor Ambarus
---
.../mtd/spi-nor/controllers/cadence-quadspi.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/spi-nor/controllers/cadence-quadspi.c
b/drivers/mtd/spi-nor/controllers/cadence-quadspi.c
index
var Vadivel Murugan (2):
mtd: spi-nor: Convert cadence-quadspi to use spi-mem framework
spi: Move cadence-quadspi driver to drivers/spi/
Vignesh Raghavendra (6):
mtd: spi-nor: cadence-quadspi: Make driver independent of flash
geometry
mtd: spi-nor: cadence-quadspi: Provide a way to d
Make sure to undo the prior changes done by the driver when exiting due
to failure to acquire reset lines.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Tudor Ambarus
---
drivers/mtd/spi-nor/controllers/cadence-quadspi.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff
of sending WREN, there
is no need to configure these fields either.
Therefore drop these in preparation to move the driver to spi-mem
framework where flash geometry is not visible to controller driver.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Tudor Ambarus
---
.../mtd/spi-nor/controllers
Drop redundant WREN command in cqspi_erase() as SPI NOR core takes care
of sending WREN command before sending erase command.
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/spi-nor/controllers/cadence-quadspi.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/mtd/spi-nor
atic int cqspi_probe(struct platform_device *pdev)
probe_clk_failed:
pm_runtime_put_sync(dev);
pm_runtime_disable(dev);
+probe_master_put:
+ spi_master_put(master);
return ret;
}
static int cqspi_remove(struct platform_device *pdev)
{
struct cqspi_st *cqspi = platform_get_drvdata(pdev);
- int i;
-
- for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
- if (cqspi->f_pdata[i].registered)
- mtd_device_unregister(>f_pdata[i].nor.mtd);
cqspi_controller_enable(cqspi, 0);
@@ -1462,17 +1368,15 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {
#endif
static const struct cqspi_driver_platdata cdns_qspi = {
- .hwcaps_mask = CQSPI_BASE_HWCAPS_MASK,
.quirks = CQSPI_DISABLE_DAC_MODE,
};
static const struct cqspi_driver_platdata k2g_qspi = {
- .hwcaps_mask = CQSPI_BASE_HWCAPS_MASK,
.quirks = CQSPI_NEEDS_WR_DELAY,
};
static const struct cqspi_driver_platdata am654_ospi = {
- .hwcaps_mask = CQSPI_BASE_HWCAPS_MASK | SNOR_HWCAPS_READ_1_1_8,
+ .hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
.quirks = CQSPI_NEEDS_WR_DELAY,
};
@@ -1511,3 +1415,5 @@ MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" CQSPI_NAME);
MODULE_AUTHOR("Ley Foon Tan ");
MODULE_AUTHOR("Graham Moore ");
+MODULE_AUTHOR("Vadivel Murugan R ");
+MODULE_AUTHOR("Vignesh Raghavendra ");
--
2.26.2
les. This is in preparation to move to spi-mem framework
where flash geometry cannot be known.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Tudor Ambarus
---
drivers/mtd/spi-nor/controllers/cadence-quadspi.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-
of sending WREN, there
is no need to configure these fields either.
Therefore drop these in preparation to move the driver to spi-mem
framework where flash geometry is not visible to controller driver.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Tudor Ambarus
---
.../mtd/spi-nor/controllers
Make sure to undo the prior changes done by the driver when exiting due
to failure to acquire reset lines.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Tudor Ambarus
---
drivers/mtd/spi-nor/controllers/cadence-quadspi.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff
-by: Vignesh Raghavendra
---
.../mtd/spi-nor/controllers/cadence-quadspi.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/spi-nor/controllers/cadence-quadspi.c
b/drivers/mtd/spi-nor/controllers/cadence-quadspi.c
index 608ca657ff7f..0570ebca135a
From: Ramuthevar Vadivel Murugan
Now that cadence-quadspi has been converted to use spi-mem framework,
move it under drivers/spi/
Update license header to match SPI subsystem style
Signed-off-by: Ramuthevar Vadivel Murugan
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/spi-nor
If driver fails to acquire DMA channel then don't initialize
rx_dma_complete struct as it won't be used.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Tudor Ambarus
---
drivers/mtd/spi-nor/controllers/cadence-quadspi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/spi-nor
i-nor: Convert cadence-quadspi to use spi-mem framework
spi: Move cadence-quadspi driver to drivers/spi/
Vignesh Raghavendra (6):
mtd: spi-nor: cadence-quadspi: Make driver independent of flash
geometry
mtd: spi-nor: cadence-quadspi: Provide a way to disable DAC mode
mtd: spi-nor: cad
On 30/05/20 7:20 pm, tudor.amba...@microchip.com wrote:
> Hi, Vignesh,
>
> On Tuesday, May 26, 2020 12:36:03 PM EEST Vignesh Raghavendra wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
>> content is safe
>>
>> From: Ramuthev
On 28/05/20 4:12 pm, Serge Semin wrote:
[...]
>>> +
>>> +static map_word __xipram bt1_rom_dummy_read(struct map_info *map,
>>> + unsigned long ofs)
>>> +{
>>> + map_word ret;
>>> +
>>> + ret.x[0] = 0xFF;
>>> +
>>> + return ret;
>>> +}
>> Why define
On 18/05/20 11:29 pm, Daniel Walker wrote:
> This option currently doesn't work as expected. If the BIOS has this
> flash as read-only there is no way to change this thru the driver.
> There is a parameter which allows the flash to become writable with the
> "writable" option to the module, but
+Mika Westerberg original author of the driver
On 18/05/20 11:29 pm, Daniel Walker wrote:
> From: Bobby Liu
>
> How to use:
> append softwareseq=1 while probe the driver.
> example:
> modprobe intel-spi writeable=1 softwareseq=1
> it will let driver use software sequence to write register for
Hi,
On 21/05/20 10:56 am, Rayagonda Kokatanur wrote:
> Both w25q64 and s25fl064k nor flash support QUAD and DUAL read
> command, hence update the same in flash_info table.
>
I am guessing both modes were tested on some platform?
Could you add that info here?
> Signed-off-by: Rayagonda
Hi,
On 27/05/20 4:28 am, Serge Semin wrote:
> Baikal-T1 Boot Controller provides an access to a RO storages, which are
> physically mapped into the MMIO space. In particularly there are the
> Internal ROM embedded into the SoC with a pre-installed firmware,
> externally attached SPI flash (also
Hi,
On 28/05/20 2:28 am, kbuild test robot wrote:
> Hi Vignesh,
>
[...]
>
> In file included from include/linux/err.h:5,
> from include/linux/clk.h:12,
> from drivers/spi/spi-cadence-quadspi.c:9:
> include/linux/scatterlist.h: In function 'sg_set_buf':
> arch/xtensa/include/asm/page.h:193:9:
Hi,
On 22/05/20 10:23 am, Dinghao Liu wrote:
> When devm_clk_get() returns an error code, a pairing
> runtime PM usage counter decrement is needed to keep
> the counter balanced.
>
> Signed-off-by: Dinghao Liu
> ---
Thanks for the patch! But this fix is incomplete, I have posted
a more
Fix unwinding of pm_runtime changes when bailing out of driver probe due
to a failure and also on removal of driver.
Fixes: 6979e56cec97 ("scsi: ufs: Add driver for TI wrapper for Cadence UFS IP")
Reported-by: Dinghao Liu
Signed-off-by: Vignesh Raghavendra
---
drivers/scsi/ufs/ti-j
+ if (ret) {
+ dev_err(>dev, "failed to register SPI ctlr %d\n", ret);
+ goto probe_setup_failed;
+ }
+
+ return 0;
probe_setup_failed:
cqspi_controller_enable(cqspi, 0);
probe_reset_failed:
@@ -1412,11 +1314,6 @@ static int cqspi_probe(struct platform_device *pdev)
static int cqspi_remove(struct platform_device *pdev)
{
struct cqspi_st *cqspi = platform_get_drvdata(pdev);
- int i;
-
- for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
- if (cqspi->f_pdata[i].registered)
- mtd_device_unregister(>f_pdata[i].nor.mtd);
cqspi_controller_enable(cqspi, 0);
@@ -1459,17 +1356,15 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {
#endif
static const struct cqspi_driver_platdata cdns_qspi = {
- .hwcaps_mask = CQSPI_BASE_HWCAPS_MASK,
.quirks = CQSPI_DISABLE_DAC_MODE,
};
static const struct cqspi_driver_platdata k2g_qspi = {
- .hwcaps_mask = CQSPI_BASE_HWCAPS_MASK,
.quirks = CQSPI_NEEDS_WR_DELAY,
};
static const struct cqspi_driver_platdata am654_ospi = {
- .hwcaps_mask = CQSPI_BASE_HWCAPS_MASK | SNOR_HWCAPS_READ_1_1_8,
+ .hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
.quirks = CQSPI_NEEDS_WR_DELAY,
};
@@ -1508,3 +1403,5 @@ MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" CQSPI_NAME);
MODULE_AUTHOR("Ley Foon Tan ");
MODULE_AUTHOR("Graham Moore ");
+MODULE_AUTHOR("Vadivel Murugan R ");
+MODULE_AUTHOR("Vignesh Raghavendra ");
--
2.26.2
From: Ramuthevar Vadivel Murugan
Now that cadence-quadspi has been converted to use spi-mem framework,
move it under drivers/spi/
Update license header to match SPI subsystem style
Signed-off-by: Ramuthevar Vadivel Murugan
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/spi-nor
.
Ramuthevar Vadivel Murugan (2):
mtd: spi-nor: Convert cadence-quadspi to use spi-mem framework
spi: Move cadence-quadspi driver to drivers/spi/
Vignesh Raghavendra (4):
mtd: spi-nor: cadence-quadspi: Make driver independent of flash
geometry
mtd: spi-nor: cadence-quadspi: Provide a
les. This is in preparation to move to spi-mem framework
where flash geometry cannot be known.
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/spi-nor/controllers/cadence-quadspi.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/controllers/cadence-quadsp
If driver fails to acquire DMA channel then don't initialize
rx_dma_complete struct as it won't be used.
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/spi-nor/controllers/cadence-quadspi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/spi-nor/controllers/cadence-quadspi.c
of sending WREN, there
is no need to configure these fields either.
Therefore drop these in preparation to move the driver to spi-mem
framework where flash geometry is not visible to controller driver.
Signed-off-by: Vignesh Raghavendra
---
.../mtd/spi-nor/controllers/cadence-quadspi.c | 36
Make sure to undo the prior changes done by the driver when exiting due
to failure to acquire reset lines.
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/spi-nor/controllers/cadence-quadspi.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/spi-nor
On 09/05/20 12:24 am, Vignesh Raghavendra wrote:
> Cadence QSPI provides a way to automatically decode CS based on the
> offset accessed within memory map window. This feature cannot be
> supported in spi-mem framework as controller driver would not have
> access to flash geometr
On Thu, 7 May 2020 14:00:33 -0500, Gustavo A. R. Silva wrote:
> The current codebase makes use of the zero-length array language
> extension to the C90 standard, but the preferred mechanism to declare
> variable-length types such as these ones is a flexible array member[1][2],
> introduced in C99:
On 13/05/20 2:15 am, Rob Herring wrote:
> The ti,j721e-ufs schema is missing an 'additionalProperties: false'. Add
> that and and the missing assigned-clock properties.
>
> Cc: Vignesh Raghavendra
> Signed-off-by: Rob Herring
> ---
Acked-by: Vignesh Raghavendra
translation for the child ufs node is broken because
> 'ranges', '#address-cells', and '#size-cells' are missing from the
> schema.
>
> Cc: Vignesh Raghavendra
> Signed-off-by: Rob Herring
> ---
Acked-by: Vignesh Raghavendra
Regards
Vignesh
> Please ack, dependency for patch 5.
>
On 12/05/20 11:46 am, tudor.amba...@microchip.com wrote:
> Hi, Boris, Pratyush,
>
> I stripped case 2/, we'll not treat it for now.
>
> On Monday, May 11, 2020 12:27:12 PM EEST Boris Brezillon wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
>> content is
On 11/05/20 2:30 pm, tudor.amba...@microchip.com wrote:
> Hi, Pratyush, Boris,
>
> On Friday, April 24, 2020 9:43:54 PM EEST Pratyush Yadav wrote:
>> This series adds support for octal DTR flashes in the spi-nor framework,
>
> I'm still learning about this, but I can give you my 2 cents as of
From: Ramuthevar Vadivel Murugan
Now that cadence-quadspi has been converted to use spi-mem framework,
move it under drivers/spi/
Update license header to match SPI subsystem style
Signed-off-by: Ramuthevar Vadivel Murugan
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/spi-nor
If driver fails to acquire DMA channel then don't initialize
rx_dma_complete struct as it won't be used.
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/spi-nor/controllers/cadence-quadspi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/spi-nor/controllers/cadence-quadspi.c
that, this feature never worked in the driver (Direct/Indirect mode
accesses did not take into account size of flash on other CSs) and there
are no users of this feature in kernel. Therefore dropping this should
not cause a regression
Signed-off-by: Vignesh Raghavendra
---
.../mtd/spi-nor
eds cleanup):
https://github.com/r-vignesh/linux.git branch: cqspi-mig
Please use above branch to test the same.
Ramuthevar Vadivel Murugan (2):
mtd: spi-nor: Convert cadence-quadspi to use spi-mem framework
spi: Move cadence-quadspi driver to drivers/spi/
Vignesh Raghavendra (4):
mtd: spi-nor: cadenc
Make sure to undo the prior changes done by the driver when exiting due
to failure to acquire reset lines.
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/spi-nor/controllers/cadence-quadspi.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/spi-nor
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