Thanks for you, Shunyong.
Best Regards,
Wen He
> -Original Message-
> From: dmaengine-ow...@vger.kernel.org
> [mailto:dmaengine-ow...@vger.kernel.org] On Behalf Of Adam Wallis
> Sent: 2018年1月23日 22:32
> To: Yang Shunyong <shunyong.y...@hxt-semitech.com>;
> v
> -Original Message-
> From: Stephen Boyd
> Sent: 2019年8月20日 2:30
> To: devicet...@vger.kernel.org; linux-...@vger.kernel.org;
> linux-de...@linux.nxdi.nxp.com; linux-kernel@vger.kernel.org; Mark Rutland
> ; Michael Turquette ;
> Rob Herring ; Shawn Guo ; W
Add clock driver for QorIQ LS1028A Display output interfaces(LCD, DPHY),
as implemented in TSMC CLN28HPM PLL, this PLL supports the programmable
integer division and range of the display output pixel clock's 27-594MHz.
Signed-off-by: Wen He
---
change in v2:
- replace OF archticure
The LS1028A has a clock domain PXLCLK0 used for the Display output
interface in the display core, independent of the system bus frequency,
for flexible clock design. This display core has its own pixel clock.
This patch enable the pixel clock provider on the LS1028A.
Signed-off-by: Wen He
LS1028A has a clock domain PXLCLK0 used for provide pixel clocks to Display
output interface. Add a YAML schema for this.
Signed-off-by: Wen He
---
change in v2:
- Convert bindings to YAML format
.../devicetree/bindings/clock/fsl,plldig.yaml | 43 +++
1 file changed, 43
Add optional property node 'arm,malidp-arqos-value' for the Mali DP500.
This property describe the ARQoS levels of DP500's QoS signaling.
Signed-off-by: Wen He
---
change in v3:
- correction the describe of the node
Documentation/devicetree/bindings/display/arm,malidp.txt | 3 +++
1
> -Original Message-
> From: Stephen Boyd
> Sent: 2019年8月17日 1:47
> To: Mark Rutland ; Michael Turquette
> ; Rob Herring ; Shawn Guo
> ; Wen He ;
> devicet...@vger.kernel.org; linux-...@vger.kernel.org;
> linux-de...@linux.nxdi.nxp.com; linux-kernel@vger
> -Original Message-
> From: Stephen Boyd
> Sent: 2019年8月17日 1:46
> To: Mark Rutland ; Michael Turquette
> ; Rob Herring ; Shawn Guo
> ; Wen He ;
> devicet...@vger.kernel.org; linux-...@vger.kernel.org;
> linux-de...@linux.nxdi.nxp.com; linux-kernel@vger
> -Original Message-
> From: Shawn Guo
> Sent: 2019年8月19日 17:32
> To: Wen He
> Cc: Rob Herring ; Michael Turquette
> ; Stephen Boyd ; Mark
> Rutland ; devicet...@vger.kernel.org;
> linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; Leo Li
> ; liviu.du
> -Original Message-
> From: Stephen Boyd
> Sent: 2019年9月17日 4:27
> To: Mark Rutland ; Michael Turquette
> ; Rob Herring ; Wen He
> ; devicet...@vger.kernel.org; linux-...@vger.kernel.org;
> linux-de...@linux.nxdi.nxp.com; linux-kernel@vger.kernel.org
> Cc: Leo
> -Original Message-
> From: Stephen Boyd
> Sent: 2019年9月19日 1:01
> To: devicet...@vger.kernel.org; linux-...@vger.kernel.org;
> linux-de...@linux.nxdi.nxp.com; linux-kernel@vger.kernel.org; Mark Rutland
> ; Michael Turquette ;
> Rob Herring ; Wen He
> Cc: Leo
LS1028A has a clock domain PXLCLK0 used for provide pixel clocks to Display
output interface. Add a YAML schema for this.
Signed-off-by: Wen He
Reviewed-by: Rob Herring
---
.../devicetree/bindings/clock/fsl,plldig.yaml | 43 +++
1 file changed, 43 insertions(+)
create mode
Add clock driver for QorIQ LS1028A Display output interfaces(LCD, DPHY),
as implemented in TSMC CLN28HPM PLL, this PLL supports the programmable
integer division and range of the display output pixel clock's 27-594MHz.
Signed-off-by: Wen He
---
change in v5:
- update some code according
Thanks for you, Shunyong.
Best Regards,
Wen He
> -Original Message-
> From: dmaengine-ow...@vger.kernel.org
> [mailto:dmaengine-ow...@vger.kernel.org] On Behalf Of Adam Wallis
> Sent: 2018年1月23日 22:32
> To: Yang Shunyong ;
> vinod.k...@intel.com
> Cc: dan.j.will
This patch use the optional property node "arm,malidp-arqos-value" to
can be dynamic configure QoS signaling.
Signed-off-by: Wen He
---
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
b/
/2. APB slave interface clock(PCLK) and
Main processing clock(PCLK) both are tied to the same clock as ACLK.
This change followed the LS1028A Architecture Specification Manual.
Signed-off-by: Wen He
---
change in v2:
- add details commit description for this change.
- v1: Link
Update DT node name clock-controller to clock-display, also change
the property #clock-cells value to zero.
This update according the feedback of the Display output interface
clock driver upstream.
Link: https://lore.kernel.org/patchwork/patch/1113832/
Signed-off-by: Wen He
---
arch/arm64/boot
> -Original Message-
> From: Stephen Boyd
> Sent: 2019年8月14日 2:25
> To: Michael Turquette ; Wen He
> ; Leo Li ;
> linux-...@vger.kernel.org; linux-de...@linux.nxdi.nxp.com;
> linux-kernel@vger.kernel.org; liviu.du...@arm.com
> Cc: Wen He
> Subject: [EXT] Re:
> -Original Message-
> From: Stephen Boyd
> Sent: 2019年8月14日 2:30
> To: Mark Rutland ; Michael Turquette
> ; Rob Herring ; Shawn Guo
> ; Wen He ;
> devicet...@vger.kernel.org; linux-...@vger.kernel.org;
> linux-kernel@vger.kernel.org
> Cc: Leo Li ;
> -Original Message-
> From: Stephen Boyd
> Sent: 2019年8月15日 1:27
> To: linux-...@vger.kernel.org; linux-de...@linux.nxdi.nxp.com;
> linux-kernel@vger.kernel.org; liviu.du...@arm.com; Leo Li
> ; Michael Turquette ; Wen
> He
> Subject: RE: [EXT] Re: [v1 1/3]
> -Original Message-
> From: Stephen Boyd
> Sent: 2019年8月23日 9:27
> To: Mark Rutland ; Michael Turquette
> ; Rob Herring ; Wen He
> ; devicet...@vger.kernel.org; linux-...@vger.kernel.org;
> linux-de...@linux.nxdi.nxp.com; linux-kernel@vger.kernel.org
> Cc: Leo
LS1028A has a clock domain PXLCLK0 used for provide pixel clocks to Display
output interface. Add a YAML schema for this.
Signed-off-by: Wen He
Reviewed-by: Rob Herring
---
.../devicetree/bindings/clock/fsl,plldig.yaml | 43 +++
1 file changed, 43 insertions(+)
create mode
Add clock driver for QorIQ LS1028A Display output interfaces(LCD, DPHY),
as implemented in TSMC CLN28HPM PLL, this PLL supports the programmable
integer division and range of the display output pixel clock's 27-594MHz.
Signed-off-by: Wen He
---
change in v4:
- correction some code
Add clock driver for QorIQ LS1028A Display output interfaces(LCD, DPHY),
as implemented in TSMC CLN28HPM PLL, this PLL supports the programmable
integer division and range of the display output pixel clock's 27-594MHz.
Signed-off-by: Wen He
---
drivers/clk/Kconfig | 9 ++
drivers/clk
Add DT bindings documentmation for the Clock of the LS1028A Display
output interface.
Signed-off-by: Wen He
---
.../devicetree/bindings/clock/fsl,plldig.txt | 26 +++
1 file changed, 26 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/fsl,plldig.txt
The LS1028A has a clock domain PXLCLK0 used for the Display output
interface in the display core, independent of the system bus frequency,
for flexible clock design. This display core has its own pixel clock.
This patch enable the pixel clock provider on the LS1028A.
Signed-off-by: Wen He
LS1028A has a clock domain PXLCLK0 used for provide pixel clocks to Display
output interface. Add a YAML schema for this.
Signed-off-by: Wen He
Reviewed-by: Rob Herring
---
.../devicetree/bindings/clock/fsl,plldig.yaml | 43 +++
1 file changed, 43 insertions(+)
create mode
Add clock driver for QorIQ LS1028A Display output interfaces(LCD, DPHY),
as implemented in TSMC CLN28HPM PLL, this PLL supports the programmable
integer division and range of the display output pixel clock's 27-594MHz.
Signed-off-by: Wen He
---
change in v3:
- remove the OF dependency
Replace pclk/aclk/mclk fixed-clock clock provider with platform clockgen
pre-divider provider, those clocks should be driven by the CGA_PLL2/2.
More details please refer Reference Manual.
Signed-off-by: Wen He
---
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 17 ++---
1 file
> -Original Message-
> From: Shawn Guo
> Sent: 2019年10月7日 20:35
> To: Wen He
> Cc: linux-de...@linux.nxdi.nxp.com; Leo Li ; Rob Herring
> ; Mark Rutland ;
> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org;
> linux-arm-ker...@lists.infradead.org
>
> -Original Message-
> From: Shawn Guo
> Sent: 2019年10月14日 14:22
> To: Wen He
> Cc: linux-de...@linux.nxdi.nxp.com; Leo Li ; Rob Herring
> ; Mark Rutland ;
> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org;
> linux-arm-ker...@lists.infradead.org
> S
Update the property #clock-cells = <1> to #clock-cells = <0> of the
dpclk, since the Display output pixel clock driver provides single
clock output.
Signed-off-by: Wen He
---
change in v3:
- according the maintainer correction node name
- update the commit message
> -Original Message-
> From: Liviu Dudau
> Sent: 2019年9月5日 0:13
> To: Wen He
> Cc: dri-de...@lists.freedesktop.org; linux-kernel@vger.kernel.org;
> brian.star...@arm.com; airl...@linux.ie; dan...@ffwll.ch; Leo Li
>
> Subject: Re: [EXT] Re: [v2 1/3] drm/arm/
> -Original Message-
> From: Rob Herring
> Sent: 2019年6月14日 4:08
> To: Wen He
> Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> devicet...@vger.kernel.org; shawn...@kernel.org; Leo Li
>
> Subject: [EXT] Re: [v1 1/4] dt-bindings:
> -Original Message-
> From: Rob Herring
> Sent: 2019年6月19日 22:07
> To: Wen He
> Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> devicet...@vger.kernel.org; shawn...@kernel.org; Leo Li
>
> Subject: Re: [EXT] Re: [v1 1/4] dt-bindings:
> -Original Message-
> From: Wen He
> Sent: 2019年5月8日 17:42
> To: dri-de...@lists.freedesktop.org; p.za...@pengutronix.de
> Cc: Leo Li ; Wen He
> Subject: [v1] gpu: ipu-v3: allow to build with ARCH_LAYERSCAPE
>
> The new LS1028A DP driver code causes a link fa
The LS1028A has a LCD controller and Displayport interface that
connects to eDP and Displayport connectors on the LS1028A board.
This patch enables the LCD controller driver on the LS1028A.
Signed-off-by: Alison Wang
Signed-off-by: Wen He
Reviewed-by: Liviu Dudau
Reviewed-by: Rob Herring
This patch enables the HDP controller driver on the LS1028A.
Signed-off-by: Alison Wang
Signed-off-by: Wen He
---
.../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 25 +++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
b/arch/arm64
user can specify any combination of monitor supported
resoluions by written in the node 'resoluion'.
- By default, the edid function is not in use.
Signed-off-by: Alison Wang
Signed-off-by: Wen He
---
arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 12
1 file changed, 12
Add DT bindings documentmation for the HDP-TX PHY controller. The describes
which could be found on NXP Layerscape ls1028a platform.
Signed-off-by: Wen He
---
.../devicetree/bindings/display/fsl,hdp.txt | 56 +++
1 file changed, 56 insertions(+)
create mode 100644
user can specify any combination of monitor supported
resoluions by written in the node 'resoluion'.
- By default, the edid function is not in use.
Signed-off-by: Alison Wang
Signed-off-by: Wen He
---
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 12
1 file changed, 12
> -Original Message-
> From: Robin Murphy [mailto:robin.mur...@arm.com]
> Sent: 2019年5月16日 1:14
> To: Wen He ; dri-de...@lists.freedesktop.org;
> linux-kernel@vger.kernel.org; liviu.du...@arm.com
> Cc: Leo Li
> Subject: [EXT] Re: [v1] drm/arm/mali-dp: Disable checki
42 matches
Mail list logo
