[PATCH v5 0/5] support rockchip dwc3 driver

This series add support for rockchip dwc3 driver, and add additional optional properties for specific platforms (e.g., rockchip rk3399 platform). William Wu (5): usb: dwc3: of-simple: add compatible for rockchip rk3399 usb: dwc3: add dis_u2_freeclk_exists_quirk usb: dwc3: add

[PATCH v5 4/5] usb: dwc3: add dis_del_phy_power_chg_quirk

Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Signed-off-by: William Wu --- Changes in v5: - None Changes in v4: - rebase on top of balbi testing/next

[PATCH v5 3/5] usb: dwc3: add phyif_utmi_quirk

configuration value is fault, so we need to reconfigure it by software. And refer to the dwc3 databook, the GUSB2PHYCFG.USBTRDTIM must be set to the corresponding value according to the UTMI+ PHY interface. Signed-off-by: William Wu --- Changes in v5: - None Changes in v4: - rebase on top of balbi

[PATCH v5 2/5] usb: dwc3: add dis_u2_freeclk_exists_quirk

Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Signed-off-by: William Wu --- Changes in v5: - None Changes in v4: - rebase on top of balbi testing/next

[PATCH v5 1/5] usb: dwc3: of-simple: add compatible for rockchip rk3399

Rockchip platform merely enable usb3 clocks and populate its children. So we can use this generic glue layer to support Rockchip dwc3. Signed-off-by: William Wu --- Changes in v5: - change compatible from "rockchip,dwc3" to "rockchip,rk3399-dwc3" (Heiko) Changes in v4: -

[PATCH v5 5/5] usb: dwc3: rockchip: add devicetree bindings documentation

This patch adds the devicetree documentation required for Rockchip USB3.0 core wrapper consisting of USB3.0 IP from Synopsys. It supports DRD mode, and could operate in device mode (SS, HS, FS) and host mode (SS, HS, FS, LS). Signed-off-by: William Wu --- Changes in v5: - rename clock-names

Re: [PATCH v4 5/5] usb: dwc3: rockchip: add devicetree bindings documentation

Dear Heiko, On 06/17/2016 07:15 AM, Heiko Stübner wrote: Hi William, Am Donnerstag, 2. Juni 2016, 20:34:56 schrieb William Wu: This patch adds the devicetree documentation required for Rockchip USB3.0 core wrapper consisting of USB3.0 IP from Synopsys. It supports DRD mode, and could operate

Re: [PATCH v2 5/5] usb: dwc3: rockchip: add devicetree bindings documentation

Hi Felipe, On 05/24/2016 05:32 PM, Felipe Balbi wrote: Hi, William Wu writes: This patch documents the device tree documentation required for Rockchip USB3.0 core wrapper consist of USB3.0 IP from Synopsys. It could operate in device mode (SS, HS, FS) and host mode (SS, HS, FS, LS). Signed

Re: [PATCH v2 5/5] usb: dwc3: rockchip: add devicetree bindings documentation

Hi Felipe & Rob, On 05/25/2016 04:04 PM, Felipe Balbi wrote: Hi, William Wu writes: Hi Felipe, On 05/24/2016 05:32 PM, Felipe Balbi wrote: Hi, William Wu writes: This patch documents the device tree documentation required for Rockchip USB3.0 core wrapper consist of USB3.0 IP

[PATCH v3 4/5] usb: dwc3: add dis_del_phy_power_chg_quirk

Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Signed-off-by: William Wu --- Changes in v3: - None Changes in v2: - None Documentation/devicetree

[PATCH v3 3/5] usb: dwc3: add phyif_utmi_quirk

configuration value is fault, so we need to reconfigure it by software. And refer to the dwc3 databook, the GUSB2PHYCFG.USBTRDTIM must be set to the corresponding value according to the UTMI+ PHY interface. Signed-off-by: William Wu --- Changes in v3: - None Changes in v2: - add a quirk

[PATCH v3 1/5] usb: dwc3: of-simple: add compatible for rockchip

Rockchip platform merely enable usb3 clocks and populate its children. So we can use this generic glue layer to support Rockchip dwc3. Signed-off-by: William Wu --- Changes in v3: - None Changes in v2: - sort the list of_dwc3_simple_match (Doug) drivers/usb/dwc3/dwc3-of-simple.c | 1 + 1 file

[PATCH v3 2/5] usb: dwc3: add dis_u2_freeclk_exists_quirk

Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Signed-off-by: William Wu --- Changes in v3: - None Changes in v2: - None Documentation/devicetree

[PATCH v3 0/5] support rockchip dwc3 driver

This series add support for rockchip dwc3 driver, and add additional optional properties for specific platforms (e.g., rockchip platform). William Wu (5): usb: dwc3: of-simple: add compatible for rockchip usb: dwc3: add dis_u2_freeclk_exists_quirk usb: dwc3: add phyif_utmi_quirk usb: dwc3

[PATCH v3 5/5] usb: dwc3: rockchip: add devicetree bindings documentation

This patch documents the device tree documentation required for Rockchip USB3.0 core wrapper consist of USB3.0 IP from Synopsys. It could operate in device mode (SS, HS, FS) and host mode (SS, HS, FS, LS). Signed-off-by: William Wu --- Changes in v3: - add dwc3 address (Felipe) Changes in v2

Re: [PATCH v3 5/5] usb: dwc3: rockchip: add devicetree bindings documentation

Dear Sergei, On 05/27/2016 07:54 PM, Sergei Shtylyov wrote: Hello. On 5/27/2016 2:31 PM, William Wu wrote: This patch documents the device tree documentation required for Documents the documentation? :-) Ah, my commit log seems a little weird. I'll corrcet it next patch. Thanks

[PATCH v4 0/5] support rockchip dwc3 driver

This series add support for rockchip dwc3 driver, and add additional optional properties for specific platforms (e.g., rockchip rk3399 platform). William Wu (5): usb: dwc3: of-simple: add compatible for rockchip usb: dwc3: add dis_u2_freeclk_exists_quirk usb: dwc3: add phyif_utmi_quirk

[PATCH v4 4/5] usb: dwc3: add dis_del_phy_power_chg_quirk

Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Signed-off-by: William Wu --- Changes in v4: - rebase on top of balbi testing/next, remove pdata (balbi

[PATCH v4 2/5] usb: dwc3: add dis_u2_freeclk_exists_quirk

Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Signed-off-by: William Wu --- Changes in v4: - rebase on top of balbi testing/next, remove pdata (balbi

[PATCH v4 5/5] usb: dwc3: rockchip: add devicetree bindings documentation

This patch adds the devicetree documentation required for Rockchip USB3.0 core wrapper consisting of USB3.0 IP from Synopsys. It supports DRD mode, and could operate in device mode (SS, HS, FS) and host mode (SS, HS, FS, LS). Signed-off-by: William Wu --- Changes in v4: - modify commit log

[PATCH v4 1/5] usb: dwc3: of-simple: add compatible for rockchip

Rockchip platform merely enable usb3 clocks and populate its children. So we can use this generic glue layer to support Rockchip dwc3. Signed-off-by: William Wu --- Changes in v4: - None Changes in v3: - None Changes in v2: - sort the list of_dwc3_simple_match (Doug) drivers/usb/dwc3/dwc3

[PATCH v4 3/5] usb: dwc3: add phyif_utmi_quirk

configuration value is fault, so we need to reconfigure it by software. And refer to the dwc3 databook, the GUSB2PHYCFG.USBTRDTIM must be set to the corresponding value according to the UTMI+ PHY interface. Signed-off-by: William Wu --- Changes in v4: - rebase on top of balbi testing/next, remove

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