% speedup.
Signed-off-by: Yazen Ghannam yazen.ghan...@linaro.org
Acked-by: Steve Capper steve.cap...@linaro.org
Acked-by: Ard Biesheuvel ard.biesheu...@linaro.org
---
arch/arm64/crypto/Kconfig | 4 +
arch/arm64/crypto/Makefile | 4 +
arch/arm64/crypto/crc32-arm64.c | 274
+linux-arm-ker...@lists.infradead.org
On Wed, Nov 19, 2014 at 11:19 AM, Yazen Ghannam
yazen.ghan...@linaro.org wrote:
This module registers a crc32 algorithm and a crc32c algorithm
that use the optional CRC32 and CRC32C instructions in ARMv8.
Tested on AMD Seattle.
Improvement compared
Biesheuvel
ard.biesheu...@linaro.org wrote:
On 20 November 2014 15:22, Yazen Ghannam yazen.ghan...@linaro.org wrote:
+linux-arm-ker...@lists.infradead.org
On Wed, Nov 19, 2014 at 11:19 AM, Yazen Ghannam
yazen.ghan...@linaro.org wrote:
This module registers a crc32 algorithm and a crc32c
The Socket ID is ApicId[bits] on Fam17h systems.
Change substraction to logical AND when extracting socket_id
from c->apicid.
Signed-off-by: Yazen Ghannam <yazen.ghan...@amd.com>
---
arch/x86/kernel/cpu/amd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x
Socket ID is an unsigned value and starts at 0. Subtracting 1
from it is incorrect and the result will underflow if
socket_id=0.
Remove substraction when extracting socket_id from c->apicid.
Signed-off-by: Yazen Ghannam <yazen.ghan...@amd.com>
---
Link:
http://lkml.kernel.org/r/1472674
Fix an underflow bug with the current Fam17h LLC ID derivation by
simplifying the derivation, and also move it into amd_get_topology().
Signed-off-by: Yazen Ghannam <yazen.ghan...@amd.com>
Cc: sta...@vger.kernel.org # v4.6..
Fixes: 3849e91f571d ("x86/AMD: Fix last level cache topol
10h and 15h will have a Node ID of 0 which
will be the same as the phys_proc_id, so we don't need to check for
multiple nodes before using the node_id.
Signed-off-by: Yazen Ghannam <yazen.ghan...@amd.com>
---
arch/x86/kernel/cpu/amd.c | 32
1 file chang
-off-by: Yazen Ghannam <yazen.ghan...@amd.com>
Cc: <sta...@vger.kernel.org> # v4.4..
Fixes: 3849e91f571d ("x86/AMD: Fix last level cache topology for AMD Fam17h
systems")
---
arch/x86/kernel/cpu/amd.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/arc
> >
> > Argh, the macro should be adding the additional parentheses:
> >
> > #define HWID_MCATYPE(hwid, mcatype) (((hwid) << 16) | (mcatype))
> >
> > That should fix the issue too.
>
Yep, sure does.
> Patch please.
Will do.
Thanks,
Yazen
> static void get_smca_bank_info(unsigned int bank)
> {
> unsigned int i, hwid_mcatype, cpu = smp_processor_id();
> - struct smca_hwid_mcatype *type;
> + struct smca_hwid *s_hwid;
> u32 high, instance_id;
> - u16 hwid, mcatype;
>
> /* Collect bank_info using CPU 0
s Gleixner <t...@linutronix.de>
> Cc: Yazen Ghannam <yazen.ghan...@amd.com>
> ---
> Documentation/x86/topology.txt | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/Documentation/x86/topology.txt b/Documentation/x86/topology.txt
> index 06afac252
will be node_id for TOPOEXT systems.
Single node systems in families 10h and 15h will have a Node ID of 0 which
will be the same as the phys_proc_id, so we don't need to check for
multiple nodes before using the node_id.
Signed-off-by: Yazen Ghannam <yazen.ghan...@amd.com>
---
Link:
http://lkml.kern
bug and simplify the code by replacing the
current cpu_llc_id derivation with a right shift.
Signed-off-by: Yazen Ghannam <yazen.ghan...@amd.com>
Cc: <sta...@vger.kernel.org> # v4.4..
Fixes: 3849e91f571d ("x86/AMD: Fix last level cache topology for AMD Fam17h
systems
>> +/*
>> + * LLC is at the Core Complex level.
>> + * Core Complex Id is ApicId[3].
>> + */
>> +else if (c->x86 == 0x17)
>> +per_cpu(cpu_llc_id, cpu) = c->initial_apicid
>
> Call the struct simply smca_bank, it's instance ID can be simply ->id.
> Makes the code much more readable.
>
> Signed-off-by: Borislav Petkov <b...@suse.de>
Looks good to me.
Please add:
Tested-by: Yazen Ghannam <yazen.ghan...@amd.com>
Ditto for the others.
Thanks,
Yazen
>
> > The NODEID_MSR feature only applies to Fam10h in which case the llc is at
>
> s/llc/LLC (Last Level Cache/
>
> Let's try to have abbreviations written out in their first mention in the
> text.
>
Okay.
> > the node level.
> >
> > The TOPOEXT feature is used on families 15h, 16h and
>
> "... because then the LSBit will be the Core Complex ID."
>
Ack.
> > We can fix the underflow bug and simplify the code by replacing the
> > current cpu_llc_id derivation with a right shift.
> >
> > Signed-off-by: Yazen Ghannam <yazen.ghan...
ith was introduced by this commit:
>
> commit d12a969ebbfcfc25853c4147d42b388f758e8784
> Author: Yazen Ghannam <yazen.ghan...@amd.com>
> Date: Thu Nov 17 17:57:32 2016 -0500
>
> EDAC, amd64: Add Deferred Error type
>
> Currently, deferred errors are cl
On Thu, Dec 01, 2016 at 07:15:01PM +0100, Borislav Petkov wrote:
> On Thu, Dec 01, 2016 at 11:02:04AM -0500, Yazen Ghannam wrote:
> > A deferred error is an uncorrectable error whose handling can be
> > deferred, i.e. it's not urgent. This affects the system behavior, but
>
From: Yazen Ghannam <yazen.ghan...@amd.com>
We have support for the new SMCA MCA_DE{STAT,ADDR} registers in Linux. So
we've used these registers in place of MCA_{STATUS,ADDR} on SMCA systems.
However, the guidance for current implementations of SMCA is to continue
using MCA_{STATU
From: Yazen Ghannam <yazen.ghan...@amd.com>
Scalable MCA systems have a new MCA_CONFIG register that we use to
configure each bank. We currently use this when we set up thresholding.
However, this is logically separate.
Move setup of MCA_CONFIG into a separate function.
Signed-off-by:
looking at UMCs in case
the UMC instance IDs ever match up with other bank types.
Signed-off-by: Yazen Ghannam <yazen.ghan...@amd.com>
---
Link:
http://lkml.kernel.org/r/1486760120-60944-2-git-send-email-yazen.ghan...@amd.com
v1->v2:
- Redo commit message based on comments.
- Add UMC bank ty
From: Yazen Ghannam <yazen.ghan...@amd.com>
We should move away from using AMD-specific amd_get_nb_id() to find a node
ID and move toward using generic Linux methods. We can use cpu_to_node()
since NUMA should be working as expected on newly released Fam17h systems.
Replace call to amd_get
From: Yazen Ghannam <yazen.ghan...@amd.com>
Give Deferred errors an Action Optional severity on SMCA systems so that
the SRAO notifier block can potentially handle them.
Signed-off-by: Yazen Ghannam <yazen.ghan...@amd.com>
---
Link:
http://lkml.kernel.org/r/1486760120-60944-3-gi
From: Yazen Ghannam <yazen.ghan...@amd.com>
This set is based on an earlier 3 patch set.
Patch 1:
- Address comments by using cpu_to_node() when finding a node ID rather
than amd_get_nb_id().
Link:
http://lkml.kernel.org/r/1486760120-60944-1-git-send-email-yazen.ghan...@amd.com
Patch 2:
From: Yazen Ghannam <yazen.ghan...@amd.com>
Deferred errors on AMD systems may get an Action Optional severity with the
goal of being handled by the SRAO notifier block. However, the process of
determining if an address is usable is different between Intel and AMD. So
define vendor-sp
From: Yazen Ghannam <yazen.ghan...@amd.com>
MCA bank 3 is reserved on systems pre-Fam17h, so it didn't have a name.
However, MCA bank 3 is defined on Fam17h systems and can be accessed using
legacy MSRs. Without a name we get a stack trace on Fam17h systems when
trying to register sysfs
initialization will still happen after generic init.
Signed-off-by: Yazen Ghannam <yazen.ghan...@amd.com>
---
arch/x86/kernel/cpu/mcheck/mce.c | 27 ---
1 file changed, 20 insertions(+), 7 deletions(-)
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kern
From: Yazen Ghannam <yazen.ghan...@amd.com>
We have support for the new SMCA MCA_DE{STAT,ADDR} registers in Linux. So
we've used these registers in place of MCA_{STATUS,ADDR} on SMCA systems.
However, the guidance for current implementations of SMCA is to continue
using MCA_{STATU
From: Yazen Ghannam <yazen.ghan...@amd.com>
Scalable MCA systems have a new MCA_CONFIG register that we use to
configure each bank. We currently use this when we set up thresholding.
However, this is logically separate.
Group all SMCA-related initialization into a single, separate fu
From: Yazen Ghannam <yazen.ghan...@amd.com>
ACPI defines a number of instructions to use for triggering errors. However
we are currently removing the address resources from the trigger resources
for only the WRITE_REGISTER_VALUE instruction. This leads to a resource
conflict for any other
From: Yazen Ghannam <yazen.ghan...@amd.com>
Current SMCA implementations have the same banks on each CPU with the
non-core banks only visible to a "master thread" on each Die. Practically,
this means the smca_banks array, which describes the banks, only needs to
be populated
From: Yazen Ghannam <yazen.ghan...@amd.com>
The wrong value is being passed to our function to compute CS sizes which
results in the wrong size being computed.
Redo the printing function so that the correct values are computed and
printed.
Also, redo how we calculate the number of pages i
From: Yazen Ghannam <yazen.ghan...@amd.com>
We have support for the new SMCA MCA_DE{STAT,ADDR} registers in Linux. So
we've used these registers in place of MCA_{STATUS,ADDR} on SMCA systems.
However, the guidance for current implementations of SMCA is to continue
using MCA_{STATU
From: Yazen Ghannam <yazen.ghan...@amd.com>
Scalable MCA systems have a new MCA_CONFIG register that we use to
configure each bank. We currently use this when we set up thresholding.
However, this is logically separate.
Group all SMCA-related initialization into a single, separate fu
From: Yazen Ghannam <yazen.ghan...@amd.com>
AMD systems support the Monitor/Mwait instructions and these can be used
for ACPI C1 in the same way as on Intel systems, with appropriate BIOS
support.
Allow ffh_cstate_init() to succeed on AMD systems and make the Cstate
description vendor-ag
From: Yazen Ghannam <yazen.ghan...@amd.com>
Remove code that was used to decide whether to schedule work. The decision
to schedule work is made later, so this code is now only deciding if we
should save the error severity.
Save the severity since we have it, and let the notifier blocks
From: Yazen Ghannam <yazen.ghan...@amd.com>
Fix typo in "poison consumption" error description.
Signed-off-by: Yazen Ghannam <yazen.ghan...@amd.com>
---
drivers/edac/mce_amd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/edac/mce_amd.c b/
From: Yazen Ghannam <yazen.ghan...@amd.com>
The severity gives a hint as to how to handle the error. The notifier
blocks can then use the severity to decide on an action. It's not necessary
for machine_check_poll() to filter errors for the notifier chain, since
each block will check its o
From: Yazen Ghannam <yazen.ghan...@amd.com>
AMD systems support the Monitor/Mwait instructions and these can be used
for ACPI C1 in the same way as on Intel systems.
Three things are needed:
1) This patch.
2) BIOS that declares a C1 state in _CST to use FFH, with correct val
From: Yazen Ghannam <yazen.ghan...@amd.com>
The bootlog option is only disabled by default on AMD Fam10h and older
systems.
Update bootlog description to say this.
Change the family value to hex to avoid confusion.
Signed-off-by: Yazen Ghannam <yazen.ghan...@amd.com>
---
Docum
From: Yazen Ghannam <yazen.ghan...@amd.com>
The value of MCA_STATUS is used as the MSR when clearing MCA_STATUS.
This may cause the following warning:
unchecked MSR access error: WRMSR to 0x11b (tried to write 0x)
Call Trace:
? amd_threshold_interrupt+0x209
From: Yazen Ghannam <yazen.ghan...@amd.com>
In the amd_threshold_interrupt() handler, we loop through every possible
block in each bank and rediscover the block's address and if it's valid,
e.g. valid, counter present and not locked. However, we already have the
address saved in the thr
From: Yazen Ghannam <yazen.ghan...@amd.com>
There needs to be a list_head outside of a linked list in order to iterate
over it and have access to all its elements. This is because the
list_for_each* macros iterate starting from head->next rather than head.
Define a list_head for the
From: Yazen Ghannam <yazen.ghan...@amd.com>
In the amd_threshold_interrupt() handler, we loop through every possible
block in each bank and rediscover the block's address and if it's valid,
e.g. valid, counter present and not locked. However, we already have the
address saved in the thr
From: Yazen Ghannam <yazen.ghan...@amd.com>
AMD systems have non-core, shared MCA banks within a Die. These banks are
controlled by a master CPU per Die. If this CPU is offlined then all the
shared banks are disabled in addition to the CPU's core banks.
Also, Fam17h systems may have SMT e
From: Yazen Ghannam <yazen.ghan...@amd.com>
Our current AMD severity logic can possibly give MCE_AR_SEVERITY for
uncorrectable errors in kernel context. The current #MC handler only calls
memory_failure() on errors in user context, but older versions will call
memory_failure() unconditi
From: Yazen Ghannam <yazen.ghan...@amd.com>
ACPI defines a number of instructions to use for triggering errors. However
we are currently removing the address resources from the trigger resources
for only the WRITE_REGISTER_VALUE instruction. This leads to a resource
conflict for any other
From: Yazen Ghannam <yazen.ghan...@amd.com>
AMD systems may log Deferred errors. These are errors that are uncorrected
but which do not need immediate action. The MCA_STATUS[UC] bit may not be
set for Deferred errors.
Flag the error as not correctable when MCA_STATUS[Deferred] is set.
From: Yazen Ghannam <yazen.ghan...@amd.com>
The McaIntrCfg register at MSRC000_0410, previously known as CU_DEFER_ERR,
is used on SMCA systems to set the LVT offset for the Threshold and
Deferred error interrupts.
This register was used on non-SMCA systems to also set the Deferred
interrup
From: Yazen Ghannam <yazen.ghan...@amd.com>
[Upstream commit d65dfc81bb3894fdb68cbc74bbf5fb48d2354071]
The AMD severity grading function was introduced in kernel 4.1. The
current logic can possibly give MCE_AR_SEVERITY for uncorrectable
errors in kernel context. The system may then get
From: Yazen Ghannam <yazen.ghan...@amd.com>
The AMD severity grading function was introduced in v4.1 and has remained
logically unchanged with the exception of a separate SMCA severity grading
function for SMCA systems. The current logic can possibly give
MCE_AR_SEVERITY for uncorrectable
From: Yazen Ghannam <yazen.ghan...@amd.com>
Change the err_ctx type to "enum context" to match the type passed in.
Suggested-by: Borislav Petkov <b...@suse.de>
Signed-off-by: Yazen Ghannam <yazen.ghan...@amd.com>
---
arch/x86/kernel/cpu/mcheck/mce-severity.c | 2 +-
From: Yazen Ghannam <yazen.ghan...@amd.com>
Scalable MCA systems have various types of banks. The bank's type can
determine how we handle errors from it. For example, if a bank represents
a UMC then we will need to convert its address from a normalized address
to a system physical address
From: Yazen Ghannam <yazen.ghan...@amd.com>
The MCA_STATUS[ErrorCodeExt] field is very bank type specific. We currently
check if the ErrorCodeExt value is 0x0 or 0x8 in mce_is_memory_error(), but
we don't check the bank. This means that we could flag non-memory errors as
memory errors.
W
From: Yazen Ghannam <yazen.ghan...@amd.com>
The MCA_STATUS[ErrorCodeExt] field is very bank type specific. We currently
check if the ErrorCodeExt value is 0x0 or 0x8 in mce_is_memory_error(), but
we don't check the bank. This means that we could flag non-memory errors as
memory errors.
W
From: Yazen Ghannam <yazen.ghan...@amd.com>
Scalable MCA systems have various types of banks. The bank's type can
determine how we handle errors from it. For example, if a bank represents
a UMC then we will need to convert its address from a normalized address
to a system physical address
From: Yazen Ghannam <yazen.ghan...@amd.com>
Currently, aer_service_init() checks if AER is available and that
Firmware First handling is not enabled. The _OSC request for AER is
not taken into account when deciding to enable AER in Linux.
We should check that the _OSC control for AER
From: Yazen Ghannam <yazen.ghan...@amd.com>
Currently, aer_service_init() checks if AER is available and that
Firmware First handling is not enabled. The _OSC request for AER is not
taken into account when deciding to enable AER in Linux.
>From ACPI 6.2 Section 6.2.11.3, &qu
From: Yazen Ghannam <yazen.ghan...@amd.com>
The acpi_idle driver will default to ACPI_CSTATE_HALT for C1 if a _CST
object for C1 is not defined. However, the description will not be set,
so users will see "" when reading the description from sysfs.
Set the C1 state description
From: Yazen Ghannam <yazen.ghan...@amd.com>
Currently, bank 4 is reserved on Fam17h, so we chose not to initialize
bank 4 in the smca_banks array. This means that when we check if a bank
is initialized, like during boot or resume, we will see that bank 4 is
not initialized and try to init
From: Yazen Ghannam <yazen.ghan...@amd.com>
The block address is saved after the block is initialized when
threshold_init_device() is called.
Use the saved block address, if available, rather than trying to
rediscover it.
We can avoid some *on_cpu() calls in the init path that will cause
From: Yazen Ghannam <yazen.ghan...@amd.com>
Pass the bank number to smca_get_bank_type() since that's all we need.
Also, we should compare the bank number to the size of the smca_banks
array not the number of bank types. Bank types are reused for multiple
banks, so the number of typ
From: Yazen Ghannam <yazen.ghan...@amd.com>
Pass the bank number to smca_get_bank_type() since that's all we need.
Also, we should compare the bank number to the size of the smca_banks
array not the number of bank types. Bank types are reused for multiple
banks, so the number of typ
From: Yazen Ghannam <yazen.ghan...@amd.com>
The block address is saved after the block is initialized when
threshold_init_device() is called.
Use the saved block address, if available, rather than trying to
rediscover it.
This will avoid a call trace, when resuming from suspen
From: Yazen Ghannam <yazen.ghan...@amd.com>
Currently, bank 4 is reserved on Fam17h, so we chose not to initialize
bank 4 in the smca_banks array. This means that when we check if a bank
is initialized, like during boot or resume, we will see that bank 4 is
not initialized and try to init
From: Yazen Ghannam <yazen.ghan...@amd.com>
Carve out the SMCA code in get_block_address() into a separate helper
function.
No functional change.
Signed-off-by: Yazen Ghannam <yazen.ghan...@amd.com>
---
v1->v2:
* New in this series.
arch/x86/kernel/cpu/mcheck
From: Yazen Ghannam <yazen.ghan...@amd.com>
For easier handling, match the known IA32/X64 error structure GUIDs to
enums.
Also, print out the name of the matching Error Structure Type.
GUIDs taken from UEFI 2.7 section N.2.4.2.1 IA32/X64 Processor Error
Information Structure.
Cc
From: Yazen Ghannam <yazen.ghan...@amd.com>
Based on UEFI 2.7 Table 255. Processor Error Record, the "Local APIC_ID"
field is 8 bytes but Linux defines this field as 1 byte.
Fix this in the struct cper_sec_proc_ia definition.
Cc: <sta...@vger.kernel.org> # 4.16.x
Signed
From: Yazen Ghannam <yazen.ghan...@amd.com>
Print the fields of the IA32/X64 Context Information structure.
Print the "Register Array" as raw values. Some context types are defined
in the UEFI spec, so more detailed decoded may be added in the future.
Based on UEFI 2.7 sectio
From: Yazen Ghannam <yazen.ghan...@amd.com>
Print the common fields of the Cache, TLB, and Bus check structures.The
fields of these three check types are the same except for a few more
fields in the Bus check structure. The remaining Bus check structure
fields will be decoded in a following
From: Yazen Ghannam <yazen.ghan...@amd.com>
This series adds decoding for the IA32/X64 Common Platform Error Record.
Patch 1 fixes the IA32/X64 Processor Error Section definition to match
the UEFI spec.
Patches 2-8 add the new decoding. The patches incrementally add the
decoding startin
From: Yazen Ghannam <yazen.ghan...@amd.com>
Print the fields in the IA32/X64 Processor Error Info Structure.
Based on UEFI 2.7 Table 256. IA32/X64 Processor Error Information
Structure.
Cc: <sta...@vger.kernel.org> # 4.16.x
Signed-off-by: Yazen Ghannam <yazen.ghan...@amd.co
From: Yazen Ghannam <yazen.ghan...@amd.com>
The "Participation Type", "Time Out", and "Address Space" fields are
unique to the IA32/X64 Bus Check structure. Print these fields.
Based on UEFI 2.7 Table 259. IA32/X64 Bus Check Structure
Cc: <sta...@vger.ke
From: Yazen Ghannam <yazen.ghan...@amd.com>
The IA32/X64 MS Check structure varies from the other Check structures
in the the bit positions of its fields, and it includes an additional
"Error Type" field.
Decode the MS Check structure in a separate function.
Based on UEFI 2.7
From: Yazen Ghannam <yazen.ghan...@amd.com>
Recognize the IA32/X64 Processor Error Section.
Do the section decoding in a new "cper-x86.c" file and add this to the
Makefile depending on a new "UEFI_CPER_X86" config option.
Print the Local APIC ID and CPUID info from
From: Yazen Ghannam <yazen.ghan...@amd.com>
Print the fields of the IA32/X64 Context Information structure.
Print the "Register Array" as raw values. Some context types are defined
in the UEFI spec, so more detailed decoded may be added in the future.
Based on UEFI 2.7 sectio
From: Yazen Ghannam <yazen.ghan...@amd.com>
Print the common fields of the Cache, TLB, and Bus check structures.The
fields of these three check types are the same except for a few more
fields in the Bus check structure. The remaining Bus check structure
fields will be decoded in a following
From: Yazen Ghannam <yazen.ghan...@amd.com>
Print the fields in the IA32/X64 Processor Error Info Structure.
Based on UEFI 2.7 Table 256. IA32/X64 Processor Error Information
Structure.
Signed-off-by: Yazen Ghannam <yazen.ghan...@amd.com>
---
Link:
https://lkml.kernel.org/r/2018022
From: Yazen Ghannam <yazen.ghan...@amd.com>
Based on UEFI 2.7 Table 255. Processor Error Record, the "Local APIC_ID"
field is 8 bytes but Linux defines this field as 1 byte.
Fix this in the struct cper_sec_proc_ia definition.
Signed-off-by: Yazen Ghannam <yazen.ghan...@amd.c
From: Yazen Ghannam <yazen.ghan...@amd.com>
Recognize the IA32/X64 Processor Error Section.
Do the section decoding in a new "cper-x86.c" file and add this to the
Makefile depending on a new "UEFI_CPER_X86" config option.
Print the Local APIC ID and CPUID info from
From: Yazen Ghannam <yazen.ghan...@amd.com>
For easier handling, match the known IA32/X64 error structure GUIDs to
enums.
Also, print out the name of the matching Error Structure Type.
GUIDs taken from UEFI 2.7 section N.2.4.2.1 IA32/X64 Processor Error
Information Structure.
Sign
From: Yazen Ghannam <yazen.ghan...@amd.com>
The "Participation Type", "Time Out", and "Address Space" fields are
unique to the IA32/X64 Bus Check structure. Print these fields.
Based on UEFI 2.7 Table 259. IA32/X64 Bus Check Structure
Signed-off-by:
From: Yazen Ghannam <yazen.ghan...@amd.com>
The IA32/X64 MS Check structure varies from the other Check structures
in the the bit positions of its fields, and it includes an additional
"Error Type" field.
Decode the MS Check structure in a separate function.
Based on UEFI 2.7
From: Yazen Ghannam <yazen.ghan...@amd.com>
This series adds decoding for the IA32/X64 Common Platform Error Record.
Patch 1 fixes the IA32/X64 Processor Error Section definition to match
the UEFI spec.
Patches 2-8 add the new decoding. The patches incrementally add the
decoding startin
From: Yazen Ghannam
Linux reads MCG_CAP[Count] to find the number of MCA banks visible to a
CPU. Currently, this is assumed to be the same for all CPUs and a
warning is shown if there is a difference. The number of banks is
overwritten with the MCG_CAP[Count] value of each following CPU
From: Yazen Ghannam
During mce_threshold_create_device() data structures are allocated for
each CPUs MCA banks and thresholding blocks. These data structures are
used to save information related to AMD's MCA Error Thresholding
feature. The structures are used in the thresholding interrupt
From: Yazen Ghannam
If threshold_init_device() fails then per_cpu(threshold_banks) will be
deallocated. The thresholding interrupt handler will still be active, so
it's possible to get a NULL pointer dereference if a THR interrupt
happens and any of the structures are NULL.
Exit the handler
From: Yazen Ghannam <yazen.ghan...@amd.com>
Based on UEFI 2.7 Table 252. Processor Error Record, the "Local APIC_ID"
field is 8 bytes but Linux defines this field as 1 byte.
Fix this in the struct cper_sec_proc_ia definition.
Signed-off-by: Yazen Ghannam <yazen.ghan...@amd.c
From: Yazen Ghannam <yazen.ghan...@amd.com>
Print the fields of the IA32/X64 Context Information structure.
Print the "Register Array" as raw values. Some context types are defined
in the UEFI spec, so more detailed decoded may be added in the future.
Based on UEFI 2.7 sectio
From: Yazen Ghannam <yazen.ghan...@amd.com>
The "Participation Type", "Time Out", and "Address Space" fields are
unique to the IA32/X64 Bus Check structure. Print these fields.
Based on UEFI 2.7 Table 256. IA32/X64 Bus Check Structure
Signed-off-by:
From: Yazen Ghannam <yazen.ghan...@amd.com>
The IA32/X64 MS Check structure varies from the other Check structures
in the the bit positions of its fields, and it includes an additional
"Error Type" field.
Decode the MS Check structure in a separate function.
Based on UEFI 2.7
From: Yazen Ghannam <yazen.ghan...@amd.com>
For easier handling, match the known IA32/X64 error structure GUIDs to
enums.
Also, print out the name of the matching Error Structure Type.
Only print the GUID for unknown types.
GUIDs taken from UEFI 2.7 section N.2.4.2.1 IA32/X64 Processor
From: Yazen Ghannam <yazen.ghan...@amd.com>
Recognize the IA32/X64 Processor Error Section.
Do the section decoding in a new "cper-x86.c" file and add this to the
Makefile depending on a new "UEFI_CPER_X86" config option.
Print the Local APIC ID and CPUID info from
From: Yazen Ghannam <yazen.ghan...@amd.com>
This series adds decoding for the IA32/X64 Common Platform Error Record.
Patch 1 fixes the IA32/X64 Processor Error Section definition to match
the UEFI spec.
Patches 2-8 add the new decoding. The patches incrementally add the
decoding startin
From: Yazen Ghannam <yazen.ghan...@amd.com>
Print the common fields of the Cache, TLB, and Bus check structures.The
fields of these three check types are the same except for a few more
fields in the Bus check structure. The remaining Bus check structure
fields will be decoded in a following
From: Yazen Ghannam <yazen.ghan...@amd.com>
Print the fields in the IA32/X64 Processor Error Info Structure.
Based on UEFI 2.7 Table 253. IA32/X64 Processor Error Information
Structure.
Signed-off-by: Yazen Ghannam <yazen.ghan...@amd.com>
---
Link:
https://lkml.kernel.org/r/20180226
From: Yazen Ghannam <yazen.ghan...@amd.com>
The Intel SDM and AMD APM both state that the contents of the MCA_ADDR
register should be saved if MCA_STATUS[ADDRV] is set. The same applies
to MCA_MISC and MCA_SYND (on SMCA systems) and their respective valid
bits.
However, the Fam17h Pro
From: Yazen Ghannam <yazen.ghan...@amd.com>
This reverts commit 4b1e84276a6172980c5bf39aa091ba13e90d6dad.
Software uses the valid bits to decide if the values can be used for
further processing or other actions. So setting the valid bits will have
software act on values that it sho
From: Yazen Ghannam <yazen.ghan...@amd.com>
For easier handling, match the known IA32/X64 error structure GUIDs to
enums.
Also, print out the name of the matching Error Structure Type.
Only print the GUID for unknown types.
GUIDs taken from UEFI 2.7 section N.2.4.2.1 IA32/X64 Processor
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