Current code will exist when read eMMC 5.0, add support for it
Signed-off-by: Zhang Yi yix.x.zh...@gmail.com
---
mmc_cmds.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/mmc_cmds.c b/mmc_cmds.c
index b8afa74..5edf42b 100644
--- a/mmc_cmds.c
+++ b/mmc_cmds.c
@@ -722,6 +722,9 @@ int
, and the 3rd thread block on
the 2nd mutex.
5. The 1st thread unlock the 2nd mutex, the 3rd thread cannot take
the 2nd mutex, and may block forever.
Signed-off-by: Zhang Yi zhang.y...@zte.com.cn
Tested-by: Ma Chenggong ma.chengg...@zte.com.cn
Reviewed-by: Jiang Biao jiang.bi...@zte.com.cn
diff -uprN
Hi all,
I reworked the patch base on your advices。
For the line-wrapped bug before, I use this mailbox to send the mail .
Signed-off-by: Zhang Yi zhang.y...@zte.com.cnTested-by: Ma Chenggong
ma.chengg...@zte.com.cnReviewed-by: Liu Dong
liu.do...@zte.com.cnReviewed-by: Cui Yunfeng
cui.yunf
Hi all,
I reworked the patch base on your advices.
For the line-wrapped bug before, I use this mailbox to send the mail .
Signed-off-by: Zhang Yi zhang.y...@zte.com.cn
Tested-by: Ma Chenggong ma.chengg...@zte.com.cn
Reviewed-by: Liu Dong liu.do...@zte.com.cn
Reviewed-by: Cui Yunfeng cui.yunf
. The 1st thread create the 3rd thread, and the 3rd thread block on the 2nd
mutex.
5. The 1st thread unlock the 2nd mutex, the 3rd thread can not take the 2nd
mutex, and
may block forever.
Signed-off-by: Zhang Yi zhang.y...@zte.com.cn
Tested-by: Ma Chenggong ma.chengg...@zte.com.cn
Reviewed
, and the 3rd thread block on
the 2nd mutex.
5. The 1st thread unlock the 2nd mutex, the 3rd thread cannot take
the 2nd mutex, and may block forever.
Signed-off-by: Zhang Yi zhang.y...@zte.com.cn
Tested-by: Ma Chenggong ma.chengg...@zte.com.cn
Reviewed-by: Thomas Gleixner t...@linutronix.de
Reviewed
From: Zhang Yi Z <yi.z.zh...@linux.intel.com>
Adds reporting SPP capability from VMX Procbased MSR, according to
the definition of hardware spec, bit 32 is the control of the SPP
capability.
Defined X86_FEATURE_SPP under intel X86 VT-x CPU features.
Defined the X86_VMX_FEATURE_PROC_CTL
From: Zhang Yi Z <yi.z.zh...@linux.intel.com>
Signed-off-by: Zhang Yi Z <yi.z.zh...@linux.intel.com>
Signed-off-by: He Chen <he.c...@linux.intel.com>
---
Documentation/virtual/kvm/spp_design_kvm.txt | 272 +++
1 file changed, 272 insertions(+)
From: Zhang Yi Z <yi.z.zh...@linux.intel.com>
The hardware uses the guest-physical address and bits 11:7 of the
address accessed to lookup the SPPT to fetch a write permission bit for
the 128 byte wide sub-page region being accessed within the 4K
guest-physical page. If the sub-page region
From: Zhang Yi Z <yi.z.zh...@linux.intel.com>
If the sub-page write permission VM-execution control is set,
treatment of write accesses to guest-physical accesses
depends on the state of the accumulated write-access bit (position 1)
and sub-page permission bit (position 61) in the EPT leaf
From: Zhang Yi Z <yi.z.zh...@linux.intel.com>
We introduced 2 ioctls to let user application to set/get subpage write
protection bitmap per gfn, each gfn corresponds to a bitmap.
The user application, qemu, or some other security control daemon. will
set the protection bitmap via this
From: Zhang Yi Z <yi.z.zh...@linux.intel.com>
Add new secondary processor-based VM-execution control bit which
defined as "sub-page write permission", same as VMX Procbased MSR,
bit 23 is the enable bit of SPP.
Also we introduced a enable_ept_spp parameter to control the
SP
From: Zhang Yi Z <yi.z.zh...@linux.intel.com>
SPPT has 4-level paging structure that is similar to EPT
except L1E.
The sub-page permission table is referenced via a 64-bit control field
called Sub-Page Permission Table Pointer (SPPTP) which contains a
4K-aligned physical address. the
From: Zhang Yi Z <yi.z.zh...@linux.intel.com>
A control bit in EPT leaf paging-structure entries is defined as
“Sub-Page Permission” (SPP bit). The bit position is 61
While hardware walking the SPP page table, If the sub-page
region write permission bit is set, the write is allowed
From: Zhang Yi Z <yi.z.zh...@linux.intel.com>
Accesses using guest-physical addresses may cause SPP-induced VM exits
due to an SPPT misconfiguration or an
SPPT miss. The basic VM exit reason code reported for SPP-induced VM
exits is 66.
An SPPT misconfiguration VM exit occurs when, in the
From: Zhang Yi Z <yi.z.zh...@linux.intel.com>
Hi All,
Here is a patch-series which adding EPT-Based Sub-page Write Protection
Support. You can get It's software developer manuals from:
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-exte
From: Zhang Yi Z <yi.z.zh...@linux.intel.com>
We also should setup SPP page structure while we catch
a SPP miss, some case, such as hotplug vcpu, should update
the SPP page table in SPP miss handler.
Signed-off-by: Zhang Yi Z <yi.z.zh...@linux.intel.com>
---
arch/x86/include/asm/kvm
; or fs_dax pages to kvm for DIMM/NVDIMM backend). Together with the type
>> MEMORY_DEVICE_FS_DAX, we can use is_dax_page() to differentiate the pages
>> is DAX device memory or not.
>>
>> Signed-off-by: Zhang Yi
>> Signed-off-by: Zhang Yu
>> ---
>> incl
Thanks Paolo, let's wait Jan 's comments.
Thank you, Paolo.
Regards
Yi
On 2018年07月20日 16:32, Paolo Bonzini wrote:
> On 20/07/2018 16:11, Zhang,Yi wrote:
>> Added Jiang,Dave,
>>
>> Ping for further review, comments.
> I need an Acked-by from the MM people to merge th
MEMORY_DEVICE_FS_DAX, we can use is_dax_page() to differentiate the pages
is DAX device memory or not.
Signed-off-by: Zhang Yi
Signed-off-by: Zhang Yu
---
include/linux/mm.h | 12
1 file changed, 12 insertions(+)
diff --git a/include/linux/mm.h b/include/linux/mm.h
index 6e19265..9f0f690
for MEMORY_DEVICE_DEV_DAX memory type in comment block
*Add is_dax_page() in mm.h to differentiate the pages is from DAX device.
*Remove the function kvm_is_nd_pfn().
Zhang Yi (4):
kvm: remove redundant reserved page check
mm: introduce memory type MEMORY_DEVICE_DEV_DAX
mm: add a function
operations will be missed due to this
mistreatment to pmem pages. For example, a page may not have chance to
be unpinned for KVM guest(in kvm_release_pfn_clean); not able to be
marked as dirty/accessed(in kvm_set_pfn_dirty/accessed) etc
Signed-off-by: Zhang Yi
---
virt/kvm/kvm_main.c | 8 ++--
1
f
enabling.
Now SPP is active when the "Sub-page Write Protection"
in Secondary VM-Execution Control is set and enable the kernel
parameter by "spp=on".
Signed-off-by: Zhang Yi
Signed-off-by: He Chen
---
arch/x86/include/asm/vmx.h | 1 +
arch/x86/kvm/vmx.c | 15 ++
i-th 128 byte sub-page region. |
| 1+2i | Reserved (0). |
Note: `0<=i<=31`
Chang logs:
V2 - V1:
1. Rebased to 4.20-rc1
2. Move VMCS change to a separated patch.
3. Code refine and Bug fix
Zhang Yi (11):
Documentatio
Signed-off-by: Zhang Yi
---
Documentation/virtual/kvm/spp_design_kvm.txt | 275 +++
1 file changed, 275 insertions(+)
create mode 100644 Documentation/virtual/kvm/spp_design_kvm.txt
diff --git a/Documentation/virtual/kvm/spp_design_kvm.txt
b/Documentation/virtual/kvm
initialization. and free at mmu page free.
Same as EPT page table, We initialized the SPPT,
and write the SPPT point into VMCS field.
Also we added a mmu page role type spp to distinguish it is a spp page
or a EPT page.
Signed-off-by: Zhang Yi
Signed-off-by: He Chen
---
arch/x86/include/asm/kvm_host.h | 4
Same as EPT page table, We initialized the SPPT,
and write the SPPT point into VMCS field.
Signed-off-by: Zhang Yi
---
arch/x86/include/asm/vmx.h | 2 ++
arch/x86/kvm/vmx.c | 17 +
2 files changed, 19 insertions(+)
diff --git a/arch/x86/include/asm/vmx.h b/arch/x86
SPP capability by this MSR.
Signed-off-by: Zhang Yi
Signed-off-by: He Chen
---
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/kernel/cpu/intel.c| 4
2 files changed, 5 insertions(+)
diff --git a/arch/x86/include/asm/cpufeatures.h
b/arch/x86/include/asm/cpufeatures.h
index
kvm_set_subpage.
Signed-off-by: Zhang Yi
---
arch/x86/kvm/mmu.c | 100 +
1 file changed, 100 insertions(+)
diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index b1773c6..d512125 100644
--- a/arch/x86/kvm/mmu.c
+++ b/arch/x86/kvm/mmu.c
@@ -1668,6
and SPPT misses can occur only due to an attempt
to write memory with a guest-physical address.
Signed-off-by: Zhang Yi
Signed-off-by: He Chen
---
arch/x86/include/asm/vmx.h | 7 +++
arch/x86/include/uapi/asm/vmx.h | 2 ++
arch/x86/kvm/vmx.c | 45
{
__u64 base_gfn;
__u64 npages;
/* sub-page write-access bitmap array */
__u32 access_map[SUBPAGE_MAX_BITMAP];
}sp;
kvm_vm_ioctl(s, KVM_SUBPAGES_SET_ACCESS, )
kvm_vm_ioctl(s, KVM_SUBPAGES_GET_ACCESS, )
Signed-off-by: Zhang Yi
Signed-off-by: He Chen
---
arch/x86/include
violation.
we need peek this case in EPT violation handler, and trigger
a user-space exit, return the write protected address(GPA)
to user(qemu).
Signed-off-by: Zhang Yi
Signed-off-by: He Chen
---
arch/x86/kvm/mmu.c | 19 +++
arch/x86/kvm/mmu.h | 1 +
include/uapi/linux
it could be divided to 32 x 128 sub-pages.
Signed-off-by: Zhang Yi
---
arch/x86/include/asm/kvm_host.h | 4 ++
arch/x86/kvm/mmu.c | 123 +++-
2 files changed, 125 insertions(+), 2 deletions(-)
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86
We also should setup SPP page structure while we catch
a SPP miss, some case, such as hotplug vcpu, should update
the SPP page table in SPP miss handler.
Signed-off-by: Zhang Yi
---
arch/x86/include/asm/kvm_host.h | 2 ++
arch/x86/kvm/mmu.c | 12
arch/x86/kvm/vmx.c
, and the 3rd thread block on
the 2nd mutex.
5. The 1st thread unlock the 2nd mutex, the 3rd thread cannot take
the 2nd mutex, and may block forever.
Signed-off-by: Zhang Yi
Tested-by: Ma Chenggong
Reviewed-by: Jiang Biao
diff -uprN linux-3.10-rc7.org/include/linux/hugetlb.h
linux-3.10-rc7/include
, and the 3rd thread block on
the 2nd mutex.
5. The 1st thread unlock the 2nd mutex, the 3rd thread cannot take
the 2nd mutex, and may block forever.
Signed-off-by: Zhang Yi
Tested-by: Ma Chenggong
Reviewed-by: Thomas Gleixner
Reviewed-by: Darren Hart
Reviewed-by: Dave Hansen
Reviewed-by: Mel
> -Original Message-
> From: Thomas Gleixner [mailto:t...@linutronix.de]
> Sent: Saturday, April 27, 2013 2:26 AM
> To: Zhang Yi
> Cc: linux-kernel@vger.kernel.org; 'Peter Zijlstra'; 'Darren Hart'; 'Ingo
> Molnar'; 'Dave Hansen';
zhang.y...@zte.com.cn;
> wet...@
It is OK that I send the mail to myself , but there are some wrong while
sending to you.
Ignore this mail ,please, I will check and send it again.
> -Original Message-
> From: Zhang Yi [mailto:wet...@gmail.com]
> Sent: Tuesday, May 07, 2013 8:24 PM
> To: 'Thomas Gleixner'
, the 3rd thread cannot take
the 2nd mutex, and may block forever.
Signed-off-by: Zhang Yi
Tested-by: Ma Chenggong
Reviewed-by: Thomas Gleixner
Reviewed-by: Darren Hart
Reviewed-by: Dave Hansen
Reviewed-by: Liu Dong
Reviewed-by: Cui Yunfeng
Reviewed-by: Lu Zhongjun
Reviewed-by: Jiang Biao
Current code will exist when read eMMC 5.0, add support for it
Signed-off-by: Zhang Yi
---
mmc_cmds.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/mmc_cmds.c b/mmc_cmds.c
index b8afa74..5edf42b 100644
--- a/mmc_cmds.c
+++ b/mmc_cmds.c
@@ -722,6 +722,9 @@ int do_read_extcsd(int
Hi all,
I reworked the patch base on your advices。
For the line-wrapped bug before, I use this mailbox to send the mail .
Signed-off-by: Zhang Yi Tested-by: Ma Chenggong
Reviewed-by: Liu Dong
Reviewed-by: Cui Yunfeng
Reviewed-by: Lu Zhongjun
Reviewed-by: Jiang Biao
diff -uprN orig
Hi all,
I reworked the patch base on your advices.
For the line-wrapped bug before, I use this mailbox to send the mail .
Signed-off-by: Zhang Yi
Tested-by: Ma Chenggong
Reviewed-by: Liu Dong
Reviewed-by: Cui Yunfeng
Reviewed-by: Lu Zhongjun
Reviewed-by: Jiang Biao
diff -uprN orig
k on the 1st
mutex.
4. The 1st thread create the 3rd thread, and the 3rd thread block on the 2nd
mutex.
5. The 1st thread unlock the 2nd mutex, the 3rd thread can not take the 2nd
mutex, and
may block forever.
Signed-off-by: Zhang Yi
Tested-by: Ma Chenggong
Reviewed-by: Liu Dong
Reviewed-b
From: Zhang Yi Z
Hi All,
Here is a patch-series which adding EPT-Based Sub-page Write Protection
Support. You can get It's software developer manuals from:
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
From: Zhang Yi Z
Signed-off-by: Zhang Yi Z
Signed-off-by: He Chen
---
Documentation/virtual/kvm/spp_design_kvm.txt | 272 +++
1 file changed, 272 insertions(+)
create mode 100644 Documentation/virtual/kvm/spp_design_kvm.txt
diff --git a/Documentation/virtual/kvm
From: Zhang Yi Z
Adds reporting SPP capability from VMX Procbased MSR, according to
the definition of hardware spec, bit 32 is the control of the SPP
capability.
Defined X86_FEATURE_SPP under intel X86 VT-x CPU features.
Defined the X86_VMX_FEATURE_PROC_CTLS2_SPP in intel VMX MSR indicated
From: Zhang Yi Z
Add new secondary processor-based VM-execution control bit which
defined as "sub-page write permission", same as VMX Procbased MSR,
bit 23 is the enable bit of SPP.
Also we introduced a enable_ept_spp parameter to control the
SPP is ON/OFF, Set the default is
From: Zhang Yi Z
SPPT has 4-level paging structure that is similar to EPT
except L1E.
The sub-page permission table is referenced via a 64-bit control field
called Sub-Page Permission Table Pointer (SPPTP) which contains a
4K-aligned physical address. the index and encoding for this VMCS field
From: Zhang Yi Z
A control bit in EPT leaf paging-structure entries is defined as
“Sub-Page Permission” (SPP bit). The bit position is 61
While hardware walking the SPP page table, If the sub-page
region write permission bit is set, the write is allowed,
else the write is disallowed and results
From: Zhang Yi Z
Accesses using guest-physical addresses may cause SPP-induced VM exits
due to an SPPT misconfiguration or an
SPPT miss. The basic VM exit reason code reported for SPP-induced VM
exits is 66.
An SPPT misconfiguration VM exit occurs when, in the course of
translating a guest
From: Zhang Yi Z
We introduced 2 ioctls to let user application to set/get subpage write
protection bitmap per gfn, each gfn corresponds to a bitmap.
The user application, qemu, or some other security control daemon. will
set the protection bitmap via this ioctl.
the API defined as:
struct
From: Zhang Yi Z
If the sub-page write permission VM-execution control is set,
treatment of write accesses to guest-physical accesses
depends on the state of the accumulated write-access bit (position 1)
and sub-page permission bit (position 61) in the EPT leaf paging-structure.
Software
From: Zhang Yi Z
The hardware uses the guest-physical address and bits 11:7 of the
address accessed to lookup the SPPT to fetch a write permission bit for
the 128 byte wide sub-page region being accessed within the 4K
guest-physical page. If the sub-page region write permission bit is set
From: Zhang Yi Z
We also should setup SPP page structure while we catch
a SPP miss, some case, such as hotplug vcpu, should update
the SPP page table in SPP miss handler.
Signed-off-by: Zhang Yi Z
---
arch/x86/include/asm/kvm_host.h | 2 ++
arch/x86/kvm/mmu.c | 12
for MEMORY_DEVICE_DEV_DAX memory type in comment block
*Add is_dax_page() in mm.h to differentiate the pages is from DAX device.
*Remove the function kvm_is_nd_pfn().
Zhang Yi (4):
kvm: remove redundant reserved page check
mm: introduce memory type MEMORY_DEVICE_DEV_DAX
mm: add a function
MEMORY_DEVICE_FS_DAX, we can use is_dax_page() to differentiate the pages
is DAX device memory or not.
Signed-off-by: Zhang Yi
Signed-off-by: Zhang Yu
---
include/linux/mm.h | 12
1 file changed, 12 insertions(+)
diff --git a/include/linux/mm.h b/include/linux/mm.h
index 6e19265..9f0f690
operations will be missed due to this
mistreatment to pmem pages. For example, a page may not have chance to
be unpinned for KVM guest(in kvm_release_pfn_clean); not able to be
marked as dirty/accessed(in kvm_set_pfn_dirty/accessed) etc
Signed-off-by: Zhang Yi
---
virt/kvm/kvm_main.c | 8 ++--
1
i-th 128 byte sub-page region. |
| 1+2i | Reserved (0). |
Note: `0<=i<=31`
Chang logs:
V2 - V1:
1. Rebased to 4.20-rc1
2. Move VMCS change to a separated patch.
3. Code refine and Bug fix
Zhang Yi (11):
Documentatio
f
enabling.
Now SPP is active when the "Sub-page Write Protection"
in Secondary VM-Execution Control is set and enable the kernel
parameter by "spp=on".
Signed-off-by: Zhang Yi
Signed-off-by: He Chen
---
arch/x86/include/asm/vmx.h | 1 +
arch/x86/kvm/vmx.c | 15 ++
Signed-off-by: Zhang Yi
---
Documentation/virtual/kvm/spp_design_kvm.txt | 275 +++
1 file changed, 275 insertions(+)
create mode 100644 Documentation/virtual/kvm/spp_design_kvm.txt
diff --git a/Documentation/virtual/kvm/spp_design_kvm.txt
b/Documentation/virtual/kvm
initialization. and free at mmu page free.
Same as EPT page table, We initialized the SPPT,
and write the SPPT point into VMCS field.
Also we added a mmu page role type spp to distinguish it is a spp page
or a EPT page.
Signed-off-by: Zhang Yi
Signed-off-by: He Chen
---
arch/x86/include/asm/kvm_host.h | 4
Same as EPT page table, We initialized the SPPT,
and write the SPPT point into VMCS field.
Signed-off-by: Zhang Yi
---
arch/x86/include/asm/vmx.h | 2 ++
arch/x86/kvm/vmx.c | 17 +
2 files changed, 19 insertions(+)
diff --git a/arch/x86/include/asm/vmx.h b/arch/x86
SPP capability by this MSR.
Signed-off-by: Zhang Yi
Signed-off-by: He Chen
---
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/kernel/cpu/intel.c| 4
2 files changed, 5 insertions(+)
diff --git a/arch/x86/include/asm/cpufeatures.h
b/arch/x86/include/asm/cpufeatures.h
index
kvm_set_subpage.
Signed-off-by: Zhang Yi
---
arch/x86/kvm/mmu.c | 100 +
1 file changed, 100 insertions(+)
diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index b1773c6..d512125 100644
--- a/arch/x86/kvm/mmu.c
+++ b/arch/x86/kvm/mmu.c
@@ -1668,6
and SPPT misses can occur only due to an attempt
to write memory with a guest-physical address.
Signed-off-by: Zhang Yi
Signed-off-by: He Chen
---
arch/x86/include/asm/vmx.h | 7 +++
arch/x86/include/uapi/asm/vmx.h | 2 ++
arch/x86/kvm/vmx.c | 45
{
__u64 base_gfn;
__u64 npages;
/* sub-page write-access bitmap array */
__u32 access_map[SUBPAGE_MAX_BITMAP];
}sp;
kvm_vm_ioctl(s, KVM_SUBPAGES_SET_ACCESS, )
kvm_vm_ioctl(s, KVM_SUBPAGES_GET_ACCESS, )
Signed-off-by: Zhang Yi
Signed-off-by: He Chen
---
arch/x86/include
violation.
we need peek this case in EPT violation handler, and trigger
a user-space exit, return the write protected address(GPA)
to user(qemu).
Signed-off-by: Zhang Yi
Signed-off-by: He Chen
---
arch/x86/kvm/mmu.c | 19 +++
arch/x86/kvm/mmu.h | 1 +
include/uapi/linux
it could be divided to 32 x 128 sub-pages.
Signed-off-by: Zhang Yi
---
arch/x86/include/asm/kvm_host.h | 4 ++
arch/x86/kvm/mmu.c | 123 +++-
2 files changed, 125 insertions(+), 2 deletions(-)
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86
We also should setup SPP page structure while we catch
a SPP miss, some case, such as hotplug vcpu, should update
the SPP page table in SPP miss handler.
Signed-off-by: Zhang Yi
---
arch/x86/include/asm/kvm_host.h | 2 ++
arch/x86/kvm/mmu.c | 12
arch/x86/kvm/vmx.c
; or fs_dax pages to kvm for DIMM/NVDIMM backend). Together with the type
>> MEMORY_DEVICE_FS_DAX, we can use is_dax_page() to differentiate the pages
>> is DAX device memory or not.
>>
>> Signed-off-by: Zhang Yi
>> Signed-off-by: Zhang Yu
>> ---
>> incl
Thanks Paolo, let's wait Jan 's comments.
Thank you, Paolo.
Regards
Yi
On 2018年07月20日 16:32, Paolo Bonzini wrote:
> On 20/07/2018 16:11, Zhang,Yi wrote:
>> Added Jiang,Dave,
>>
>> Ping for further review, comments.
> I need an Acked-by from the MM people to merge th
On 2021/3/22 11:36, Theodore Ts'o wrote:
> On Mon, Mar 22, 2021 at 11:05:13AM +0800, Gao Xiang wrote:
>> I think the legel name would be "Zhang Yi" (family name goes first [1])
>> according to
>> The Chinese phonetic alphabet spelling rules for Chinese names [2].
Commit-ID: 13d60f4b6ab5b702dc8d2ee20999f98a93728aec
Gitweb: http://git.kernel.org/tip/13d60f4b6ab5b702dc8d2ee20999f98a93728aec
Author: Zhang Yi wet...@gmail.com
AuthorDate: Tue, 25 Jun 2013 21:19:31 +0800
Committer: Thomas Gleixner t...@linutronix.de
CommitDate: Tue, 25 Jun 2013 23:11:19
Commit-ID: 13d60f4b6ab5b702dc8d2ee20999f98a93728aec
Gitweb: http://git.kernel.org/tip/13d60f4b6ab5b702dc8d2ee20999f98a93728aec
Author: Zhang Yi
AuthorDate: Tue, 25 Jun 2013 21:19:31 +0800
Committer: Thomas Gleixner
CommitDate: Tue, 25 Jun 2013 23:11:19 +0200
futex: Take hugepages
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