[PATCHv4 3/9] arm64: dts: ls1043a: fix typo of MSI compatible string

From: Minghuan Lian "1" should be replaced by "l". This is a typo. The patch is to fix it. Signed-off-by: Minghuan Lian Signed-off-by: Hou Zhiqiang --- v4-v1: - None arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 6

[PATCHv4 7/9] irqchip/ls-scfg-msi: add LS1046a MSI support

From: Minghuan Lian LS1046a includes 4 MSIRs, each MSIR is assigned a dedicate GIC SPI interrupt and provides 32 MSI interrupts. Compared to previous MSI, LS1046a's IBS(interrupt bit select) shift is changed to 2 and total MSI interrupt number is changed to 128. The patch

[PATCHv4 5/9] arm64: dts: ls1043a: share all MSIs

From: Minghuan Lian In order to maximize the use of MSI, a PCIe controller will share all MSI controllers. The patch changes "msi-parent" to refer to all MSI controller dts nodes. Signed-off-by: Minghuan Lian Signed-off-by: Hou Zhiqiang

[PATCHv4 2/9] arm: dts: ls1021a: fix typo of MSI compatible string

From: Minghuan Lian "1" should be replaced by "l". This is a typo. The patch is to fix it. Signed-off-by: Minghuan Lian Signed-off-by: Hou Zhiqiang --- v4-v1: - None arch/arm/boot/dts/ls1021a.dtsi | 4 ++-- 1 file changed,

[PATCHv4 9/9] irqchip/ls-scfg-msi: add MSI affinity support

From: Minghuan Lian For LS1046a and LS1043a v1.1, the MSI controller has 4 MSIRs and 4 GIC SPI interrupts which can be associated with different Core. So we can support affinity to improve the performance. The MSI message data is a byte for Layerscape MSI. 76 5 4

[PATCHv4 6/9] arm64: dts: ls1046a: add MSI dts node

From: Minghuan Lian LS1046a includes 3 MSI controllers. Each controller supports 128 interrupts. Signed-off-by: Minghuan Lian Acked-by: Rob Herring Signed-off-by: Hou Zhiqiang --- v4: - rebased code v3-v2:

[PATCHv4 4/9] arm: dts: ls1021a: share all MSIs

From: Minghuan Lian In order to maximize the use of MSI, a PCIe controller will share all MSI controllers. The patch changes msi-parent to refer to all MSI controller dts nodes. Signed-off-by: Minghuan Lian Signed-off-by: Hou Zhiqiang

[PATCHv4 8/9] irqchip/ls-scfg-msi: add LS1043a v1.1 MSI support

From: Minghuan Lian A MSI controller of LS1043a v1.0 only includes one MSIR and is assigned one GIC interrupt. In order to support affinity, LS1043a v1.1 MSI is assigned 4 MSIRs and 4 GIC interrupts. But the MSIR has the different offset and only supports 8 MSIs. The bits

[PATCHv4 1/9] irqchip/ls-scfg-msi: fix typo of MSI compatible strings

From: Minghuan Lian The patch is to fix typo of the Layerscape SCFG MSI dts compatible strings. "1" is replaced by "l". Signed-off-by: Minghuan Lian Acked-by: Rob Herring Signed-off-by: Hou Zhiqiang ---

[PATCH 1/5] irqchip/ls-scfg-msi: add LS1012a MSI support

From: Hou Zhiqiang The ls1012a implement only 1 msi controller, and it is the same as ls1043a. Signed-off-by: Hou Zhiqiang --- .../devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt | 1 + drivers/irqchip/irq-ls-scfg-msi.c

[PATCH 5/5] arm64: dts: ls1046a: add PCIe controller DT nodes

From: Hou Zhiqiang LS1046a implements 3 PCIe 3.0 controllers. Signed-off-by: Hou Zhiqiang --- arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 75 ++ 1 file changed, 75 insertions(+) diff --git

[PATCH 2/5] arm64: dts: ls1012a: Add MSI controller DT node

From: Hou Zhiqiang Add MSI controller node for ls1012a platform. Signed-off-by: Hou Zhiqiang --- arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi

[PATCH 0/5] arm64: add ls1012a and ls1046a pcie support

From: Hou Zhiqiang This patch set adds ls1012a MSI and PCIe support, including driver and device tree nodes. The ls1046a's MSI support patch and PCIe driver patch has been applied, so only adds the PCIe device tree nodes. Hou Zhiqiang (5): irqchip/ls-scfg-msi: add

[PATCH 3/5] PCI: layerscape: Add support for ls1012a

From: Hou Zhiqiang Signed-off-by: Hou Zhiqiang --- Documentation/devicetree/bindings/pci/layerscape-pci.txt | 1 + drivers/pci/dwc/pci-layerscape.c | 1 + 2 files changed, 2 insertions(+) diff --git

[PATCH 4/5] arm64: dts: ls1012a: Add PCIe controller DT node

From: Hou Zhiqiang Add PCIe controller node for ls1012a platform. Signed-off-by: Hou Zhiqiang --- arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 24 1 file changed, 24 insertions(+) diff --git

[PATCH 2/2] pci/layerscape: change the default error response behavior

From: Minghuan Lian By default, when the PCIe controller experiences an erroneous completion from an external completer for its outbound non-posted request, it always sends an OKAY response to the device's internal AXI slave system interface. However, such default system

[PATCH 0/2] PCI: layerscape: add fixes for layerscape-pcie errata

From: Hou Zhiqiang The [1/2] is to fix layerscape PCIe MSI/MSI-X capability errata. The [2/2] is to change the default AXI system error response behavior for PCI Express outbound non-posted requests. Hou Zhiqiang (1): PCI: Disable MSI for Freescale PCIe RC mode Minghuan

[PATCH 1/2] PCI: Disable MSI for Freescale PCIe RC mode

From: Hou Zhiqiang The Freescale PCIe controller advertises the MSI/MSI-X capability in both RC and Endpoint mode, but in RC mode it doesn't support MSI/MSI-X by it self, it can only transfer MSI/MSI-X from downstream devices. So add this quirk to prevent use of MSI/MSI-X

[PATCHv2 2/2] pci/layerscape: change the default error response behavior

From: Minghuan Lian By default, when the PCIe controller experiences an erroneous completion from an external completer for its outbound non-posted request, it always sends an OKAY response to the device's internal AXI slave system interface. However, such default system

[PATCHv2 1/2] PCI: Disable MSI for Freescale PCIe RC mode

From: Hou Zhiqiang The Freescale PCIe controller advertises the MSI/MSI-X capability in both RC and Endpoint mode, but in RC mode it doesn't support MSI/MSI-X by itself, it can only transfer MSI/MSI-X from downstream devices. So add this quirk to prevent use of MSI/MSI-X in

[PATCHv2 0/2] PCI: layerscape: add fixes for layerscape-pcie errata

From: Hou Zhiqiang The [1/2] is to fix layerscape PCIe MSI/MSI-X capability errata. The [2/2] is to change the default AXI system error response behavior for PCI Express outbound non-posted requests. Hou Zhiqiang (1): PCI: Disable MSI for Freescale PCIe RC mode Minghuan

[PATCHv2 0/3] arm64: dts: ls1012a: add the DTS node for DSPI support

From: Hou Zhiqiang Corrected the subject for 3/5 patch v1. Yuan Yao (3): arm64: dts: ls1012a: add the DTS node for DSPI support Documentation: fsl: dspi: Add fsl,ls1012a-dspi compatible string Documentation: dt: mtd: add sst25wf040b and en25s64 to the SPI NOR

[PATCHv2 2/3] Documentation: fsl: dspi: Add fsl,ls1012a-dspi compatible string

From: Yuan Yao new compatible string: "fsl,ls1012a-dspi". Signed-off-by: Yuan Yao Signed-off-by: Hou Zhiqiang Acked-by: Rob Herring --- V2: - No change Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt | 1 +

[PATCHv2 1/3] arm64: dts: ls1012a: add the DTS node for DSPI support

From: Yuan Yao Signed-off-by: Yuan Yao Signed-off-by: Hou Zhiqiang --- V2: - No change arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts | 33 +++ arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi| 13 +

[PATCHv2 3/3] Documentation: dt: mtd: add sst25wf040b and en25s64 to the SPI NOR support list

From: Yuan Yao The chip sst25wf040b and en25s64 are compatible with SPI NOR flash. Signed-off-by: Yuan Yao Signed-off-by: Hou Zhiqiang Acked-by: Rob Herring --- V2: - Corrected the subject.

[PATCH 1/2] mtd: spi-nor: add a API to restore the addressing mode

From: Hou Zhiqiang It's better to restore the addressing mode of the SPI flash whenever remove the driver or reboot the system. Signed-off-by: Hou Zhiqiang --- drivers/mtd/spi-nor/spi-nor.c | 8 include/linux/mtd/spi-nor.h | 1 + 2 files

[PATCH 0/2] mtd: m25p80: restore the addressing mode when stop using the flash

From: Hou Zhiqiang To be compatible with legacy device, reset the addressing mode to the default mode. Such as Freescale eSPI boot, it copies the images from SPI flash without firing a reset signal previously, so the reboot command will fail without reseting the addressing

[PATCH 2/2] mtd: m25p80: restore the addressing mode when stop using the flash

From: Hou Zhiqiang Add .shutdown function to restore the addressing mode in reboot process, and add the same operation to the .remove function. Signed-off-by: Hou Zhiqiang --- drivers/mtd/devices/m25p80.c | 8 1 file changed, 8

[PATCHv2 0/2] mtd: m25p80: restore the addressing mode when stop using the flash

From: Hou Zhiqiang To be compatible with legacy device, reset the addressing mode to the default mode. Such as Freescale eSPI boot, it copies the images from SPI flash without firing a reset signal previously, so the reboot command will fail without reseting the addressing

[PATCHv2 1/2] mtd: spi-nor: add an API to restore the status of SPI flash chip

From: Hou Zhiqiang Add this API to restore the status of SPI flash chip to the default such as addressing mode, whenever detach the driver from device or reboot the system. Signed-off-by: Hou Zhiqiang --- V2: - Changed the API name and added the

[PATCHv2 2/2] mtd: m25p80: restore the status of SPI flash when stop using it

From: Hou Zhiqiang Implement .shutdown function to restore the status in reboot process, and add the same operation to the .remove function. Signed-off-by: Hou Zhiqiang --- V2: - Changed code format slightly. drivers/mtd/devices/m25p80.c | 9

[PATCHv3 2/2] mtd: m25p80: restore the status of SPI flash when exiting

From: Hou Zhiqiang Restore the status to be compatible with legacy devices. Take Freescale eSPI boot for example, it copies (in 3 Byte addressing mode) the RCW and bootloader images from SPI flash without firing a reset signal previously, so the reboot command will fail

[PATCHv3 0/2] mtd: m25p80: restore the addressing mode when exiting

From: Hou Zhiqiang Restore the status to be compatible with legacy devices. Take Freescale eSPI boot for example, it copies (in 3 Byte addressing mode) the RCW and bootloader images from SPI flash without firing a reset signal previously, so the reboot command will fail

[PATCHv3 1/2] mtd: spi-nor: add an API to restore the status of SPI flash chip

From: Hou Zhiqiang Add this API to restore the status of SPI flash chip to the default such as addressing mode, whenever detach the driver from device or reboot the system. Signed-off-by: Hou Zhiqiang --- V3: - no change.

[PATCH 0/2] arm64: dts: Add ls1088a DSPI device tree nodes

From: Hou Zhiqiang LS1088A reuse LS2085A DSPI driver, this patchset just adds device tree nodes and adds compatible entry to documentation. Hou Zhiqiang (2): arm64: dts: ls1088a: add DT nodes for DSPI support Documentation: fsl: dspi: Add a compatible string for

[PATCH 2/2] Documentation: fsl: dspi: Add a compatible string for ls1088a DSPI

From: Hou Zhiqiang Add a new compatible string "fsl,ls1088a-dspi". Signed-off-by: Hou Zhiqiang --- Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt | 1 + 1 file changed, 1 insertion(+) diff --git

[PATCH 1/2] arm64: dts: ls1088a: add DT nodes for DSPI support

From: Hou Zhiqiang Signed-off-by: Hou Zhiqiang --- arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts | 28 +++ arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi| 13 +++ 2 files changed, 41 insertions(+) diff --git

[PATCH 1/4] doc/layerscape-pci: update the PCIe compatible strings

From: Hou Zhiqiang The pcie compatible string for LS1043A was lost, so add it. Signed-off-by: Hou Zhiqiang --- Documentation/devicetree/bindings/pci/layerscape-pci.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt

[PATCH 0/4] dts/layerscape-pci: removed unsuitable compatible string

From: Hou Zhiqiang Removed the compatible string "snps,dw-pcie" from FSL layerscape-pci compatible string list. Hou Zhiqiang (4): doc/layerscape-pci: update the PCIe compatible strings doc/layerscape-pci: removed unsuitable compatible string dts/arm/ls1021a: Clean PCIe controller

[PATCH 2/4] doc/layerscape-pci: removed unsuitable compatible string

From: Hou Zhiqiang Removed the compatible string "snps,dw-pcie", it is for the reference platform driver for PCI RC IP Protoyping Kits based on the ARC SDP, so it is not suitable for all platform with designware PCIe controller, and platform vendors have themselves' drivers. The compatible

[PATCH 3/4] dts/arm/ls1021a: Clean PCIe controller compatible strings

From: Hou Zhiqiang Removed the wrong compatible string "snps,dw-pcie", in case match incorrect driver. Signed-off-by: Hou Zhiqiang --- arch/arm/boot/dts/ls1021a.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/ls1021a.dtsi

[PATCH 4/4] dts/arm64/layerscape: Clean PCIe controller compatible strings

From: Hou Zhiqiang Removed the wrong compatible string "snps,dw-pcie", in case match incorrect driver. Signed-off-by: Hou Zhiqiang --- arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 6 +++---

[PATCHv2 0/3] arm64: dts: ls1012a: add the DTS node for DSPI support

From: Hou Zhiqiang Corrected the subject for 3/5 patch v1. Yuan Yao (3): arm64: dts: ls1012a: add the DTS node for DSPI support Documentation: fsl: dspi: Add fsl,ls1012a-dspi compatible string Documentation: dt: mtd: add sst25wf040b and en25s64 to the SPI NOR support list

[PATCHv2 2/3] Documentation: fsl: dspi: Add fsl,ls1012a-dspi compatible string

From: Yuan Yao new compatible string: "fsl,ls1012a-dspi". Signed-off-by: Yuan Yao Signed-off-by: Hou Zhiqiang Acked-by: Rob Herring --- V2: - No change Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt | 1 + 1 file changed, 1 insertion(+) diff --git

[PATCHv2 1/3] arm64: dts: ls1012a: add the DTS node for DSPI support

From: Yuan Yao Signed-off-by: Yuan Yao Signed-off-by: Hou Zhiqiang --- V2: - No change arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts | 33 +++ arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi| 13 + 2 files changed, 46 insertions(+) diff --git

[PATCHv2 3/3] Documentation: dt: mtd: add sst25wf040b and en25s64 to the SPI NOR support list

From: Yuan Yao The chip sst25wf040b and en25s64 are compatible with SPI NOR flash. Signed-off-by: Yuan Yao Signed-off-by: Hou Zhiqiang Acked-by: Rob Herring --- V2: - Corrected the subject. Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt | 2 ++ 1 file changed, 2 insertions(+)

[PATCHv2 1/2] PCI: Disable MSI for Freescale PCIe RC mode

From: Hou Zhiqiang The Freescale PCIe controller advertises the MSI/MSI-X capability in both RC and Endpoint mode, but in RC mode it doesn't support MSI/MSI-X by itself, it can only transfer MSI/MSI-X from downstream devices. So add this quirk to prevent use of MSI/MSI-X in RC mode.

[PATCHv2 0/2] PCI: layerscape: add fixes for layerscape-pcie errata

From: Hou Zhiqiang The [1/2] is to fix layerscape PCIe MSI/MSI-X capability errata. The [2/2] is to change the default AXI system error response behavior for PCI Express outbound non-posted requests. Hou Zhiqiang (1): PCI: Disable MSI for Freescale PCIe RC mode Minghuan Lian (1):

[PATCHv2 2/2] pci/layerscape: change the default error response behavior

From: Minghuan Lian By default, when the PCIe controller experiences an erroneous completion from an external completer for its outbound non-posted request, it always sends an OKAY response to the device's internal AXI slave system interface. However, such default system error response behavior

[PATCHv2 0/2] mtd: m25p80: restore the addressing mode when stop using the flash

From: Hou Zhiqiang To be compatible with legacy device, reset the addressing mode to the default mode. Such as Freescale eSPI boot, it copies the images from SPI flash without firing a reset signal previously, so the reboot command will fail without reseting the addressing mode of SPI flash.

[PATCHv2 1/2] mtd: spi-nor: add an API to restore the status of SPI flash chip

From: Hou Zhiqiang Add this API to restore the status of SPI flash chip to the default such as addressing mode, whenever detach the driver from device or reboot the system. Signed-off-by: Hou Zhiqiang --- V2: - Changed the API name and added the comments and kernel document for it. - Export

[PATCHv2 2/2] mtd: m25p80: restore the status of SPI flash when stop using it

From: Hou Zhiqiang Implement .shutdown function to restore the status in reboot process, and add the same operation to the .remove function. Signed-off-by: Hou Zhiqiang --- V2: - Changed code format slightly. drivers/mtd/devices/m25p80.c | 9 + 1 file changed, 9 insertions(+) diff

[PATCHv3 2/2] mtd: m25p80: restore the status of SPI flash when exiting

From: Hou Zhiqiang Restore the status to be compatible with legacy devices. Take Freescale eSPI boot for example, it copies (in 3 Byte addressing mode) the RCW and bootloader images from SPI flash without firing a reset signal previously, so the reboot command will fail without reseting the

[PATCHv3 0/2] mtd: m25p80: restore the addressing mode when exiting

From: Hou Zhiqiang Restore the status to be compatible with legacy devices. Take Freescale eSPI boot for example, it copies (in 3 Byte addressing mode) the RCW and bootloader images from SPI flash without firing a reset signal previously, so the reboot command will fail without reseting the

[PATCHv3 1/2] mtd: spi-nor: add an API to restore the status of SPI flash chip

From: Hou Zhiqiang Add this API to restore the status of SPI flash chip to the default such as addressing mode, whenever detach the driver from device or reboot the system. Signed-off-by: Hou Zhiqiang --- V3: - no change. Documentation/mtd/spi-nor.txt | 3 +++ drivers/mtd/spi-nor/spi-nor.c

[PATCH 0/2] arm64: dts: Add ls1088a DSPI device tree nodes

From: Hou Zhiqiang LS1088A reuse LS2085A DSPI driver, this patchset just adds device tree nodes and adds compatible entry to documentation. Hou Zhiqiang (2): arm64: dts: ls1088a: add DT nodes for DSPI support Documentation: fsl: dspi: Add a compatible string for ls1088a DSPI

[PATCH 2/2] Documentation: fsl: dspi: Add a compatible string for ls1088a DSPI

From: Hou Zhiqiang Add a new compatible string "fsl,ls1088a-dspi". Signed-off-by: Hou Zhiqiang --- Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt

[PATCH 1/2] arm64: dts: ls1088a: add DT nodes for DSPI support

From: Hou Zhiqiang Signed-off-by: Hou Zhiqiang --- arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts | 28 +++ arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi| 13 +++ 2 files changed, 41 insertions(+) diff --git

[PATCH 2/2] pci/layerscape: change the default error response behavior

From: Minghuan Lian By default, when the PCIe controller experiences an erroneous completion from an external completer for its outbound non-posted request, it always sends an OKAY response to the device's internal AXI slave system interface. However, such default system error response behavior

[PATCH 0/2] PCI: layerscape: add fixes for layerscape-pcie errata

From: Hou Zhiqiang The [1/2] is to fix layerscape PCIe MSI/MSI-X capability errata. The [2/2] is to change the default AXI system error response behavior for PCI Express outbound non-posted requests. Hou Zhiqiang (1): PCI: Disable MSI for Freescale PCIe RC mode Minghuan Lian (1):

[PATCH 1/2] PCI: Disable MSI for Freescale PCIe RC mode

From: Hou Zhiqiang The Freescale PCIe controller advertises the MSI/MSI-X capability in both RC and Endpoint mode, but in RC mode it doesn't support MSI/MSI-X by it self, it can only transfer MSI/MSI-X from downstream devices. So add this quirk to prevent use of MSI/MSI-X in RC mode.

[PATCH 0/5] arm64: add ls1012a and ls1046a pcie support

From: Hou Zhiqiang This patch set adds ls1012a MSI and PCIe support, including driver and device tree nodes. The ls1046a's MSI support patch and PCIe driver patch has been applied, so only adds the PCIe device tree nodes. Hou Zhiqiang (5): irqchip/ls-scfg-msi: add LS1012a MSI support arm64:

[PATCH 3/5] PCI: layerscape: Add support for ls1012a

From: Hou Zhiqiang Signed-off-by: Hou Zhiqiang --- Documentation/devicetree/bindings/pci/layerscape-pci.txt | 1 + drivers/pci/dwc/pci-layerscape.c | 1 + 2 files changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt

[PATCH 5/5] arm64: dts: ls1046a: add PCIe controller DT nodes

From: Hou Zhiqiang LS1046a implements 3 PCIe 3.0 controllers. Signed-off-by: Hou Zhiqiang --- arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 75 ++ 1 file changed, 75 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi

[PATCH 2/5] arm64: dts: ls1012a: Add MSI controller DT node

From: Hou Zhiqiang Add MSI controller node for ls1012a platform. Signed-off-by: Hou Zhiqiang --- arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi

[PATCH 4/5] arm64: dts: ls1012a: Add PCIe controller DT node

From: Hou Zhiqiang Add PCIe controller node for ls1012a platform. Signed-off-by: Hou Zhiqiang --- arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 24 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi

[PATCH 1/5] irqchip/ls-scfg-msi: add LS1012a MSI support

From: Hou Zhiqiang The ls1012a implement only 1 msi controller, and it is the same as ls1043a. Signed-off-by: Hou Zhiqiang --- .../devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt | 1 + drivers/irqchip/irq-ls-scfg-msi.c| 1 + 2

[PATCHv4 3/9] arm64: dts: ls1043a: fix typo of MSI compatible string

From: Minghuan Lian "1" should be replaced by "l". This is a typo. The patch is to fix it. Signed-off-by: Minghuan Lian Signed-off-by: Hou Zhiqiang --- v4-v1: - None arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git

[PATCHv4 7/9] irqchip/ls-scfg-msi: add LS1046a MSI support

From: Minghuan Lian LS1046a includes 4 MSIRs, each MSIR is assigned a dedicate GIC SPI interrupt and provides 32 MSI interrupts. Compared to previous MSI, LS1046a's IBS(interrupt bit select) shift is changed to 2 and total MSI interrupt number is changed to 128. The patch adds structure

[PATCHv4 5/9] arm64: dts: ls1043a: share all MSIs

From: Minghuan Lian In order to maximize the use of MSI, a PCIe controller will share all MSI controllers. The patch changes "msi-parent" to refer to all MSI controller dts nodes. Signed-off-by: Minghuan Lian Signed-off-by: Hou Zhiqiang --- v4-v1: - None

[PATCHv4 2/9] arm: dts: ls1021a: fix typo of MSI compatible string

From: Minghuan Lian "1" should be replaced by "l". This is a typo. The patch is to fix it. Signed-off-by: Minghuan Lian Signed-off-by: Hou Zhiqiang --- v4-v1: - None arch/arm/boot/dts/ls1021a.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

[PATCHv4 9/9] irqchip/ls-scfg-msi: add MSI affinity support

From: Minghuan Lian For LS1046a and LS1043a v1.1, the MSI controller has 4 MSIRs and 4 GIC SPI interrupts which can be associated with different Core. So we can support affinity to improve the performance. The MSI message data is a byte for Layerscape MSI. 76 5 4 3 2 1 0 | - |

[PATCHv4 6/9] arm64: dts: ls1046a: add MSI dts node

From: Minghuan Lian LS1046a includes 3 MSI controllers. Each controller supports 128 interrupts. Signed-off-by: Minghuan Lian Acked-by: Rob Herring Signed-off-by: Hou Zhiqiang --- v4: - rebased code v3-v2: - None v2-v1: - change whitespace number

[PATCHv4 8/9] irqchip/ls-scfg-msi: add LS1043a v1.1 MSI support

From: Minghuan Lian A MSI controller of LS1043a v1.0 only includes one MSIR and is assigned one GIC interrupt. In order to support affinity, LS1043a v1.1 MSI is assigned 4 MSIRs and 4 GIC interrupts. But the MSIR has the different offset and only supports 8 MSIs. The bits between variable

[PATCHv4 4/9] arm: dts: ls1021a: share all MSIs

From: Minghuan Lian In order to maximize the use of MSI, a PCIe controller will share all MSI controllers. The patch changes msi-parent to refer to all MSI controller dts nodes. Signed-off-by: Minghuan Lian Signed-off-by: Hou Zhiqiang --- v4-v1: - None arch/arm/boot/dts/ls1021a.dtsi | 4

[PATCHv4 1/9] irqchip/ls-scfg-msi: fix typo of MSI compatible strings

From: Minghuan Lian The patch is to fix typo of the Layerscape SCFG MSI dts compatible strings. "1" is replaced by "l". Signed-off-by: Minghuan Lian Acked-by: Rob Herring Signed-off-by: Hou Zhiqiang --- v4-v1: - None .../devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt| 6

[PATCH 1/2] mtd: spi-nor: add a API to restore the addressing mode

From: Hou Zhiqiang It's better to restore the addressing mode of the SPI flash whenever remove the driver or reboot the system. Signed-off-by: Hou Zhiqiang --- drivers/mtd/spi-nor/spi-nor.c | 8 include/linux/mtd/spi-nor.h | 1 + 2 files changed, 9 insertions(+) diff --git

[PATCH 0/2] mtd: m25p80: restore the addressing mode when stop using the flash

From: Hou Zhiqiang To be compatible with legacy device, reset the addressing mode to the default mode. Such as Freescale eSPI boot, it copies the images from SPI flash without firing a reset signal previously, so the reboot command will fail without reseting the addressing mode of SPI flash.

[PATCH 2/2] mtd: m25p80: restore the addressing mode when stop using the flash

From: Hou Zhiqiang Add .shutdown function to restore the addressing mode in reboot process, and add the same operation to the .remove function. Signed-off-by: Hou Zhiqiang --- drivers/mtd/devices/m25p80.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/mtd/devices/m25p80.c

[PATCH 0/4] PCI: dwc: Refine the EP code no functionality change

From: Hou Zhiqiang Tune the EP mode code slightly to make it more readable. Hou Zhiqiang (4): PCI: dwc: Change to use an array to store the structure of functions PCI: dwc: Add CFG offset info into function's represented structure PCI: dwc: Rename callback function func_conf_select and

[PATCH 4/4] PCI: dwc: Change the parameter of function dw_pcie_ep_reset_bar()

From: Hou Zhiqiang This helper is endpoint mode specific, so change to use a pointer of 'struct dw_pcie_ep' as the parameter. Signed-off-by: Hou Zhiqiang --- drivers/pci/controller/dwc/pci-dra7xx.c | 2 +- drivers/pci/controller/dwc/pci-layerscape-ep.c | 2 +-

[PATCH 2/4] PCI: dwc: Add CFG offset info into function's represented structure

From: Hou Zhiqiang To avoid multiple calculating of the CFG offset for each function, store the CFG offset info to the function's represented structure, and only do one time calculation during the initialization. Signed-off-by: Hou Zhiqiang --- .../pci/controller/dwc/pcie-designware-ep.c |

[PATCH 3/4] PCI: dwc: Rename callback function func_conf_select and its instance

From: Hou Zhiqiang Rename the callback func_conf_select() and its instance and wrapper to *get_func_cfg_addr(), such that the code becomes more readable. Signed-off-by: Hou Zhiqiang --- drivers/pci/controller/dwc/pci-layerscape-ep.c | 6 +++--- drivers/pci/controller/dwc/pcie-designware-ep.c

[PATCH 1/4] PCI: dwc: Change to use an array to store the structure of functions

From: Hou Zhiqiang As there isn't dynamically adding and deleting a function's structure, the list_head is not necessary for this case. Array is easier and more efficient to search. Signed-off-by: Hou Zhiqiang --- .../pci/controller/dwc/pcie-designware-ep.c | 33 ---

[PATCH] PCI: dwc: Move forward the iATU detection process

From: Hou Zhiqiang In the dw_pcie_ep_init(), it depends on the detected iATU region numbers to allocate the in/outbound window management bit map. It fails after the commit 281f1f99cf3a ("PCI: dwc: Detect number of iATU windows"). So this patch move the iATU region detection into a new

[PATCHv7 00/12]PCI: dwc: Add the multiple PF support for DWC and Layerscape

From: Hou Zhiqiang Add the PCIe EP multiple PF support for DWC and Layerscape, and use a list to manage the PFs of each PCIe controller; add the doorbell MSIX function for DWC; and refactor the Layerscape EP driver due to some difference in Layercape platforms PCIe integration. Hou Zhiqiang

[PATCHv7 01/12] PCI: designware-ep: Add multiple PFs support for DWC

From: Xiaowei Bao Add multiple PFs support for DWC, due to different PF have different config space, we use func_conf_select callback function to access the different PF's config space, the different chip company need to implement this callback function when use the DWC IP core and intend to

[PATCHv7 02/12] PCI: designware-ep: Add the doorbell mode of MSI-X in EP mode

From: Xiaowei Bao Add the doorbell mode of MSI-X in DWC EP driver. Signed-off-by: Xiaowei Bao Reviewed-by: Andrew Murray Signed-off-by: Hou Zhiqiang --- V7: - Rebase the patch without functionality change. drivers/pci/controller/dwc/pcie-designware-ep.c | 14 ++

[PATCHv7 12/12] misc: pci_endpoint_test: Add driver data for Layerscape PCIe controllers

From: Hou Zhiqiang The commit 0a121f9bc3f5 ("misc: pci_endpoint_test: Use streaming DMA APIs for buffer allocation") changed to use streaming DMA APIs, however, dma_map_single() might not return a 4KB aligned address, so add the default_data as driver data for Layerscape PCIe controllers to make

[PATCHv7 06/12] PCI: layerscape: Fix some format issue of the code

From: Xiaowei Bao Fix some format issue of the code in EP driver. Signed-off-by: Xiaowei Bao Reviewed-by: Andrew Murray Signed-off-by: Hou Zhiqiang --- V7: - Rebase the patch without functionality change. drivers/pci/controller/dwc/pci-layerscape-ep.c | 4 ++-- 1 file changed, 2

[PATCHv7 09/12] PCI: layerscape: Add EP mode support for ls1088a and ls2088a

From: Xiaowei Bao Add PCIe EP mode support for ls1088a and ls2088a, there are some difference between LS1 and LS2 platform, so refactor the code of the EP driver. Signed-off-by: Xiaowei Bao Reviewed-by: Rob Herring Signed-off-by: Hou Zhiqiang --- V7: - Rebase the patch without functionality

[PATCHv7 05/12] dt-bindings: pci: layerscape-pci: Add compatible strings for ls1088a and ls2088a

From: Xiaowei Bao Add compatible strings for ls1088a and ls2088a. Signed-off-by: Xiaowei Bao Acked-by: Rob Herring Signed-off-by: Hou Zhiqiang --- V7: - Rebase the patch without functionality change. Documentation/devicetree/bindings/pci/layerscape-pci.txt | 2 ++ 1 file changed, 2

[PATCHv7 11/12] misc: pci_endpoint_test: Add LS1088a in pci_device_id table

From: Xiaowei Bao Add LS1088a in pci_device_id table so that pci-epf-test can be used for testing PCIe EP in LS1088a. Signed-off-by: Xiaowei Bao Reviewed-by: Andrew Murray Signed-off-by: Hou Zhiqiang --- V7: - Rebase the patch without functionality change. drivers/misc/pci_endpoint_test.c

[PATCHv7 03/12] PCI: designware-ep: Move the function of getting MSI capability forward

From: Xiaowei Bao Move the function of getting MSI capability to the front of init function, because the init function of the EP platform driver will use the return value by the function of getting MSI capability. Signed-off-by: Xiaowei Bao Reviewed-by: Andrew Murray Signed-off-by: Hou

[PATCHv7 08/12] PCI: layerscape: Modify the MSIX to the doorbell mode

From: Xiaowei Bao dw_pcie_ep_raise_msix_irq was never called in the exisitng driver before, because the ls1046a platform don't support the MSIX feature and msix_capable was always set to false. Now that add the ls1088a platform with MSIX support, use the doorbell method to support the MSIX

[PATCHv7 10/12] arm64: dts: layerscape: Add PCIe EP node for ls1088a

From: Xiaowei Bao Add PCIe EP node for ls1088a to support EP mode. Signed-off-by: Xiaowei Bao Reviewed-by: Andrew Murray Signed-off-by: Hou Zhiqiang --- V7: - Rebase the patch without functionality change. .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 31 +++ 1 file

[PATCHv7 07/12] PCI: layerscape: Modify the way of getting capability with different PEX

From: Xiaowei Bao The different PCIe controller in one board may be have different capability of MSI or MSIX, so change the way of getting the MSI capability, make it more flexible. Signed-off-by: Xiaowei Bao Reviewed-by: Rob Herring Signed-off-by: Hou Zhiqiang --- V7: - Rebase the patch

[PATCHv7 04/12] PCI: designware-ep: Modify MSI and MSIX CAP way of finding

From: Xiaowei Bao Each PF of EP device should have its own MSI or MSIX capabitily struct, so create a dw_pcie_ep_func struct and move the msi_cap and msix_cap to this struct from dw_pcie_ep, and manage the PFs via a list. Signed-off-by: Xiaowei Bao Signed-off-by: Hou Zhiqiang --- V7: -

[PATCH] PCI: layerscape: Change back to the default error response behavior

From: Hou Zhiqiang In the current error response behavior, it will send a SLVERR response to device's internal AXI slave system interface when the PCIe controller experiences an erroneous completion (UR, CA and CT) from an external completer for its outbound non-posted request, which will result

[PATCH] PCI: designware-ep: Fix the Header Type check

From: Hou Zhiqiang The current check will result in the multiple function device fails to initialize. So fix the check by masking out the multiple function bit. Fixes: 0b24134f7888 ("PCI: dwc: Add validation that PCIe core is set to correct mode") Signed-off-by: Hou Zhiqiang ---

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