[PATCH v6 1/3] dt-bindings: auxadc: Add binding document for Mediatek auxadc.
The commit adds the device tree binding documentation for the mediatek
auxadc found on Mediatek MT2701.
Thermal gets auxadc sample data by iio device.
So the commit changes auxadc device tree binding documentation from
/soc/mediatek/auxadc.txt to /iio/adc/mt6577_auxadc.txt.
Acked-by: Rob Herring <r...@kernel.org>
Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
---
.../auxadc.txt => iio/adc/mt6577_auxadc.txt} | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
rename Documentation/devicetree/bindings/{soc/mediatek/auxadc.txt =>
iio/adc/mt6577_auxadc.txt} (46%)
diff --git a/Documentation/devicetree/bindings/soc/mediatek/auxadc.txt
b/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt
similarity index 46%
rename from Documentation/devicetree/bindings/soc/mediatek/auxadc.txt
rename to Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt
index bdb7829..68c45cb 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/auxadc.txt
+++ b/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt
@@ -1,4 +1,4 @@
-MediaTek AUXADC
+* Mediatek AUXADC - Analog to Digital Converter on Mediatek mobile soc
(mt65xx/mt81xx/mt27xx)
===
The Auxiliary Analog/Digital Converter (AUXADC) is an ADC found
@@ -10,12 +10,20 @@
Documentation/devicetree/bindings/thermal/mediatek-thermal.txt
for the Thermal Controller which holds a phandle to the AUXADC.
Required properties:
-- compatible: Must be "mediatek,mt8173-auxadc"
-- reg: Address range of the AUXADC unit
+ - compatible: Should be one of:
+- "mediatek,mt2701-auxadc": For MT2701 family of SoCs
+- "mediatek,mt8173-auxadc": For MT8173 family of SoCs
+ - reg: Address range of the AUXADC unit.
+ - clocks: Should contain a clock specifier for each entry in clock-names
+ - clock-names: Should contain "main".
+ - #io-channel-cells: Should be 1, see ../iio-bindings.txt
Example:
-auxadc: auxadc@11001000 {
- compatible = "mediatek,mt8173-auxadc";
+auxadc: adc@11001000 {
+ compatible = "mediatek,mt2701-auxadc";
reg = <0 0x11001000 0 0x1000>;
+ clocks = < CLK_PERI_AUXADC>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
};
--
1.7.9.5
[PATCH v6 0/3] AUXADC: Mediatek auxadc driver
This series includes three patches:
1.Change the device tree binding documentation.
2.Add auxadc driver based on linux iio.
3.Add auxadc nodes in the mediatek MT2701 dtsi file.
Changes in patch v6:
1).Add commit message in auxadc node patch which dependents on "Add clock
support for Mediatek MT2701"[1].
2).Use val variable instead of rawdata variable and Change 'mutex_unlock' to
'goto err_timeout' in 'mt6577_auxadc_read'.
3).Remove '.' in the log when failed to get auxadc base address.
4).Change 'return -EINVAL' to 'return ret' and add 'ret = -EINVAL' when get
null clock rate.
5).Add inline function 'mt6577_auxadc_mod_reg' to replace read/modify/write
code sequence.
Changes in patch v5:
1).Add 'Acked-by' information in commit message.
1).Change auxadc compatible in binding document.
2).Remove power on failed check.
3).Moved power off error unwind block to 'err_power_off'.
Changes in patch v4:
1).Change the file name 'mt65xx_auxdc.txt' to 'mt6577_auxdc.txt'.
2).Remove 'break' after 'return' in 'mt6577_auxadc_read_raw'.
3).Use 'mt2701' instead of 'auxadc' in dts commit message.
4).Change 'auxadc@' to 'adc@' in mt2701.dtsi.
Changes in patch v3:
1).Add '#' before 'io-channel-cells' and change 'auxadc@' to 'adc@' in auxadc
binding document.
2).Fix CONFIG_MEDIATEK_MT65XX_AUXADC sequence as alphabetical order.
3).Change the prefix 'MT65XX' to 'MT6577' to match auxadc driver name.
4).Remove the delays stored in 'mt6577_auxadc_device' and use the defined delay
directly.
5).Use '-ETIMEDOUT' instead of '-EINVAL'.
6).Return value directly in 'mt6577_auxadc_read_raw'.
7).Add power off and unprepare clock if 'iio_device_register' failed.
8).Change 'Registers' to 'Register'.
Changes in patch v2:
1).Change the file name mt65xx_auxadc.c to mt6577_auxadc.c.
2).Add 'depends on ARCH_MEDIATEK || COMPILE_TEST and HAS_IOMEM' for
MEDIATEK_MT65XX_AUXADC config.
3).Add check case for return value of 'readl_poll_timeout'.
4).Remove returning 1 and 0 for SCALE and OFFSET. use channel type
'IIO_CHAN_INFO_PROCESSED' instead of 'IIO_CHAN_INFO_RAW'.
5).Remove 'IIO_CHAN_INFO_OFFSET' and 'IIO_CHAN_INFO_SCALE' in
'MT65XX_AUXADC_CHANNEL' channel type.
6).Add check case when auxadc power on failure. if auxadc power on failure,
clk_disable_unprepare should be executed.
7).Put 'platform_set_drvdata' before 'iio_device_register'.
8).Fix coding style and spelling error.
Zhiyong Tao (3):
dt-bindings: auxadc: Add binding document for Mediatek auxadc.
iio: adc: mt2701: Add Mediatek auxadc driver for mt2701.
arm: dts: mt2701: Add auxadc node.
.../auxadc.txt => iio/adc/mt6577_auxadc.txt} | 18 +-
arch/arm/boot/dts/mt2701.dtsi |9 +
drivers/iio/adc/Kconfig| 13 +
drivers/iio/adc/Makefile |1 +
drivers/iio/adc/mt6577_auxadc.c| 291
5 files changed, 327 insertions(+), 5 deletions(-)
rename Documentation/devicetree/bindings/{soc/mediatek/auxadc.txt =>
iio/adc/mt6577_auxadc.txt} (46%)
create mode 100644 drivers/iio/adc/mt6577_auxadc.c
[PATCH v6 3/3] arm: dts: mt2701: Add auxadc node.
The commit adds auxadc nodes to the Mediatek MT2701 dtsi file.
Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
---
This patch dependents on "Add clock support for Mediatek MT2701"[1].
Please accept this patch together with [1].
[1]http://lists.infradead.org/pipermail/linux-mediatek/2016-June/005969.html
---
arch/arm/boot/dts/mt2701.dtsi |9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 42d5a37..c0a2644 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -187,6 +187,15 @@
<0 0x10216000 0 0x2000>;
};
+ auxadc: adc@11001000 {
+ compatible = "mediatek,mt2701-auxadc";
+ reg = <0 0x11001000 0 0x1000>;
+ clocks = < CLK_PERI_AUXADC>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,mt2701-uart",
"mediatek,mt6577-uart";
--
1.7.9.5
[PATCH v6 2/3] iio: adc: mt2701: Add Mediatek auxadc driver for mt2701.
Add Mediatek auxadc driver based on iio.
It will register a device in iio and support iio.
So thermal can read auxadc channel to sample data by iio device.
It is tested successfully on mt2701 platform.
Mt8173 and mt6577 platforms are not tested.
But the expectation is compatible.
Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
---
drivers/iio/adc/Kconfig | 13 ++
drivers/iio/adc/Makefile|1 +
drivers/iio/adc/mt6577_auxadc.c | 291 +++
3 files changed, 305 insertions(+)
create mode 100644 drivers/iio/adc/mt6577_auxadc.c
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 25378c5..14929fc 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -305,6 +305,19 @@ config MCP3422
This driver can also be built as a module. If so, the module will be
called mcp3422.
+config MEDIATEK_MT6577_AUXADC
+tristate "MediaTek AUXADC driver"
+depends on ARCH_MEDIATEK || COMPILE_TEST
+depends on HAS_IOMEM
+help
+ Say yes here to enable support for MediaTek mt65xx AUXADC.
+
+ The driver supports immediate mode operation to read from one of
sixteen
+ channels (external or internal).
+
+ This driver can also be built as a module. If so, the module will be
+ called mt6577_auxadc.
+
config MEN_Z188_ADC
tristate "MEN 16z188 ADC IP Core support"
depends on MCB
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index 38638d4..8306347 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_MAX1027) += max1027.o
obj-$(CONFIG_MAX1363) += max1363.o
obj-$(CONFIG_MCP320X) += mcp320x.o
obj-$(CONFIG_MCP3422) += mcp3422.o
+obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
obj-$(CONFIG_NAU7802) += nau7802.o
diff --git a/drivers/iio/adc/mt6577_auxadc.c b/drivers/iio/adc/mt6577_auxadc.c
new file mode 100644
index 000..2d104c8
--- /dev/null
+++ b/drivers/iio/adc/mt6577_auxadc.c
@@ -0,0 +1,291 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ * Author: Zhiyong Tao <zhiyong@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Register definitions */
+#define MT6577_AUXADC_CON00x00
+#define MT6577_AUXADC_CON10x04
+#define MT6577_AUXADC_CON20x10
+#define MT6577_AUXADC_STA BIT(0)
+
+#define MT6577_AUXADC_DAT00x14
+#define MT6577_AUXADC_RDY0BIT(12)
+
+#define MT6577_AUXADC_MISC0x94
+#define MT6577_AUXADC_PDN_EN BIT(14)
+
+#define MT6577_AUXADC_DAT_MASK0xfff
+#define MT6577_AUXADC_SLEEP_US1000
+#define MT6577_AUXADC_TIMEOUT_US 1
+#define MT6577_AUXADC_POWER_READY_MS 1
+#define MT6577_AUXADC_SAMPLE_READY_US 25
+
+struct mt6577_auxadc_device {
+ void __iomem *reg_base;
+ struct clk *adc_clk;
+ struct mutex lock;
+};
+
+#define MT6577_AUXADC_CHANNEL(idx) { \
+ .type = IIO_VOLTAGE,\
+ .indexed = 1, \
+ .channel = (idx), \
+ .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \
+}
+
+static const struct iio_chan_spec mt6577_auxadc_iio_channels[] = {
+ MT6577_AUXADC_CHANNEL(0),
+ MT6577_AUXADC_CHANNEL(1),
+ MT6577_AUXADC_CHANNEL(2),
+ MT6577_AUXADC_CHANNEL(3),
+ MT6577_AUXADC_CHANNEL(4),
+ MT6577_AUXADC_CHANNEL(5),
+ MT6577_AUXADC_CHANNEL(6),
+ MT6577_AUXADC_CHANNEL(7),
+ MT6577_AUXADC_CHANNEL(8),
+ MT6577_AUXADC_CHANNEL(9),
+ MT6577_AUXADC_CHANNEL(10),
+ MT6577_AUXADC_CHANNEL(11),
+ MT6577_AUXADC_CHANNEL(12),
+ MT6577_AUXADC_CHANNEL(13),
+ MT6577_AUXADC_CHANNEL(14),
+ MT6577_AUXADC_CHANNEL(15),
+};
+
+static inline void mt6577_auxadc_mod_reg(void __iomem *reg,
+u32 or_mask, u32 and_mask)
+{
+ u32 val;
+
+ val = readl(reg);
+ val |= or_mask;
+ val &= ~and_mask;
+ writel(val, reg);
+}
+
+static int mt6577_a
Re: [PATCH v5 3/3] arm: dts: mt2701: Add auxadc node.
On Fri, 2016-07-22 at 06:08 +0800, kbuild test robot wrote: sorry, I forget to add this information: --- This patch dependents on "Add clock support for Mediatek MT2701"[1]. Please accept this patch together with [1]. [1]http://lists.infradead.org/pipermail/linux-mediatek/2016-June/005969.html --- I will add this information in next version commit message. > Hi, > > [auto build test ERROR on robh/for-next] > [also build test ERROR on v4.7-rc7 next-20160721] > [if your patch is applied to the wrong git tree, please drop us a note to > help improve the system] > > url: > https://github.com/0day-ci/linux/commits/Zhiyong-Tao/AUXADC-Mediatek-auxadc-driver/20160722-041141 > base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git > for-next > config: arm-at91_dt_defconfig (attached as .config) > compiler: arm-linux-gnueabi-gcc (Debian 5.4.0-6) 5.4.0 20160609 > reproduce: > wget > https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross > -O ~/bin/make.cross > chmod +x ~/bin/make.cross > # save the attached .config to linux build tree > make.cross ARCH=arm > > All errors (new ones prefixed by >>): > > >> Error: arch/arm/boot/dts/mt2701.dtsi:145.22-23 syntax error >FATAL ERROR: Unable to parse input tree > > --- > 0-DAY kernel test infrastructureOpen Source Technology Center > https://lists.01.org/pipermail/kbuild-all Intel Corporation
[PATCH v5 1/3] dt-bindings: auxadc: Add binding document for Mediatek auxadc.
The commit adds the device tree binding documentation for the mediatek
auxadc found on Mediatek MT2701.
Thermal gets auxadc sample data by iio device.
So the commit changes auxadc device tree binding documentation from
/soc/mediatek/auxadc.txt to /iio/adc/mt6577_auxadc.txt.
Acked-by: Rob Herring <r...@kernel.org>
Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
---
.../auxadc.txt => iio/adc/mt6577_auxadc.txt} | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
rename Documentation/devicetree/bindings/{soc/mediatek/auxadc.txt =>
iio/adc/mt6577_auxadc.txt} (46%)
diff --git a/Documentation/devicetree/bindings/soc/mediatek/auxadc.txt
b/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt
similarity index 46%
rename from Documentation/devicetree/bindings/soc/mediatek/auxadc.txt
rename to Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt
index bdb7829..68c45cb 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/auxadc.txt
+++ b/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt
@@ -1,4 +1,4 @@
-MediaTek AUXADC
+* Mediatek AUXADC - Analog to Digital Converter on Mediatek mobile soc
(mt65xx/mt81xx/mt27xx)
===
The Auxiliary Analog/Digital Converter (AUXADC) is an ADC found
@@ -10,12 +10,20 @@
Documentation/devicetree/bindings/thermal/mediatek-thermal.txt
for the Thermal Controller which holds a phandle to the AUXADC.
Required properties:
-- compatible: Must be "mediatek,mt8173-auxadc"
-- reg: Address range of the AUXADC unit
+ - compatible: Should be one of:
+- "mediatek,mt2701-auxadc": For MT2701 family of SoCs
+- "mediatek,mt8173-auxadc": For MT8173 family of SoCs
+ - reg: Address range of the AUXADC unit.
+ - clocks: Should contain a clock specifier for each entry in clock-names
+ - clock-names: Should contain "main".
+ - #io-channel-cells: Should be 1, see ../iio-bindings.txt
Example:
-auxadc: auxadc@11001000 {
- compatible = "mediatek,mt8173-auxadc";
+auxadc: adc@11001000 {
+ compatible = "mediatek,mt2701-auxadc";
reg = <0 0x11001000 0 0x1000>;
+ clocks = < CLK_PERI_AUXADC>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
};
--
1.7.9.5
[PATCH v5 3/3] arm: dts: mt2701: Add auxadc node.
The commit adds auxadc nodes to the Mediatek MT2701 dtsi file.
Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
---
arch/arm/boot/dts/mt2701.dtsi |9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 42d5a37..c0a2644 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -187,6 +187,15 @@
<0 0x10216000 0 0x2000>;
};
+ auxadc: adc@11001000 {
+ compatible = "mediatek,mt2701-auxadc";
+ reg = <0 0x11001000 0 0x1000>;
+ clocks = < CLK_PERI_AUXADC>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,mt2701-uart",
"mediatek,mt6577-uart";
--
1.7.9.5
[PATCH v5 2/3] iio: adc: mt2701: Add Mediatek auxadc driver for mt2701.
Add Mediatek auxadc driver based on iio.
It will register a device in iio and support iio.
So thermal can read auxadc channel to sample data by iio device.
It is tested successfully on mt2701 platform.
Mt8173 and mt6577 platforms are not tested.
But the expectation is compatible.
Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
---
drivers/iio/adc/Kconfig | 13 ++
drivers/iio/adc/Makefile|1 +
drivers/iio/adc/mt6577_auxadc.c | 289 +++
3 files changed, 303 insertions(+)
create mode 100644 drivers/iio/adc/mt6577_auxadc.c
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 25378c5..14929fc 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -305,6 +305,19 @@ config MCP3422
This driver can also be built as a module. If so, the module will be
called mcp3422.
+config MEDIATEK_MT6577_AUXADC
+tristate "MediaTek AUXADC driver"
+depends on ARCH_MEDIATEK || COMPILE_TEST
+depends on HAS_IOMEM
+help
+ Say yes here to enable support for MediaTek mt65xx AUXADC.
+
+ The driver supports immediate mode operation to read from one of
sixteen
+ channels (external or internal).
+
+ This driver can also be built as a module. If so, the module will be
+ called mt6577_auxadc.
+
config MEN_Z188_ADC
tristate "MEN 16z188 ADC IP Core support"
depends on MCB
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index 38638d4..8306347 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_MAX1027) += max1027.o
obj-$(CONFIG_MAX1363) += max1363.o
obj-$(CONFIG_MCP320X) += mcp320x.o
obj-$(CONFIG_MCP3422) += mcp3422.o
+obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
obj-$(CONFIG_NAU7802) += nau7802.o
diff --git a/drivers/iio/adc/mt6577_auxadc.c b/drivers/iio/adc/mt6577_auxadc.c
new file mode 100644
index 000..6240236
--- /dev/null
+++ b/drivers/iio/adc/mt6577_auxadc.c
@@ -0,0 +1,289 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ * Author: Zhiyong Tao <zhiyong@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Register definitions */
+#define MT6577_AUXADC_CON00x00
+#define MT6577_AUXADC_CON10x04
+#define MT6577_AUXADC_CON20x10
+#define MT6577_AUXADC_STA BIT(0)
+
+#define MT6577_AUXADC_DAT00x14
+#define MT6577_AUXADC_RDY0BIT(12)
+
+#define MT6577_AUXADC_MISC0x94
+#define MT6577_AUXADC_PDN_EN BIT(14)
+
+#define MT6577_AUXADC_DAT_MASK0xfff
+#define MT6577_AUXADC_SLEEP_US1000
+#define MT6577_AUXADC_TIMEOUT_US 1
+#define MT6577_AUXADC_POWER_READY_MS 1
+#define MT6577_AUXADC_SAMPLE_READY_US 25
+
+struct mt6577_auxadc_device {
+ void __iomem *reg_base;
+ struct clk *adc_clk;
+ struct mutex lock;
+};
+
+#define MT6577_AUXADC_CHANNEL(idx) { \
+ .type = IIO_VOLTAGE,\
+ .indexed = 1, \
+ .channel = (idx), \
+ .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \
+}
+
+static const struct iio_chan_spec mt6577_auxadc_iio_channels[] = {
+ MT6577_AUXADC_CHANNEL(0),
+ MT6577_AUXADC_CHANNEL(1),
+ MT6577_AUXADC_CHANNEL(2),
+ MT6577_AUXADC_CHANNEL(3),
+ MT6577_AUXADC_CHANNEL(4),
+ MT6577_AUXADC_CHANNEL(5),
+ MT6577_AUXADC_CHANNEL(6),
+ MT6577_AUXADC_CHANNEL(7),
+ MT6577_AUXADC_CHANNEL(8),
+ MT6577_AUXADC_CHANNEL(9),
+ MT6577_AUXADC_CHANNEL(10),
+ MT6577_AUXADC_CHANNEL(11),
+ MT6577_AUXADC_CHANNEL(12),
+ MT6577_AUXADC_CHANNEL(13),
+ MT6577_AUXADC_CHANNEL(14),
+ MT6577_AUXADC_CHANNEL(15),
+};
+
+static int mt6577_auxadc_read(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan)
+{
+ u32 rawdata, val;
+ void __iomem *reg_channel;
+ int ret;
+ struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev);
+
+ reg_channel = adc_de
[PATCH v5 0/3] AUXADC: Mediatek auxadc driver
This series includes three patches:
1.Change the device tree binding documentation.
2.Add auxadc driver based on linux iio.
3.Add auxadc nodes in the mediatek MT2701 dtsi file.
Changes in patch v5:
1).Add 'Acked-by' information in commit message.
1).Change auxadc compatible in binding document.
2).Remove power on failed check.
3).Moved power off error unwind block to 'err_power_off'.
Changes in patch v4:
1).Change the file name 'mt65xx_auxdc.txt' to 'mt6577_auxdc.txt'.
2).Remove 'break' after 'return' in 'mt6577_auxadc_read_raw'.
3).Use 'mt2701' instead of 'auxadc' in dts commit message.
4).Change 'auxadc@' to 'adc@' in mt2701.dtsi.
Changes in patch v3:
1).Add '#' before 'io-channel-cells' and change 'auxadc@' to 'adc@' in auxadc
binding document.
2).Fix CONFIG_MEDIATEK_MT65XX_AUXADC sequence as alphabetical order.
3).Change the prefix 'MT65XX' to 'MT6577' to match auxadc driver name.
4).Remove the delays stored in 'mt6577_auxadc_device' and use the defined delay
directly.
5).Use '-ETIMEDOUT' instead of '-EINVAL'.
6).Return value directly in 'mt6577_auxadc_read_raw'.
7).Add power off and unprepare clock if 'iio_device_register' failed.
8).Change 'Registers' to 'Register'.
Changes in patch v2:
1).Change the file name mt65xx_auxadc.c to mt6577_auxadc.c.
2).Add 'depends on ARCH_MEDIATEK || COMPILE_TEST and HAS_IOMEM' for
MEDIATEK_MT65XX_AUXADC config.
3).Add check case for return value of 'readl_poll_timeout'.
4).Remove returning 1 and 0 for SCALE and OFFSET. use channel type
'IIO_CHAN_INFO_PROCESSED' instead of 'IIO_CHAN_INFO_RAW'.
5).Remove 'IIO_CHAN_INFO_OFFSET' and 'IIO_CHAN_INFO_SCALE' in
'MT65XX_AUXADC_CHANNEL' channel type.
6).Add check case when auxadc power on failure. if auxadc power on failure,
clk_disable_unprepare should be executed.
7).Put 'platform_set_drvdata' before 'iio_device_register'.
8).Fix coding style and spelling error.
Zhiyong Tao (3):
dt-bindings: auxadc: Add binding document for Mediatek auxadc.
iio: adc: mt2701: Add Mediatek auxadc driver for mt2701.
arm: dts: mt2701: Add auxadc node.
.../auxadc.txt => iio/adc/mt6577_auxadc.txt} | 18 +-
arch/arm/boot/dts/mt2701.dtsi |9 +
drivers/iio/adc/Kconfig| 13 +
drivers/iio/adc/Makefile |1 +
drivers/iio/adc/mt6577_auxadc.c| 289
5 files changed, 325 insertions(+), 5 deletions(-)
rename Documentation/devicetree/bindings/{soc/mediatek/auxadc.txt =>
iio/adc/mt6577_auxadc.txt} (46%)
create mode 100644 drivers/iio/adc/mt6577_auxadc.c
Re: [PATCH v4 2/3] iio: adc: mt2701: Add Mediatek auxadc driver for mt2701.
On Mon, 2016-07-18 at 18:12 +0100, Jonathan Cameron wrote: > On 11/07/16 07:39, Zhiyong Tao wrote: > > Add Mediatek auxadc driver based on iio. > > It will register a device in iio and support iio. > > So thermal can read auxadc channel to sample data by iio device. > > It is tested successfully on mt2701 platform. > > Mt8173 and mt6577 platforms are not tested. > > But the expectation is compatible. > > > > Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com> > Looks good to me. Couple of really minor points / questions inline... > > Just one thing to confirm... (you probably already answered this!) > What are the units of the voltage channels? > > Jonathan The units of the voltage channels are mv. > > --- > > drivers/iio/adc/Kconfig | 13 ++ > > drivers/iio/adc/Makefile|1 + > > drivers/iio/adc/mt6577_auxadc.c | 294 > > +++ > > 3 files changed, 308 insertions(+) > > create mode 100644 drivers/iio/adc/mt6577_auxadc.c > > > > diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig > > index 25378c5..14929fc 100644 > > --- a/drivers/iio/adc/Kconfig > > +++ b/drivers/iio/adc/Kconfig > > @@ -305,6 +305,19 @@ config MCP3422 > > This driver can also be built as a module. If so, the module will be > > called mcp3422. > > > > +config MEDIATEK_MT6577_AUXADC > > +tristate "MediaTek AUXADC driver" > > +depends on ARCH_MEDIATEK || COMPILE_TEST > > +depends on HAS_IOMEM > > +help > > + Say yes here to enable support for MediaTek mt65xx AUXADC. > > + > > + The driver supports immediate mode operation to read from one of > > sixteen > > + channels (external or internal). > > + > > + This driver can also be built as a module. If so, the module > > will be > > + called mt6577_auxadc. > > + > > config MEN_Z188_ADC > > tristate "MEN 16z188 ADC IP Core support" > > depends on MCB > > diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile > > index 38638d4..8306347 100644 > > --- a/drivers/iio/adc/Makefile > > +++ b/drivers/iio/adc/Makefile > > @@ -30,6 +30,7 @@ obj-$(CONFIG_MAX1027) += max1027.o > > obj-$(CONFIG_MAX1363) += max1363.o > > obj-$(CONFIG_MCP320X) += mcp320x.o > > obj-$(CONFIG_MCP3422) += mcp3422.o > > +obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o > > obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o > > obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o > > obj-$(CONFIG_NAU7802) += nau7802.o > > diff --git a/drivers/iio/adc/mt6577_auxadc.c > > b/drivers/iio/adc/mt6577_auxadc.c > > new file mode 100644 > > index 000..c7cc901 > > --- /dev/null > > +++ b/drivers/iio/adc/mt6577_auxadc.c > > @@ -0,0 +1,294 @@ > > +/* > > + * Copyright (c) 2016 MediaTek Inc. > > + * Author: Zhiyong Tao <zhiyong@mediatek.com> > > + * > > + * This program is free software; you can redistribute it and/or modify > > + * it under the terms of the GNU General Public License version 2 as > > + * published by the Free Software Foundation. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +/* Register definitions */ > > +#define MT6577_AUXADC_CON00x00 > > +#define MT6577_AUXADC_CON10x04 > > +#define MT6577_AUXADC_CON20x10 > > +#define MT6577_AUXADC_STA BIT(0) > > + > > +#define MT6577_AUXADC_DAT00x14 > > +#define MT6577_AUXADC_RDY0BIT(12) > > + > > +#define MT6577_AUXADC_MISC0x94 > > +#define MT6577_AUXADC_PDN_EN BIT(14) > > + > > +#define MT6577_AUXADC_DAT_MASK0xfff > > +#define MT6577_AUXADC_SLEEP_US1000 > > +#define MT6577_AUXADC_TIMEOUT_US 1 > > +#define MT6577_AUXADC_POWER_READY_MS 1 > > +#define MT6577_AUXADC_SAMPLE_READY_US 25 > >
Re: [PATCH v4 2/3] iio: adc: mt2701: Add Mediatek auxadc driver for mt2701.
On Wed, 2016-07-20 at 14:02 +0800, zhiyong tao wrote: > On Mon, 2016-07-18 at 18:12 +0100, Jonathan Cameron wrote: > > On 11/07/16 07:39, Zhiyong Tao wrote: > > > Add Mediatek auxadc driver based on iio. > > > It will register a device in iio and support iio. > > > So thermal can read auxadc channel to sample data by iio device. > > > It is tested successfully on mt2701 platform. > > > Mt8173 and mt6577 platforms are not tested. > > > But the expectation is compatible. > > > > > > Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com> > > Looks good to me. Couple of really minor points / questions inline... > > > > Just one thing to confirm... (you probably already answered this!) > > What are the units of the voltage channels? > > > > Jonathan > > The units of the voltage channels are mv. > > > > --- > > > drivers/iio/adc/Kconfig | 13 ++ > > > drivers/iio/adc/Makefile|1 + > > > drivers/iio/adc/mt6577_auxadc.c | 294 > > > +++ > > > 3 files changed, 308 insertions(+) > > > create mode 100644 drivers/iio/adc/mt6577_auxadc.c > > > > > > diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig > > > index 25378c5..14929fc 100644 > > > --- a/drivers/iio/adc/Kconfig > > > +++ b/drivers/iio/adc/Kconfig > > > @@ -305,6 +305,19 @@ config MCP3422 > > > This driver can also be built as a module. If so, the module will be > > > called mcp3422. > > > > > > +config MEDIATEK_MT6577_AUXADC > > > +tristate "MediaTek AUXADC driver" > > > +depends on ARCH_MEDIATEK || COMPILE_TEST > > > +depends on HAS_IOMEM > > > +help > > > + Say yes here to enable support for MediaTek mt65xx AUXADC. > > > + > > > + The driver supports immediate mode operation to read from one > > > of sixteen > > > + channels (external or internal). > > > + > > > + This driver can also be built as a module. If so, the module > > > will be > > > + called mt6577_auxadc. > > > + > > > config MEN_Z188_ADC > > > tristate "MEN 16z188 ADC IP Core support" > > > depends on MCB > > > diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile > > > index 38638d4..8306347 100644 > > > --- a/drivers/iio/adc/Makefile > > > +++ b/drivers/iio/adc/Makefile > > > @@ -30,6 +30,7 @@ obj-$(CONFIG_MAX1027) += max1027.o > > > obj-$(CONFIG_MAX1363) += max1363.o > > > obj-$(CONFIG_MCP320X) += mcp320x.o > > > obj-$(CONFIG_MCP3422) += mcp3422.o > > > +obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o > > > obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o > > > obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o > > > obj-$(CONFIG_NAU7802) += nau7802.o > > > diff --git a/drivers/iio/adc/mt6577_auxadc.c > > > b/drivers/iio/adc/mt6577_auxadc.c > > > new file mode 100644 > > > index 000..c7cc901 > > > --- /dev/null > > > +++ b/drivers/iio/adc/mt6577_auxadc.c > > > @@ -0,0 +1,294 @@ > > > +/* > > > + * Copyright (c) 2016 MediaTek Inc. > > > + * Author: Zhiyong Tao <zhiyong@mediatek.com> > > > + * > > > + * This program is free software; you can redistribute it and/or modify > > > + * it under the terms of the GNU General Public License version 2 as > > > + * published by the Free Software Foundation. > > > + * > > > + * This program is distributed in the hope that it will be useful, > > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > > + * GNU General Public License for more details. > > > + */ > > > + > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > + > > > +/* Register definitions */ > > > +#define MT6577_AUXADC_CON00x00 > > > +#define MT6577_AUXADC_CON10x04 > > > +#define MT6577_AUXADC_CON20x10 > > > +#define MT6577_AUXADC_STA BIT(0) > > > + > > > +#d
Re: [PATCH v4 1/3] dt-bindings: auxadc: Add binding document for Mediatek auxadc.
On Mon, 2016-07-11 at 14:39 +0800, Zhiyong Tao wrote:
> The commit adds the device tree binding documentation for the mediatek
> auxadc found on Mediatek MT2701.
> Thermal gets auxadc sample data by iio device.
> So the commit changes auxadc device tree binding documentation from
> /soc/mediatek/auxadc.txt to /iio/adc/mt6577_auxadc.txt.
>
> Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
> ---
I forgot that I should use the command 'git format-patch -M' to submit
this patch. The follow information is the patch after executing the
above command. If the patch needs to be resent, please help to notify
me. I will resend the patch quickly.
The follow information:
.../auxadc.txt => iio/adc/mt6577_auxadc.txt} | 16
+++-
1 file changed, 11 insertions(+), 5 deletions(-)
rename Documentation/devicetree/bindings/{soc/mediatek/auxadc.txt =>
iio/adc/mt6577_auxadc.txt} (50%)
diff --git a/Documentation/devicetree/bindings/soc/mediatek/auxadc.txt
b/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt
similarity index 50%
rename from Documentation/devicetree/bindings/soc/mediatek/auxadc.txt
rename to Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt
index bdb7829..bc23792 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/auxadc.txt
+++ b/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt
@@ -1,4 +1,4 @@
-MediaTek AUXADC
+* Mediatek AUXADC - Analog to Digital Converter on Mediatek mobile soc
(mt65xx/mt81xx/mt27xx)
===
The Auxiliary Analog/Digital Converter (AUXADC) is an ADC found
@@ -10,12 +10,18 @@
Documentation/devicetree/bindings/thermal/mediatek-thermal.txt
for the Thermal Controller which holds a phandle to the AUXADC.
Required properties:
-- compatible: Must be "mediatek,mt8173-auxadc"
-- reg: Address range of the AUXADC unit
+ - compatible: "mediatek,mt2701-auxadc" or "mediatek,mt8173-auxadc"
+ - reg: Address range of the AUXADC unit.
+ - clocks: Should contain a clock specifier for each entry in
clock-names
+ - clock-names: Should contain "main".
+ - #io-channel-cells: Should be 1, see ../iio-bindings.txt
Example:
-auxadc: auxadc@11001000 {
- compatible = "mediatek,mt8173-auxadc";
+auxadc: adc@11001000 {
+ compatible = "mediatek,mt2701-auxadc";
reg = <0 0x11001000 0 0x1000>;
+ clocks = < CLK_PERI_AUXADC>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
};
--
1.7.9.5
> .../devicetree/bindings/iio/adc/mt6577_auxadc.txt | 27
>
> .../devicetree/bindings/soc/mediatek/auxadc.txt| 21 ---
> 2 files changed, 27 insertions(+), 21 deletions(-)
> create mode 100644
> Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt
> delete mode 100644 Documentation/devicetree/bindings/soc/mediatek/auxadc.txt
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt
> b/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt
> new file mode 100644
> index 000..bc23792
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt
> @@ -0,0 +1,27 @@
> +* Mediatek AUXADC - Analog to Digital Converter on Mediatek mobile soc
> (mt65xx/mt81xx/mt27xx)
> +===
> +
> +The Auxiliary Analog/Digital Converter (AUXADC) is an ADC found
> +in some Mediatek SoCs which among other things measures the temperatures
> +in the SoC. It can be used directly with register accesses, but it is also
> +used by thermal controller which reads the temperatures from the AUXADC
> +directly via its own bus interface. See
> +Documentation/devicetree/bindings/thermal/mediatek-thermal.txt
> +for the Thermal Controller which holds a phandle to the AUXADC.
> +
> +Required properties:
> + - compatible: "mediatek,mt2701-auxadc" or "mediatek,mt8173-auxadc"
> + - reg: Address range of the AUXADC unit.
> + - clocks: Should contain a clock specifier for each entry in clock-names
> + - clock-names: Should contain "main".
> + - #io-channel-cells: Should be 1, see ../iio-bindings.txt
> +
> +Example:
> +
> +auxadc: adc@11001000 {
> + compatible = "mediatek,mt2701-auxadc";
> + reg = <0 0x11001000 0 0x1000>;
> + clocks = < CLK_PERI_AUXADC>;
> + clock-names = "main";
> + #io-channel-cells = <1>;
> +};
> diff --git a/Documentation/devicetree/bindings/soc/mediatek/auxadc.txt
> b/Documentation/devicetree/bindings/soc/mediatek/auxadc.txt
> deleted file mode 100644
> index bdb7829..000
> --- a/Documentation/devicetree/bindings/soc/mediatek/auxadc.txt
> +++ /dev/null
> @@ -1,21 +0,0 @@
> -MediaTek AUXADC
> -===
> -
> -The Auxiliary Analog/Digital Conver
[PATCH v2 0/3] AUXADC: Mediatek auxadc driver
This series includes three patches: 1.Change the device tree binding documentation. 2.Add auxadc driver based on linux iio. 3.Add auxadc nodes in the mediatek MT2701 dtsi file. changes in patch 2: 1).Change the file name mt65xx_auxadc.c to mt6577_auxadc.c. 2).Add 'depends on ARCH_MEDIATEK || COMPILE_TEST and HAS_IOMEM' for MEDIATEK_MT65XX_AUXADC config. 3).Add check case for return value of 'readl_poll_timeout'. 4).Remove returning 1 and 0 for SCALE and OFFSET. use channel type 'IIO_CHAN_INFO_PROCESSED' instead of 'IIO_CHAN_INFO_RAW'. 5).Remove 'IIO_CHAN_INFO_OFFSET' and 'IIO_CHAN_INFO_SCALE' in 'MT65XX_AUXADC_CHANNEL' channel type. 6).Add check case when auxadc power on failure. if auxadc power on failure, clk_disable_unprepare should be executed. 7).Put 'platform_set_drvdata' before 'iio_device_register'. 8).Fix coding style and spelling error. Zhiyong Tao (3): dt-bindings: auxadc: Add binding document for Mediatek auxadc. auxadc: Add Mediatek auxadc driver for mt2701. arm: dts: auxadc: Add auxadc node. .../devicetree/bindings/iio/adc/mt65xx_auxadc.txt | 27 ++ .../devicetree/bindings/soc/mediatek/auxadc.txt| 21 -- arch/arm/boot/dts/mt2701.dtsi |9 + drivers/iio/adc/Kconfig| 13 + drivers/iio/adc/Makefile |1 + drivers/iio/adc/mt6577_auxadc.c| 301 6 files changed, 351 insertions(+), 21 deletions(-) create mode 100644 Documentation/devicetree/bindings/iio/adc/mt65xx_auxadc.txt delete mode 100644 Documentation/devicetree/bindings/soc/mediatek/auxadc.txt create mode 100644 drivers/iio/adc/mt6577_auxadc.c
[PATCH v2 1/3] dt-bindings: auxadc: Add binding document for Mediatek auxadc.
The commit adds the device tree binding documentation for the mediatek
auxadc found on Mediatek MT2701.
Thermal gets auxadc sample data by iio device.
So the commit changes auxadc device tree binding documentation from
/soc/mediatek/auxadc.txt to /iio/adc/mt65xx_auxadc.txt.
Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
---
.../devicetree/bindings/iio/adc/mt65xx_auxadc.txt | 27
.../devicetree/bindings/soc/mediatek/auxadc.txt| 21 ---
2 files changed, 27 insertions(+), 21 deletions(-)
create mode 100644 Documentation/devicetree/bindings/iio/adc/mt65xx_auxadc.txt
delete mode 100644 Documentation/devicetree/bindings/soc/mediatek/auxadc.txt
diff --git a/Documentation/devicetree/bindings/iio/adc/mt65xx_auxadc.txt
b/Documentation/devicetree/bindings/iio/adc/mt65xx_auxadc.txt
new file mode 100644
index 000..47fcd1b
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/mt65xx_auxadc.txt
@@ -0,0 +1,27 @@
+* Mediatek AUXADC - Analog to Digital Converter on Mediatek mobile soc
(mt65xx/mt81xx/mt27xx)
+===
+
+The Auxiliary Analog/Digital Converter (AUXADC) is an ADC found
+in some Mediatek SoCs which among other things measures the temperatures
+in the SoC. It can be used directly with register accesses, but it is also
+used by thermal controller which reads the temperatures from the AUXADC
+directly via its own bus interface. See
+Documentation/devicetree/bindings/thermal/mediatek-thermal.txt
+for the Thermal Controller which holds a phandle to the AUXADC.
+
+Required properties:
+ - compatible: "mediatek,mt2701-auxadc" or "mediatek,mt8173-auxadc"
+ - reg: Address range of the AUXADC unit.
+ - clocks: Should contain a clock specifier for each entry in clock-names
+ - clock-names: Should contain "main".
+ - io-channel-cells: Should be 1, see ../iio-bindings.txt
+
+Example:
+
+auxadc: auxadc@11001000 {
+ compatible = "mediatek,mt2701-auxadc";
+ reg = <0 0x11001000 0 0x1000>;
+ clocks = < CLK_PERI_AUXADC>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
+};
diff --git a/Documentation/devicetree/bindings/soc/mediatek/auxadc.txt
b/Documentation/devicetree/bindings/soc/mediatek/auxadc.txt
deleted file mode 100644
index bdb7829..000
--- a/Documentation/devicetree/bindings/soc/mediatek/auxadc.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-MediaTek AUXADC
-===
-
-The Auxiliary Analog/Digital Converter (AUXADC) is an ADC found
-in some Mediatek SoCs which among other things measures the temperatures
-in the SoC. It can be used directly with register accesses, but it is also
-used by thermal controller which reads the temperatures from the AUXADC
-directly via its own bus interface. See
-Documentation/devicetree/bindings/thermal/mediatek-thermal.txt
-for the Thermal Controller which holds a phandle to the AUXADC.
-
-Required properties:
-- compatible: Must be "mediatek,mt8173-auxadc"
-- reg: Address range of the AUXADC unit
-
-Example:
-
-auxadc: auxadc@11001000 {
- compatible = "mediatek,mt8173-auxadc";
- reg = <0 0x11001000 0 0x1000>;
-};
--
1.7.9.5
[PATCH v2 2/3] auxadc: Add Mediatek auxadc driver for mt2701.
Add Mediatek auxadc driver based on iio.
It will register a device in iio and support iio.
So thermal can read auxadc channel to sample data by iio device.
It is tested successfully on mt2701 platform.
Mt8173 and mt6577 platforms are not tested.
But the expectation is compatible.
Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
---
drivers/iio/adc/Kconfig | 13 ++
drivers/iio/adc/Makefile|1 +
drivers/iio/adc/mt6577_auxadc.c | 301 +++
3 files changed, 315 insertions(+)
create mode 100644 drivers/iio/adc/mt6577_auxadc.c
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 25378c5..66e9b44 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -315,6 +315,19 @@ config MEN_Z188_ADC
This driver can also be built as a module. If so, the module will be
called men_z188_adc.
+config MEDIATEK_MT65XX_AUXADC
+ tristate "MediaTek AUXADC driver"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ depends on HAS_IOMEM
+ help
+ Say yes here to enable support for MediaTek mt65xx AUXADC.
+
+ The driver supports immediate mode operation to read from one of
sixteen
+ channels (external or internal).
+
+ This driver can also be built as a module. If so, the module will be
+ called mt6577_auxadc.
+
config MXS_LRADC
tristate "Freescale i.MX23/i.MX28 LRADC"
depends on (ARCH_MXS || COMPILE_TEST) && HAS_IOMEM
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index 38638d4..14a630f 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_MAX1363) += max1363.o
obj-$(CONFIG_MCP320X) += mcp320x.o
obj-$(CONFIG_MCP3422) += mcp3422.o
obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
+obj-$(CONFIG_MEDIATEK_MT65XX_AUXADC) += mt6577_auxadc.o
obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
obj-$(CONFIG_NAU7802) += nau7802.o
obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
diff --git a/drivers/iio/adc/mt6577_auxadc.c b/drivers/iio/adc/mt6577_auxadc.c
new file mode 100644
index 000..a56531a
--- /dev/null
+++ b/drivers/iio/adc/mt6577_auxadc.c
@@ -0,0 +1,301 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ * Author: Zhiyong Tao <zhiyong@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Registers definitions */
+#define MT65XX_AUXADC_CON00x00
+#define MT65XX_AUXADC_CON10x04
+#define MT65XX_AUXADC_CON20x10
+#define MT65XX_AUXADC_STA BIT(0)
+
+#define MT65XX_AUXADC_DAT00x14
+#define MT65XX_AUXADC_RDY0BIT(12)
+
+#define MT65XX_AUXADC_MISC0x94
+#define MT65XX_AUXADC_PDN_EN BIT(14)
+
+#define MT65XX_AUXADC_DAT_MASK0xfff
+#define MT65XX_AUXADC_SLEEP_US1000
+#define MT65XX_AUXADC_TIMEOUT_US 1
+#define MT65XX_AUXADC_POWER_READY_MS 1
+#define MT65XX_AUXADC_SAMPLE_READY_US 25
+
+struct mt65xx_auxadc_device {
+ void __iomem *reg_base;
+ struct clk *adc_clk;
+ struct mutex lock;
+ unsigned int power_ready_ms;
+ unsigned int sample_ready_us;
+};
+
+#define MT65XX_AUXADC_CHANNEL(idx) { \
+ .type = IIO_VOLTAGE,\
+ .indexed = 1, \
+ .channel = (idx), \
+ .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \
+}
+
+static const struct iio_chan_spec mt65xx_auxadc_iio_channels[] = {
+ MT65XX_AUXADC_CHANNEL(0),
+ MT65XX_AUXADC_CHANNEL(1),
+ MT65XX_AUXADC_CHANNEL(2),
+ MT65XX_AUXADC_CHANNEL(3),
+ MT65XX_AUXADC_CHANNEL(4),
+ MT65XX_AUXADC_CHANNEL(5),
+ MT65XX_AUXADC_CHANNEL(6),
+ MT65XX_AUXADC_CHANNEL(7),
+ MT65XX_AUXADC_CHANNEL(8),
+ MT65XX_AUXADC_CHANNEL(9),
+ MT65XX_AUXADC_CHANNEL(10),
+ MT65XX_AUXADC_CHANNEL(11),
+ MT65XX_AUXADC_CHANNEL(12),
+ MT65XX_AUXADC_CHANNEL(13),
+ MT65XX_AUXADC_CHANNEL(14),
+ MT65XX_AUXADC_CHANNEL(15),
+};
+
+static int mt65xx_auxadc_read(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan)
+{
+ u32 rawdata, val;
+ void __iomem *reg_
[PATCH v2 3/3] arm: dts: auxadc: Add auxadc node.
The commit adds auxadc nodes to the Mediatek MT2701 dtsi file.
Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
---
arch/arm/boot/dts/mt2701.dtsi |9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 42d5a37..464c86a 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -187,6 +187,15 @@
<0 0x10216000 0 0x2000>;
};
+ auxadc: auxadc@11001000 {
+ compatible = "mediatek,mt2701-auxadc";
+ reg = <0 0x11001000 0 0x1000>;
+ clocks = < CLK_PERI_AUXADC>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,mt2701-uart",
"mediatek,mt6577-uart";
--
1.7.9.5
[PATCH v3 2/2] iio: adc: mt2701: Add Mediatek auxadc driver for mt2701.
Add Mediatek auxadc driver based on iio.
It will register a device in iio and support iio.
So thermal can read auxadc channel to sample data by iio device.
It is tested successfully on mt2701 platform.
Mt8173 and mt6577 platforms are not tested.
But the expectation is compatible.
Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
---
drivers/iio/adc/Kconfig | 26 +++---
drivers/iio/adc/Makefile|2 +-
drivers/iio/adc/mt6577_auxadc.c | 186 +++
3 files changed, 104 insertions(+), 110 deletions(-)
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 66e9b44..14929fc 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -305,6 +305,19 @@ config MCP3422
This driver can also be built as a module. If so, the module will be
called mcp3422.
+config MEDIATEK_MT6577_AUXADC
+tristate "MediaTek AUXADC driver"
+depends on ARCH_MEDIATEK || COMPILE_TEST
+depends on HAS_IOMEM
+help
+ Say yes here to enable support for MediaTek mt65xx AUXADC.
+
+ The driver supports immediate mode operation to read from one of
sixteen
+ channels (external or internal).
+
+ This driver can also be built as a module. If so, the module will be
+ called mt6577_auxadc.
+
config MEN_Z188_ADC
tristate "MEN 16z188 ADC IP Core support"
depends on MCB
@@ -315,19 +328,6 @@ config MEN_Z188_ADC
This driver can also be built as a module. If so, the module will be
called men_z188_adc.
-config MEDIATEK_MT65XX_AUXADC
- tristate "MediaTek AUXADC driver"
- depends on ARCH_MEDIATEK || COMPILE_TEST
- depends on HAS_IOMEM
- help
- Say yes here to enable support for MediaTek mt65xx AUXADC.
-
- The driver supports immediate mode operation to read from one of
sixteen
- channels (external or internal).
-
- This driver can also be built as a module. If so, the module will be
- called mt6577_auxadc.
-
config MXS_LRADC
tristate "Freescale i.MX23/i.MX28 LRADC"
depends on (ARCH_MXS || COMPILE_TEST) && HAS_IOMEM
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index 14a630f..8306347 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -30,8 +30,8 @@ obj-$(CONFIG_MAX1027) += max1027.o
obj-$(CONFIG_MAX1363) += max1363.o
obj-$(CONFIG_MCP320X) += mcp320x.o
obj-$(CONFIG_MCP3422) += mcp3422.o
+obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
-obj-$(CONFIG_MEDIATEK_MT65XX_AUXADC) += mt6577_auxadc.o
obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
obj-$(CONFIG_NAU7802) += nau7802.o
obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
diff --git a/drivers/iio/adc/mt6577_auxadc.c b/drivers/iio/adc/mt6577_auxadc.c
index a56531a..a853ae8 100644
--- a/drivers/iio/adc/mt6577_auxadc.c
+++ b/drivers/iio/adc/mt6577_auxadc.c
@@ -24,80 +24,78 @@
#include
#include
-/* Registers definitions */
-#define MT65XX_AUXADC_CON00x00
-#define MT65XX_AUXADC_CON10x04
-#define MT65XX_AUXADC_CON20x10
-#define MT65XX_AUXADC_STA BIT(0)
+/* Register definitions */
+#define MT6577_AUXADC_CON00x00
+#define MT6577_AUXADC_CON10x04
+#define MT6577_AUXADC_CON20x10
+#define MT6577_AUXADC_STA BIT(0)
-#define MT65XX_AUXADC_DAT00x14
-#define MT65XX_AUXADC_RDY0BIT(12)
+#define MT6577_AUXADC_DAT00x14
+#define MT6577_AUXADC_RDY0BIT(12)
-#define MT65XX_AUXADC_MISC0x94
-#define MT65XX_AUXADC_PDN_EN BIT(14)
+#define MT6577_AUXADC_MISC0x94
+#define MT6577_AUXADC_PDN_EN BIT(14)
-#define MT65XX_AUXADC_DAT_MASK0xfff
-#define MT65XX_AUXADC_SLEEP_US1000
-#define MT65XX_AUXADC_TIMEOUT_US 1
-#define MT65XX_AUXADC_POWER_READY_MS 1
-#define MT65XX_AUXADC_SAMPLE_READY_US 25
+#define MT6577_AUXADC_DAT_MASK0xfff
+#define MT6577_AUXADC_SLEEP_US1000
+#define MT6577_AUXADC_TIMEOUT_US 1
+#define MT6577_AUXADC_POWER_READY_MS 1
+#define MT6577_AUXADC_SAMPLE_READY_US 25
-struct mt65xx_auxadc_device {
+struct mt6577_auxadc_device {
void __iomem *reg_base;
struct clk *adc_clk;
struct mutex lock;
- unsigned int power_ready_ms;
- unsigned int sample_ready_us;
};
-#define MT65XX_AUXADC_CHANNEL(idx) { \
+#define MT6577_AUXADC_CHANNEL(idx) { \
.type = IIO_VOLTAGE,\
.indexed = 1,
[PATCH v3 0/2] AUXADC: Mediatek auxadc driver
This series includes three patches: 1.Change the device tree binding documentation. 2.Add auxadc driver based on linux iio. 3.Add auxadc nodes in the mediatek MT2701 dtsi file. changes in patch v3: 1).Add '#' before 'io-channel-cells' and change 'auxadc@' to 'adc@' in auxadc binding document. 2).Fix CONFIG_MEDIATEK_MT65XX_AUXADC sequence as alphabetical order. 3).Change the prefix 'MT65XX' to 'MT6577' to match auxadc driver name. 4).Remove the delays stored in 'mt6577_auxadc_device' and use the defined delay directly. 5).Use '-ETIMEDOUT' instead of '-EINVAL'. 6).Return value directly in 'mt6577_auxadc_read_raw'. 7).Add power off and unprepare clock if 'iio_device_register' failed. 8).Change 'Registers' to 'Register'. changes in patch v2: 1).Change the file name mt65xx_auxadc.c to mt6577_auxadc.c. 2).Add 'depends on ARCH_MEDIATEK || COMPILE_TEST and HAS_IOMEM' for MEDIATEK_MT65XX_AUXADC config. 3).Add check case for return value of 'readl_poll_timeout'. 4).Remove returning 1 and 0 for SCALE and OFFSET. use channel type 'IIO_CHAN_INFO_PROCESSED' instead of 'IIO_CHAN_INFO_RAW'. 5).Remove 'IIO_CHAN_INFO_OFFSET' and 'IIO_CHAN_INFO_SCALE' in 'MT65XX_AUXADC_CHANNEL' channel type. 6).Add check case when auxadc power on failure. if auxadc power on failure, clk_disable_unprepare should be executed. 7).Put 'platform_set_drvdata' before 'iio_device_register'. 8).Fix coding style and spelling error. Zhiyong Tao (2): dt-bindings: auxadc: Add binding document for Mediatek auxadc. iio: adc: mt2701: Add Mediatek auxadc driver for mt2701. .../devicetree/bindings/iio/adc/mt65xx_auxadc.txt |4 +- drivers/iio/adc/Kconfig| 26 +-- drivers/iio/adc/Makefile |2 +- drivers/iio/adc/mt6577_auxadc.c| 186 ++-- 4 files changed, 106 insertions(+), 112 deletions(-)
[PATCH v3 1/2] dt-bindings: auxadc: Add binding document for Mediatek auxadc.
The commit adds the device tree binding documentation for the mediatek
auxadc found on Mediatek MT2701.
Thermal gets auxadc sample data by iio device.
So the commit changes auxadc device tree binding documentation from
/soc/mediatek/auxadc.txt to /iio/adc/mt65xx_auxadc.txt.
Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
---
.../devicetree/bindings/iio/adc/mt65xx_auxadc.txt |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/iio/adc/mt65xx_auxadc.txt
b/Documentation/devicetree/bindings/iio/adc/mt65xx_auxadc.txt
index 47fcd1b..bc23792 100644
--- a/Documentation/devicetree/bindings/iio/adc/mt65xx_auxadc.txt
+++ b/Documentation/devicetree/bindings/iio/adc/mt65xx_auxadc.txt
@@ -14,11 +14,11 @@ Required properties:
- reg: Address range of the AUXADC unit.
- clocks: Should contain a clock specifier for each entry in clock-names
- clock-names: Should contain "main".
- - io-channel-cells: Should be 1, see ../iio-bindings.txt
+ - #io-channel-cells: Should be 1, see ../iio-bindings.txt
Example:
-auxadc: auxadc@11001000 {
+auxadc: adc@11001000 {
compatible = "mediatek,mt2701-auxadc";
reg = <0 0x11001000 0 0x1000>;
clocks = < CLK_PERI_AUXADC>;
--
1.7.9.5
[PATCH v4 0/3] AUXADC: Mediatek auxadc driver
This series includes three patches: 1.Change the device tree binding documentation. 2.Add auxadc driver based on linux iio. 3.Add auxadc nodes in the mediatek MT2701 dtsi file. Changes in patch v4: 1).Change the file name 'mt65xx_auxdc.txt' to 'mt6577_auxdc.txt'. 2).Remove 'break' after 'return' in 'mt6577_auxadc_read_raw'. 3).Use 'mt2701' instead of 'auxadc' in dts commit message. 4).Change 'auxadc@' to 'adc@' in mt2701.dtsi. Changes in patch v3: 1).Add '#' before 'io-channel-cells' and change 'auxadc@' to 'adc@' in auxadc binding document. 2).Fix CONFIG_MEDIATEK_MT65XX_AUXADC sequence as alphabetical order. 3).Change the prefix 'MT65XX' to 'MT6577' to match auxadc driver name. 4).Remove the delays stored in 'mt6577_auxadc_device' and use the defined delay directly. 5).Use '-ETIMEDOUT' instead of '-EINVAL'. 6).Return value directly in 'mt6577_auxadc_read_raw'. 7).Add power off and unprepare clock if 'iio_device_register' failed. 8).Change 'Registers' to 'Register'. Changes in patch v2: 1).Change the file name mt65xx_auxadc.c to mt6577_auxadc.c. 2).Add 'depends on ARCH_MEDIATEK || COMPILE_TEST and HAS_IOMEM' for MEDIATEK_MT65XX_AUXADC config. 3).Add check case for return value of 'readl_poll_timeout'. 4).Remove returning 1 and 0 for SCALE and OFFSET. use channel type 'IIO_CHAN_INFO_PROCESSED' instead of 'IIO_CHAN_INFO_RAW'. 5).Remove 'IIO_CHAN_INFO_OFFSET' and 'IIO_CHAN_INFO_SCALE' in 'MT65XX_AUXADC_CHANNEL' channel type. 6).Add check case when auxadc power on failure. if auxadc power on failure, clk_disable_unprepare should be executed. 7).Put 'platform_set_drvdata' before 'iio_device_register'. 8).Fix coding style and spelling error. Zhiyong Tao (3): dt-bindings: auxadc: Add binding document for Mediatek auxadc. iio: adc: mt2701: Add Mediatek auxadc driver for mt2701. arm: dts: mt2701: Add auxadc node. .../devicetree/bindings/iio/adc/mt6577_auxadc.txt | 27 ++ .../devicetree/bindings/soc/mediatek/auxadc.txt| 21 -- arch/arm/boot/dts/mt2701.dtsi |9 + drivers/iio/adc/Kconfig| 13 + drivers/iio/adc/Makefile |1 + drivers/iio/adc/mt6577_auxadc.c| 294 6 files changed, 344 insertions(+), 21 deletions(-) create mode 100644 Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt delete mode 100644 Documentation/devicetree/bindings/soc/mediatek/auxadc.txt create mode 100644 drivers/iio/adc/mt6577_auxadc.c
[PATCH v4 3/3] arm: dts: mt2701: Add auxadc node.
The commit adds auxadc nodes to the Mediatek MT2701 dtsi file.
Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
---
arch/arm/boot/dts/mt2701.dtsi |9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 42d5a37..c0a2644 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -187,6 +187,15 @@
<0 0x10216000 0 0x2000>;
};
+ auxadc: adc@11001000 {
+ compatible = "mediatek,mt2701-auxadc";
+ reg = <0 0x11001000 0 0x1000>;
+ clocks = < CLK_PERI_AUXADC>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,mt2701-uart",
"mediatek,mt6577-uart";
--
1.7.9.5
[PATCH v4 2/3] iio: adc: mt2701: Add Mediatek auxadc driver for mt2701.
Add Mediatek auxadc driver based on iio.
It will register a device in iio and support iio.
So thermal can read auxadc channel to sample data by iio device.
It is tested successfully on mt2701 platform.
Mt8173 and mt6577 platforms are not tested.
But the expectation is compatible.
Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
---
drivers/iio/adc/Kconfig | 13 ++
drivers/iio/adc/Makefile|1 +
drivers/iio/adc/mt6577_auxadc.c | 294 +++
3 files changed, 308 insertions(+)
create mode 100644 drivers/iio/adc/mt6577_auxadc.c
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 25378c5..14929fc 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -305,6 +305,19 @@ config MCP3422
This driver can also be built as a module. If so, the module will be
called mcp3422.
+config MEDIATEK_MT6577_AUXADC
+tristate "MediaTek AUXADC driver"
+depends on ARCH_MEDIATEK || COMPILE_TEST
+depends on HAS_IOMEM
+help
+ Say yes here to enable support for MediaTek mt65xx AUXADC.
+
+ The driver supports immediate mode operation to read from one of
sixteen
+ channels (external or internal).
+
+ This driver can also be built as a module. If so, the module will be
+ called mt6577_auxadc.
+
config MEN_Z188_ADC
tristate "MEN 16z188 ADC IP Core support"
depends on MCB
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index 38638d4..8306347 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_MAX1027) += max1027.o
obj-$(CONFIG_MAX1363) += max1363.o
obj-$(CONFIG_MCP320X) += mcp320x.o
obj-$(CONFIG_MCP3422) += mcp3422.o
+obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
obj-$(CONFIG_NAU7802) += nau7802.o
diff --git a/drivers/iio/adc/mt6577_auxadc.c b/drivers/iio/adc/mt6577_auxadc.c
new file mode 100644
index 000..c7cc901
--- /dev/null
+++ b/drivers/iio/adc/mt6577_auxadc.c
@@ -0,0 +1,294 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ * Author: Zhiyong Tao <zhiyong@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Register definitions */
+#define MT6577_AUXADC_CON00x00
+#define MT6577_AUXADC_CON10x04
+#define MT6577_AUXADC_CON20x10
+#define MT6577_AUXADC_STA BIT(0)
+
+#define MT6577_AUXADC_DAT00x14
+#define MT6577_AUXADC_RDY0BIT(12)
+
+#define MT6577_AUXADC_MISC0x94
+#define MT6577_AUXADC_PDN_EN BIT(14)
+
+#define MT6577_AUXADC_DAT_MASK0xfff
+#define MT6577_AUXADC_SLEEP_US1000
+#define MT6577_AUXADC_TIMEOUT_US 1
+#define MT6577_AUXADC_POWER_READY_MS 1
+#define MT6577_AUXADC_SAMPLE_READY_US 25
+
+struct mt6577_auxadc_device {
+ void __iomem *reg_base;
+ struct clk *adc_clk;
+ struct mutex lock;
+};
+
+#define MT6577_AUXADC_CHANNEL(idx) { \
+ .type = IIO_VOLTAGE,\
+ .indexed = 1, \
+ .channel = (idx), \
+ .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \
+}
+
+static const struct iio_chan_spec mt6577_auxadc_iio_channels[] = {
+ MT6577_AUXADC_CHANNEL(0),
+ MT6577_AUXADC_CHANNEL(1),
+ MT6577_AUXADC_CHANNEL(2),
+ MT6577_AUXADC_CHANNEL(3),
+ MT6577_AUXADC_CHANNEL(4),
+ MT6577_AUXADC_CHANNEL(5),
+ MT6577_AUXADC_CHANNEL(6),
+ MT6577_AUXADC_CHANNEL(7),
+ MT6577_AUXADC_CHANNEL(8),
+ MT6577_AUXADC_CHANNEL(9),
+ MT6577_AUXADC_CHANNEL(10),
+ MT6577_AUXADC_CHANNEL(11),
+ MT6577_AUXADC_CHANNEL(12),
+ MT6577_AUXADC_CHANNEL(13),
+ MT6577_AUXADC_CHANNEL(14),
+ MT6577_AUXADC_CHANNEL(15),
+};
+
+static int mt6577_auxadc_read(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan)
+{
+ u32 rawdata, val;
+ void __iomem *reg_channel;
+ int ret;
+ struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev);
+
+ reg_channel = adc_de
[PATCH v4 1/3] dt-bindings: auxadc: Add binding document for Mediatek auxadc.
The commit adds the device tree binding documentation for the mediatek
auxadc found on Mediatek MT2701.
Thermal gets auxadc sample data by iio device.
So the commit changes auxadc device tree binding documentation from
/soc/mediatek/auxadc.txt to /iio/adc/mt6577_auxadc.txt.
Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
---
.../devicetree/bindings/iio/adc/mt6577_auxadc.txt | 27
.../devicetree/bindings/soc/mediatek/auxadc.txt| 21 ---
2 files changed, 27 insertions(+), 21 deletions(-)
create mode 100644 Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt
delete mode 100644 Documentation/devicetree/bindings/soc/mediatek/auxadc.txt
diff --git a/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt
b/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt
new file mode 100644
index 000..bc23792
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt
@@ -0,0 +1,27 @@
+* Mediatek AUXADC - Analog to Digital Converter on Mediatek mobile soc
(mt65xx/mt81xx/mt27xx)
+===
+
+The Auxiliary Analog/Digital Converter (AUXADC) is an ADC found
+in some Mediatek SoCs which among other things measures the temperatures
+in the SoC. It can be used directly with register accesses, but it is also
+used by thermal controller which reads the temperatures from the AUXADC
+directly via its own bus interface. See
+Documentation/devicetree/bindings/thermal/mediatek-thermal.txt
+for the Thermal Controller which holds a phandle to the AUXADC.
+
+Required properties:
+ - compatible: "mediatek,mt2701-auxadc" or "mediatek,mt8173-auxadc"
+ - reg: Address range of the AUXADC unit.
+ - clocks: Should contain a clock specifier for each entry in clock-names
+ - clock-names: Should contain "main".
+ - #io-channel-cells: Should be 1, see ../iio-bindings.txt
+
+Example:
+
+auxadc: adc@11001000 {
+ compatible = "mediatek,mt2701-auxadc";
+ reg = <0 0x11001000 0 0x1000>;
+ clocks = < CLK_PERI_AUXADC>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
+};
diff --git a/Documentation/devicetree/bindings/soc/mediatek/auxadc.txt
b/Documentation/devicetree/bindings/soc/mediatek/auxadc.txt
deleted file mode 100644
index bdb7829..000
--- a/Documentation/devicetree/bindings/soc/mediatek/auxadc.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-MediaTek AUXADC
-===
-
-The Auxiliary Analog/Digital Converter (AUXADC) is an ADC found
-in some Mediatek SoCs which among other things measures the temperatures
-in the SoC. It can be used directly with register accesses, but it is also
-used by thermal controller which reads the temperatures from the AUXADC
-directly via its own bus interface. See
-Documentation/devicetree/bindings/thermal/mediatek-thermal.txt
-for the Thermal Controller which holds a phandle to the AUXADC.
-
-Required properties:
-- compatible: Must be "mediatek,mt8173-auxadc"
-- reg: Address range of the AUXADC unit
-
-Example:
-
-auxadc: auxadc@11001000 {
- compatible = "mediatek,mt8173-auxadc";
- reg = <0 0x11001000 0 0x1000>;
-};
--
1.7.9.5
Re: [PATCH v7 3/3] arm: dts: mt2701: Add auxadc node.
On Sun, 2016-08-21 at 19:58 +0100, Jonathan Cameron wrote:
> On 18/08/16 08:11, Zhiyong Tao wrote:
> > The commit adds auxadc nodes to the Mediatek MT2701 dtsi file.
> >
> > Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
> > ---
> > This patch dependents on "Add clock support for Mediatek MT2701"[1].
> > Please accept this patch together with [1].
> > [1]http://lists.infradead.org/pipermail/linux-mediatek/2016-August/006620.html
Dear Jonathan,
This patch dependents on "Add clock support for Mediatek MT2701"[1].
We will refresh it again to Matthias when [1] is merged.
[1]http://lists.infradead.org/pipermail/linux-mediatek/2016-August/006620.html
Thanks.
> Guessing this is working it's way ultimately through arm-soc. Patches
> 1 and 2 are now heading through the iio / staging-iio route and should be
> merging in the next merge window if nothing odd happens.
>
> Thanks,
>
> Jonathan
> > ---
> > arch/arm/boot/dts/mt2701.dtsi |9 +
> > 1 file changed, 9 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> > index 7eab6f4..8e6a18c 100644
> > --- a/arch/arm/boot/dts/mt2701.dtsi
> > +++ b/arch/arm/boot/dts/mt2701.dtsi
> > @@ -175,6 +175,15 @@
> > <0 0x10216000 0 0x2000>;
> > };
> >
> > + auxadc: adc@11001000 {
> > + compatible = "mediatek,mt2701-auxadc";
> > + reg = <0 0x11001000 0 0x1000>;
> > + clocks = < CLK_PERI_AUXADC>;
> > + clock-names = "main";
> > + #io-channel-cells = <1>;
> > + status = "disabled";
> > + };
> > +
> > uart0: serial@11002000 {
> > compatible = "mediatek,mt2701-uart",
> > "mediatek,mt6577-uart";
> >
>
[PATCH v7 2/3] iio: adc: mt2701: Add Mediatek auxadc driver for mt2701.
Add Mediatek auxadc driver based on iio.
It will register a device in iio and support iio.
So thermal can read auxadc channel to sample data by iio device.
It is tested successfully on mt2701 platform.
Mt8173 and mt6577 platforms are not tested.
But the expectation is compatible.
Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
---
drivers/iio/adc/Kconfig | 13 ++
drivers/iio/adc/Makefile|1 +
drivers/iio/adc/mt6577_auxadc.c | 291 +++
3 files changed, 305 insertions(+)
create mode 100644 drivers/iio/adc/mt6577_auxadc.c
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 1de31bd..1936152 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -317,6 +317,19 @@ config MCP3422
This driver can also be built as a module. If so, the module will be
called mcp3422.
+config MEDIATEK_MT6577_AUXADC
+tristate "MediaTek AUXADC driver"
+depends on ARCH_MEDIATEK || COMPILE_TEST
+depends on HAS_IOMEM
+help
+ Say yes here to enable support for MediaTek mt65xx AUXADC.
+
+ The driver supports immediate mode operation to read from one of
sixteen
+ channels (external or internal).
+
+ This driver can also be built as a module. If so, the module will be
+ called mt6577_auxadc.
+
config MEN_Z188_ADC
tristate "MEN 16z188 ADC IP Core support"
depends on MCB
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index 0ba0d50..d528e2b 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_MAX1027) += max1027.o
obj-$(CONFIG_MAX1363) += max1363.o
obj-$(CONFIG_MCP320X) += mcp320x.o
obj-$(CONFIG_MCP3422) += mcp3422.o
+obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
obj-$(CONFIG_NAU7802) += nau7802.o
diff --git a/drivers/iio/adc/mt6577_auxadc.c b/drivers/iio/adc/mt6577_auxadc.c
new file mode 100644
index 000..2d104c8
--- /dev/null
+++ b/drivers/iio/adc/mt6577_auxadc.c
@@ -0,0 +1,291 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ * Author: Zhiyong Tao <zhiyong@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Register definitions */
+#define MT6577_AUXADC_CON00x00
+#define MT6577_AUXADC_CON10x04
+#define MT6577_AUXADC_CON20x10
+#define MT6577_AUXADC_STA BIT(0)
+
+#define MT6577_AUXADC_DAT00x14
+#define MT6577_AUXADC_RDY0BIT(12)
+
+#define MT6577_AUXADC_MISC0x94
+#define MT6577_AUXADC_PDN_EN BIT(14)
+
+#define MT6577_AUXADC_DAT_MASK0xfff
+#define MT6577_AUXADC_SLEEP_US1000
+#define MT6577_AUXADC_TIMEOUT_US 1
+#define MT6577_AUXADC_POWER_READY_MS 1
+#define MT6577_AUXADC_SAMPLE_READY_US 25
+
+struct mt6577_auxadc_device {
+ void __iomem *reg_base;
+ struct clk *adc_clk;
+ struct mutex lock;
+};
+
+#define MT6577_AUXADC_CHANNEL(idx) { \
+ .type = IIO_VOLTAGE,\
+ .indexed = 1, \
+ .channel = (idx), \
+ .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \
+}
+
+static const struct iio_chan_spec mt6577_auxadc_iio_channels[] = {
+ MT6577_AUXADC_CHANNEL(0),
+ MT6577_AUXADC_CHANNEL(1),
+ MT6577_AUXADC_CHANNEL(2),
+ MT6577_AUXADC_CHANNEL(3),
+ MT6577_AUXADC_CHANNEL(4),
+ MT6577_AUXADC_CHANNEL(5),
+ MT6577_AUXADC_CHANNEL(6),
+ MT6577_AUXADC_CHANNEL(7),
+ MT6577_AUXADC_CHANNEL(8),
+ MT6577_AUXADC_CHANNEL(9),
+ MT6577_AUXADC_CHANNEL(10),
+ MT6577_AUXADC_CHANNEL(11),
+ MT6577_AUXADC_CHANNEL(12),
+ MT6577_AUXADC_CHANNEL(13),
+ MT6577_AUXADC_CHANNEL(14),
+ MT6577_AUXADC_CHANNEL(15),
+};
+
+static inline void mt6577_auxadc_mod_reg(void __iomem *reg,
+u32 or_mask, u32 and_mask)
+{
+ u32 val;
+
+ val = readl(reg);
+ val |= or_mask;
+ val &= ~and_mask;
+ writel(val, reg);
+}
+
+static int mt6577_a
[PATCH v7 1/3] dt-bindings: auxadc: Add binding document for Mediatek auxadc.
The commit adds the device tree binding documentation for the mediatek
auxadc found on Mediatek MT2701.
Thermal gets auxadc sample data by iio device.
So the commit changes auxadc device tree binding documentation from
/soc/mediatek/auxadc.txt to /iio/adc/mt6577_auxadc.txt.
Acked-by: Rob Herring <r...@kernel.org>
Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
---
.../auxadc.txt => iio/adc/mt6577_auxadc.txt} | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
rename Documentation/devicetree/bindings/{soc/mediatek/auxadc.txt =>
iio/adc/mt6577_auxadc.txt} (46%)
diff --git a/Documentation/devicetree/bindings/soc/mediatek/auxadc.txt
b/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt
similarity index 46%
rename from Documentation/devicetree/bindings/soc/mediatek/auxadc.txt
rename to Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt
index bdb7829..68c45cb 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/auxadc.txt
+++ b/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt
@@ -1,4 +1,4 @@
-MediaTek AUXADC
+* Mediatek AUXADC - Analog to Digital Converter on Mediatek mobile soc
(mt65xx/mt81xx/mt27xx)
===
The Auxiliary Analog/Digital Converter (AUXADC) is an ADC found
@@ -10,12 +10,20 @@
Documentation/devicetree/bindings/thermal/mediatek-thermal.txt
for the Thermal Controller which holds a phandle to the AUXADC.
Required properties:
-- compatible: Must be "mediatek,mt8173-auxadc"
-- reg: Address range of the AUXADC unit
+ - compatible: Should be one of:
+- "mediatek,mt2701-auxadc": For MT2701 family of SoCs
+- "mediatek,mt8173-auxadc": For MT8173 family of SoCs
+ - reg: Address range of the AUXADC unit.
+ - clocks: Should contain a clock specifier for each entry in clock-names
+ - clock-names: Should contain "main".
+ - #io-channel-cells: Should be 1, see ../iio-bindings.txt
Example:
-auxadc: auxadc@11001000 {
- compatible = "mediatek,mt8173-auxadc";
+auxadc: adc@11001000 {
+ compatible = "mediatek,mt2701-auxadc";
reg = <0 0x11001000 0 0x1000>;
+ clocks = < CLK_PERI_AUXADC>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
};
--
1.7.9.5
[PATCH v7 3/3] arm: dts: mt2701: Add auxadc node.
The commit adds auxadc nodes to the Mediatek MT2701 dtsi file.
Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
---
This patch dependents on "Add clock support for Mediatek MT2701"[1].
Please accept this patch together with [1].
[1]http://lists.infradead.org/pipermail/linux-mediatek/2016-August/006620.html
---
arch/arm/boot/dts/mt2701.dtsi |9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 7eab6f4..8e6a18c 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -175,6 +175,15 @@
<0 0x10216000 0 0x2000>;
};
+ auxadc: adc@11001000 {
+ compatible = "mediatek,mt2701-auxadc";
+ reg = <0 0x11001000 0 0x1000>;
+ clocks = < CLK_PERI_AUXADC>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,mt2701-uart",
"mediatek,mt6577-uart";
--
1.7.9.5
[PATCH v7 0/3] AUXADC: Mediatek auxadc driver
This series includes three patches:
1.Change the device tree binding documentation.
2.Add auxadc driver based on linux iio.
3.Add auxadc nodes in the mediatek MT2701 dtsi file.
Changes in patch v7:
changes since v6:
-Rebase to v4.8-rcl.
Changes in patch v6:
1).Add commit message in auxadc node patch which dependents on "Add clock
support for Mediatek MT2701"[1].
2).Use val variable instead of rawdata variable and Change 'mutex_unlock' to
'goto err_timeout' in 'mt6577_auxadc_read'.
3).Remove '.' in the log when failed to get auxadc base address.
4).Change 'return -EINVAL' to 'return ret' and add 'ret = -EINVAL' when get
null clock rate.
5).Add inline function 'mt6577_auxadc_mod_reg' to replace read/modify/write
code sequence.
Changes in patch v5:
1).Add 'Acked-by' information in commit message.
1).Change auxadc compatible in binding document.
2).Remove power on failed check.
3).Moved power off error unwind block to 'err_power_off'.
Changes in patch v4:
1).Change the file name 'mt65xx_auxdc.txt' to 'mt6577_auxdc.txt'.
2).Remove 'break' after 'return' in 'mt6577_auxadc_read_raw'.
3).Use 'mt2701' instead of 'auxadc' in dts commit message.
4).Change 'auxadc@' to 'adc@' in mt2701.dtsi.
Changes in patch v3:
1).Add '#' before 'io-channel-cells' and change 'auxadc@' to 'adc@' in auxadc
binding document.
2).Fix CONFIG_MEDIATEK_MT65XX_AUXADC sequence as alphabetical order.
3).Change the prefix 'MT65XX' to 'MT6577' to match auxadc driver name.
4).Remove the delays stored in 'mt6577_auxadc_device' and use the defined delay
directly.
5).Use '-ETIMEDOUT' instead of '-EINVAL'.
6).Return value directly in 'mt6577_auxadc_read_raw'.
7).Add power off and unprepare clock if 'iio_device_register' failed.
8).Change 'Registers' to 'Register'.
Changes in patch v2:
1).Change the file name mt65xx_auxadc.c to mt6577_auxadc.c.
2).Add 'depends on ARCH_MEDIATEK || COMPILE_TEST and HAS_IOMEM' for
MEDIATEK_MT65XX_AUXADC config.
3).Add check case for return value of 'readl_poll_timeout'.
4).Remove returning 1 and 0 for SCALE and OFFSET. use channel type
'IIO_CHAN_INFO_PROCESSED' instead of 'IIO_CHAN_INFO_RAW'.
5).Remove 'IIO_CHAN_INFO_OFFSET' and 'IIO_CHAN_INFO_SCALE' in
'MT65XX_AUXADC_CHANNEL' channel type.
6).Add check case when auxadc power on failure. if auxadc power on failure,
clk_disable_unprepare should be executed.
7).Put 'platform_set_drvdata' before 'iio_device_register'.
8).Fix coding style and spelling error.
Zhiyong Tao (3):
dt-bindings: auxadc: Add binding document for Mediatek auxadc.
iio: adc: mt2701: Add Mediatek auxadc driver for mt2701.
arm: dts: mt2701: Add auxadc node.
.../auxadc.txt => iio/adc/mt6577_auxadc.txt} | 18 +-
arch/arm/boot/dts/mt2701.dtsi |9 +
drivers/iio/adc/Kconfig| 13 +
drivers/iio/adc/Makefile |1 +
drivers/iio/adc/mt6577_auxadc.c| 291
5 files changed, 327 insertions(+), 5 deletions(-)
rename Documentation/devicetree/bindings/{soc/mediatek/auxadc.txt =>
iio/adc/mt6577_auxadc.txt} (46%)
create mode 100644 drivers/iio/adc/mt6577_auxadc.c
[PATCH 1/3] dt-bindings: pinctrl: mt2712: add binding document
The commit adds mt2712 compatible node in binding document. Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com> --- .../devicetree/bindings/pinctrl/pinctrl-mt65xx.txt |1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt index 17631d0..37d7447 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt @@ -5,6 +5,7 @@ The Mediatek's Pin controller is used to control SoC pins. Required properties: - compatible: value should be one of the following. "mediatek,mt2701-pinctrl", compatible with mt2701 pinctrl. + "mediatek,mt2712-pinctrl", compatible with mt2712 pinctrl. "mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl. "mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl. "mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl. -- 1.7.9.5
[PATCH 3/3] pinctrl: add mt2712 pinctrl driver
The commit includes changes:
1)Add mt2712 pinctrl driver.
2)Arrange "mtk_pinctrl" before "mtk_pinctrl_devdata"
in "pinctrl-mtk-common.h".
3)Add "spec_dir_set" and "spec_dir_get" in "mtk_pinctrl_devdata".
4)Change "spec_dir_set" and add "spec_dir_get" in "pinctrl-mt2701.c"
and "pinctrl-mtk-common.c".
5)Change "port_mask" from "7" to "6" for EINT.
6)Remove generic pull config condition in "mtk_pconf_set_pull_select".
7)Change "arg" to "MTK_PUPD_SET_R1R0_00" of "mtk_pconf_set_pull_select".
Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
---
drivers/pinctrl/mediatek/Kconfig |8 +
drivers/pinctrl/mediatek/Makefile |1 +
drivers/pinctrl/mediatek/pinctrl-mt2701.c | 21 +-
drivers/pinctrl/mediatek/pinctrl-mt2712.c | 670 +
drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 16 +-
drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 44 +-
drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h | 1858 +
7 files changed, 2586 insertions(+), 32 deletions(-)
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt2712.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index fac9866..2e7be73 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -31,6 +31,14 @@ config PINCTRL_MT8127
select PINCTRL_MTK
# For ARMv8 SoCs
+
+config PINCTRL_MT2712
+ bool "Mediatek MT2712 pin control"
+ depends on OF
+ depends on ARM64 || COMPILE_TEST
+ default ARM64 && ARCH_MEDIATEK
+ select PINCTRL_MTK
+
config PINCTRL_MT8173
bool "Mediatek MT8173 pin control"
depends on OF
diff --git a/drivers/pinctrl/mediatek/Makefile
b/drivers/pinctrl/mediatek/Makefile
index e59c613..26c7435 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -3,6 +3,7 @@ obj-y += pinctrl-mtk-common.o
# SoC Drivers
obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o
+obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o
obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2701.c
b/drivers/pinctrl/mediatek/pinctrl-mt2701.c
index f86f3b3..4a43f5c 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt2701.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c
@@ -503,10 +503,26 @@ static void mt2701_spec_pinmux_set(struct regmap *reg,
unsigned int pin,
regmap_update_bits(reg, mt2701_spec_pinmux[i].offset, mask, value);
}
-static void mt2701_spec_dir_set(unsigned int *reg_addr, unsigned int pin)
+static int mt2701_spec_dir_set(struct mtk_pinctrl *pctl,
+ unsigned int *reg_addr,
+ unsigned int pin,
+ bool input)
{
if (pin > 175)
*reg_addr += 0x10;
+
+ return 0;
+}
+
+static int mt2701_spec_dir_get(struct mtk_pinctrl *pctl,
+ unsigned int *reg_addr,
+ unsigned int pin,
+ bool input)
+{
+ if (pin > 175)
+ *reg_addr += 0x10;
+
+ return 0;
}
static const struct mtk_pinctrl_devdata mt2701_pinctrl_data = {
@@ -520,6 +536,7 @@ static void mt2701_spec_dir_set(unsigned int *reg_addr,
unsigned int pin)
.spec_ies_smt_set = mt2701_ies_smt_set,
.spec_pinmux_set = mt2701_spec_pinmux_set,
.spec_dir_set = mt2701_spec_dir_set,
+ .spec_dir_get = mt2701_spec_dir_get,
.dir_offset = 0x,
.pullen_offset = 0x0150,
.pullsel_offset = 0x0280,
@@ -551,7 +568,7 @@ static void mt2701_spec_dir_set(unsigned int *reg_addr,
unsigned int pin)
.dbnc_ctrl = 0x500,
.dbnc_set = 0x600,
.dbnc_clr = 0x700,
- .port_mask = 6,
+ .port_mask = 7,
.ports = 6,
},
.ap_num = 169,
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2712.c
b/drivers/pinctrl/mediatek/pinctrl-mt2712.c
new file mode 100644
index 000..c933b75
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt2712.c
@@ -0,0 +1,670 @@
+/*
+ * Copyright (c) 2014-2015 MediaTek Inc.
+ * Author: Hongzhou.Yang <hongzhou.y...@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * M
[PATCH 0/3] PINCTRL: Mediatek pinctrl driver for mt2712
This series includes three patches: 1.Add mt2712 compatible node in binding document. 2.Add mt2712 pinctrl device node. 3.Add mt2712 pinctrl driver. Zhiyong Tao (3): dt-bindings: pinctrl: mt2712: add binding document arm64: dts: mt2712: add pintcrl device node. pinctrl: add mt2712 pinctrl driver .../devicetree/bindings/pinctrl/pinctrl-mt65xx.txt |1 + arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h | 1014 +++ arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 18 + drivers/pinctrl/mediatek/Kconfig |8 + drivers/pinctrl/mediatek/Makefile |1 + drivers/pinctrl/mediatek/pinctrl-mt2701.c | 21 +- drivers/pinctrl/mediatek/pinctrl-mt2712.c | 670 +++ drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 16 +- drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 44 +- drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h | 1858 10 files changed, 3619 insertions(+), 32 deletions(-) create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt2712.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h -- 1.9.1
[PATCH 2/3] arm64: dts: mt2712: add pintcrl device node.
The commit includes two change: 1)add pintcrl device node for mt2712. 2)add pinfunc file for mt2712. Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h | 1014 + arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 18 + 2 files changed, 1032 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h diff --git a/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h new file mode 100644 index 000..fe9d7bd --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h @@ -0,0 +1,1014 @@ +/* + * Copyright (C) 2015 MediaTek Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __DTS_MT2712_PINFUNC_H +#define __DTS_MT2712_PINFUNC_H + +#include + +#define MT2712_PIN_0_EINT0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define MT2712_PIN_0_EINT0__FUNC_EINT0 (MTK_PIN_NO(0) | 1) +#define MT2712_PIN_0_EINT0__FUNC_MBIST_DIAG_SCANOUT (MTK_PIN_NO(0) | 2) +#define MT2712_PIN_0_EINT0__FUNC_DSIA_TE (MTK_PIN_NO(0) | 3) +#define MT2712_PIN_0_EINT0__FUNC_DIN_D3 (MTK_PIN_NO(0) | 5) + +#define MT2712_PIN_1_EINT1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define MT2712_PIN_1_EINT1__FUNC_EINT1 (MTK_PIN_NO(1) | 1) +#define MT2712_PIN_1_EINT1__FUNC_IR_IN (MTK_PIN_NO(1) | 2) +#define MT2712_PIN_1_EINT1__FUNC_DSIB_TE (MTK_PIN_NO(1) | 3) +#define MT2712_PIN_1_EINT1__FUNC_DIN_D4 (MTK_PIN_NO(1) | 5) + +#define MT2712_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define MT2712_PIN_2_EINT2__FUNC_EINT2 (MTK_PIN_NO(2) | 1) +#define MT2712_PIN_2_EINT2__FUNC_IR_IN (MTK_PIN_NO(2) | 2) +#define MT2712_PIN_2_EINT2__FUNC_LCM_RST1 (MTK_PIN_NO(2) | 3) +#define MT2712_PIN_2_EINT2__FUNC_DIN_D5 (MTK_PIN_NO(2) | 5) + +#define MT2712_PIN_3_EINT3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define MT2712_PIN_3_EINT3__FUNC_EINT3 (MTK_PIN_NO(3) | 1) +#define MT2712_PIN_3_EINT3__FUNC_IR_IN (MTK_PIN_NO(3) | 2) +#define MT2712_PIN_3_EINT3__FUNC_LCM_RST0 (MTK_PIN_NO(3) | 3) +#define MT2712_PIN_3_EINT3__FUNC_DIN_D6 (MTK_PIN_NO(3) | 5) + +#define MT2712_PIN_4_PWM0__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define MT2712_PIN_4_PWM0__FUNC_PWM0 (MTK_PIN_NO(4) | 1) +#define MT2712_PIN_4_PWM0__FUNC_DISP0_PWM (MTK_PIN_NO(4) | 2) +#define MT2712_PIN_4_PWM0__FUNC_DISP1_PWM (MTK_PIN_NO(4) | 3) +#define MT2712_PIN_4_PWM0__FUNC_DIN_CLK (MTK_PIN_NO(4) | 5) + +#define MT2712_PIN_5_PWM1__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define MT2712_PIN_5_PWM1__FUNC_PWM1 (MTK_PIN_NO(5) | 1) +#define MT2712_PIN_5_PWM1__FUNC_DISP1_PWM (MTK_PIN_NO(5) | 2) +#define MT2712_PIN_5_PWM1__FUNC_DISP0_PWM (MTK_PIN_NO(5) | 3) +#define MT2712_PIN_5_PWM1__FUNC_DIN_VSYNC (MTK_PIN_NO(5) | 5) + +#define MT2712_PIN_6_PWM2__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define MT2712_PIN_6_PWM2__FUNC_PWM2 (MTK_PIN_NO(6) | 1) +#define MT2712_PIN_6_PWM2__FUNC_DISP0_PWM (MTK_PIN_NO(6) | 2) +#define MT2712_PIN_6_PWM2__FUNC_DISP1_PWM (MTK_PIN_NO(6) | 3) +#define MT2712_PIN_6_PWM2__FUNC_DIN_HSYNC (MTK_PIN_NO(6) | 5) + +#define MT2712_PIN_7_PWM3__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define MT2712_PIN_7_PWM3__FUNC_PWM3 (MTK_PIN_NO(7) | 1) +#define MT2712_PIN_7_PWM3__FUNC_DISP1_PWM (MTK_PIN_NO(7) | 2) +#define MT2712_PIN_7_PWM3__FUNC_DISP0_PWM (MTK_PIN_NO(7) | 3) +#define MT2712_PIN_7_PWM3__FUNC_DIN_D0 (MTK_PIN_NO(7) | 5) + +#define MT2712_PIN_8_PWM4__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define MT2712_PIN_8_PWM4__FUNC_PWM4 (MTK_PIN_NO(8) | 1) +#define MT2712_PIN_8_PWM4__FUNC_DISP0_PWM (MTK_PIN_NO(8) | 2) +#define MT2712_PIN_8_PWM4__FUNC_DISP1_PWM (MTK_PIN_NO(8) | 3) +#define MT2712_PIN_8_PWM4__FUNC_DSIA_TE (MTK_PIN_NO(8) | 4) +#define MT2712_PIN_8_PWM4__FUNC_DIN_D1 (MTK_PIN_NO(8) | 5) + +#define MT2712_PIN_9_PWM5__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define MT2712_PIN_9_PWM5__FUNC_PWM5 (MTK_PIN_NO(9) | 1) +#define MT2712_PIN_9_PWM5__FUNC_DISP1_PWM (MTK_PIN_NO(9) | 2) +#define MT2712_PIN_9_PWM5__FUNC_DISP0_PWM (MTK_PIN_NO(9) | 3) +#define MT2712_PIN_9_PWM5__FUNC_DSIB_TE (MTK_PIN_NO(9) | 4) +#define MT2712_PIN_9_PWM5__FUNC_DIN_D2 (MTK_PIN_NO(9) | 5) + +#define MT2712_PIN_10_PWM6__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define MT2712_PIN_10_PWM6__FUNC_PWM6 (MTK_PIN_NO(10) | 1) +#define MT2712_PIN_10_PWM6__FUNC_DISP0_PWM (MTK_PIN_NO(10) | 2) +#define MT2712_PIN_10_PWM6__FUNC_DISP1_PWM (MTK_PIN_NO(10) | 3) +#define MT2712_PIN_10_PWM6__FUNC_LCM_RST0 (MTK_PIN_NO(10) | 4) + +#define MT2712_PIN_11_PWM7__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define MT2712_PIN_11_PWM7__FUNC_PWM7 (MTK_PIN_NO(11) | 1) +#define MT2712_PIN_11_PWM7__FUNC_DISP1_PWM (MTK_PIN_NO(11) | 2) +#define MT2712_PIN_11_PWM7__FUNC_DISP0_PWM (MTK_PIN_NO(11) | 3) +#
Re: [PATCH 3/3] pinctrl: add mt2712 pinctrl driver
On Tue, 2017-08-01 at 17:14 +0800, Yingjoe Chen wrote:
>
> Hi Zhiyong,
>
>
>
> On Mon, 2017-07-31 at 16:22 +0800, Zhiyong Tao wrote:
> <...>
> > 3)Add "spec_dir_set" and "spec_dir_get" in "mtk_pinctrl_devdata".
> > 4)Change "spec_dir_set" and add "spec_dir_get" in "pinctrl-mt2701.c"
> > and "pinctrl-mtk-common.c".
>
> I think these deserve another patch.
> Please also explain why we need this.
==> ok, I will separate it in another patch in the next version.
Because we should control another gpio base register for gpio16 and 17
in mt2712 E1. It is special for the direction control in gpio16 and
gpio17.
>
>
> > 5)Change "port_mask" from "7" to "6" for EINT.
>
> I'm assuming this is a bug fix for mt2701?
> If yes, this should be a separate patch.
==> yes, it is a bug fix for mt2701. When I use EINT bothe edge triggle,
offset can't get the offset address which offset address is 1/3/5/7.
I will separate it in another patch in the next version.
>
> > 6)Remove generic pull config condition in "mtk_pconf_set_pull_select".
> > 7)Change "arg" to "MTK_PUPD_SET_R1R0_00" of "mtk_pconf_set_pull_select".
>
> Why we need to change arg?
==> to parse the "bias-disable" property in dts for special pins.
>
>
> >
> > Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
> > ---
> > drivers/pinctrl/mediatek/Kconfig |8 +
> > drivers/pinctrl/mediatek/Makefile |1 +
> > drivers/pinctrl/mediatek/pinctrl-mt2701.c | 21 +-
> > drivers/pinctrl/mediatek/pinctrl-mt2712.c | 670 +
> > drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 16 +-
> > drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 44 +-
> > drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h | 1858
> > +
> > 7 files changed, 2586 insertions(+), 32 deletions(-)
> > create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt2712.c
> > create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h
> >
>
> <...>
>
> > diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2701.c
> > b/drivers/pinctrl/mediatek/pinctrl-mt2701.c
> > index f86f3b3..4a43f5c 100644
> > --- a/drivers/pinctrl/mediatek/pinctrl-mt2701.c
> > +++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c
> > @@ -503,10 +503,26 @@ static void mt2701_spec_pinmux_set(struct regmap
> > *reg, unsigned int pin,
> > regmap_update_bits(reg, mt2701_spec_pinmux[i].offset, mask, value);
> > }
> >
> > -static void mt2701_spec_dir_set(unsigned int *reg_addr, unsigned int pin)
> > +static int mt2701_spec_dir_set(struct mtk_pinctrl *pctl,
> > + unsigned int *reg_addr,
> > + unsigned int pin,
> > + bool input)
> > {
> > if (pin > 175)
> > *reg_addr += 0x10;
> > +
> > + return 0;
> > +}
> > +
> > +static int mt2701_spec_dir_get(struct mtk_pinctrl *pctl,
> > + unsigned int *reg_addr,
> > + unsigned int pin,
> > + bool input)
>
> incorrect prototype?
>
> > +{
> > + if (pin > 175)
> > + *reg_addr += 0x10;
> > +
> > + return 0;
> > }
> >
> > static const struct mtk_pinctrl_devdata mt2701_pinctrl_data = {
> > @@ -520,6 +536,7 @@ static void mt2701_spec_dir_set(unsigned int *reg_addr,
> > unsigned int pin)
> > .spec_ies_smt_set = mt2701_ies_smt_set,
> > .spec_pinmux_set = mt2701_spec_pinmux_set,
> > .spec_dir_set = mt2701_spec_dir_set,
> > + .spec_dir_get = mt2701_spec_dir_get,
> > .dir_offset = 0x,
> > .pullen_offset = 0x0150,
> > .pullsel_offset = 0x0280,
> > @@ -551,7 +568,7 @@ static void mt2701_spec_dir_set(unsigned int *reg_addr,
> > unsigned int pin)
> > .dbnc_ctrl = 0x500,
> > .dbnc_set = 0x600,
> > .dbnc_clr = 0x700,
> > - .port_mask = 6,
> > + .port_mask = 7,
> > .ports = 6,
> > },
> > .ap_num = 169,
> > diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2712.c
> > b/drivers/pinctrl/mediatek/pinctrl-mt2712.c
> > new file mode 100644
> > index 000..c933b75
> > --- /dev/null
> > +++ b/drivers/pinctrl/mediatek/pinctrl-mt2712.c
>
> <...>
>
> > +
> > +static int mt2712_spec_dir_se
Re: [PATCH 0/3] PINCTRL: Mediatek pinctrl driver for mt2712
On Tue, 2017-08-01 at 16:44 +0800, Yingjoe Chen wrote: > On Mon, 2017-07-31 at 16:22 +0800, Zhiyong Tao wrote: > > This series includes three patches: > > 1.Add mt2712 compatible node in binding document. > > 2.Add mt2712 pinctrl device node. > > 3.Add mt2712 pinctrl driver. > > > > Zhiyong Tao (3): > > dt-bindings: pinctrl: mt2712: add binding document > > arm64: dts: mt2712: add pintcrl device node. > > pinctrl: add mt2712 pinctrl driver > > > > .../devicetree/bindings/pinctrl/pinctrl-mt65xx.txt |1 + > > arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h | 1014 +++ > > arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 18 + > > mt2712e.dtsi doesn't exists in v4.13-rc1. > What's the base for this series? > > > > ==> This patch is based on http://lists.infradead.org/pipermail/linux-mediatek/2017-July/009618.html I forgot to add the comment, I will add it in the next version. Thanks.
[PATCH 1/3] dt-bindings: adc: mt7622: add binding document
The commit adds mt7622 compatible node in binding document. Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com> --- .../devicetree/bindings/iio/adc/mt6577_auxadc.txt |1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt b/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt index 68c45cb..e6aa30a 100644 --- a/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt +++ b/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt @@ -13,6 +13,7 @@ Required properties: - compatible: Should be one of: - "mediatek,mt2701-auxadc": For MT2701 family of SoCs - "mediatek,mt8173-auxadc": For MT8173 family of SoCs +- "mediatek,mt7622-auxadc": For MT7622 family of SoCs - reg: Address range of the AUXADC unit. - clocks: Should contain a clock specifier for each entry in clock-names - clock-names: Should contain "main". -- 1.7.9.5
[PATCH 2/3] iio: adc: mt7622: add support for suspend/resume.
This patch supports auxadc suspend/resume flow.
Disable auxadc clk and power in suspend function.
Enable axuadc clk and power in resume function.
Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
---
drivers/iio/adc/mt6577_auxadc.c | 37 +
1 file changed, 37 insertions(+)
diff --git a/drivers/iio/adc/mt6577_auxadc.c b/drivers/iio/adc/mt6577_auxadc.c
index 2d104c8..2dd7c74 100644
--- a/drivers/iio/adc/mt6577_auxadc.c
+++ b/drivers/iio/adc/mt6577_auxadc.c
@@ -184,6 +184,37 @@ static int mt6577_auxadc_read_raw(struct iio_dev
*indio_dev,
.read_raw = _auxadc_read_raw,
};
+static int mt6577_auxadc_resume(struct device *dev)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev);
+ int ret;
+
+ ret = clk_prepare_enable(adc_dev->adc_clk);
+ if (ret) {
+ pr_err("failed to enable auxadc clock\n");
+ return ret;
+ }
+
+ mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
+ MT6577_AUXADC_PDN_EN, 0);
+ mdelay(MT6577_AUXADC_POWER_READY_MS);
+
+ return 0;
+}
+
+static int mt6577_auxadc_suspend(struct device *dev)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev);
+
+ mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
+ 0, MT6577_AUXADC_PDN_EN);
+ clk_disable_unprepare(adc_dev->adc_clk);
+
+ return 0;
+}
+
static int mt6577_auxadc_probe(struct platform_device *pdev)
{
struct mt6577_auxadc_device *adc_dev;
@@ -269,6 +300,11 @@ static int mt6577_auxadc_remove(struct platform_device
*pdev)
return 0;
}
+static const struct dev_pm_ops mt6577_auxadc_pm_ops = {
+ .suspend = mt6577_auxadc_suspend,
+ .resume = mt6577_auxadc_resume,
+};
+
static const struct of_device_id mt6577_auxadc_of_match[] = {
{ .compatible = "mediatek,mt2701-auxadc", },
{ .compatible = "mediatek,mt8173-auxadc", },
@@ -280,6 +316,7 @@ static int mt6577_auxadc_remove(struct platform_device
*pdev)
.driver = {
.name = "mt6577-auxadc",
.of_match_table = mt6577_auxadc_of_match,
+ .pm = _auxadc_pm_ops,
},
.probe = mt6577_auxadc_probe,
.remove = mt6577_auxadc_remove,
--
1.7.9.5
[PATCH 3/3] iio: adc: mt7622: Add compatible node for mt7622.
This commit adds mt7622 compatible node.
Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
---
drivers/iio/adc/mt6577_auxadc.c |1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iio/adc/mt6577_auxadc.c b/drivers/iio/adc/mt6577_auxadc.c
index 2dd7c74..4a2cd9e 100644
--- a/drivers/iio/adc/mt6577_auxadc.c
+++ b/drivers/iio/adc/mt6577_auxadc.c
@@ -308,6 +308,7 @@ static int mt6577_auxadc_remove(struct platform_device
*pdev)
static const struct of_device_id mt6577_auxadc_of_match[] = {
{ .compatible = "mediatek,mt2701-auxadc", },
{ .compatible = "mediatek,mt8173-auxadc", },
+ { .compatible = "mediatek,mt7622-auxadc", },
{ }
};
MODULE_DEVICE_TABLE(of, mt6577_auxadc_of_match);
--
1.7.9.5
[PATCH 0/3] ADC: Mediatek auxadc driver for mt7622
These patches are first version of Mediatek auxadc driver for mt7622. These patches include three patches. The First patch adds mt7622 compatible node in binding document. The second patch adds support for suspend/resume. The last patch adds mt7622 compatible node in auxadc driver. Zhiyong Tao (3): dt-bindings: adc: mt7622: add binding document iio: adc: mt7622: add support for suspend/resume. iio: adc: mt7622: Add compatible node for mt7622. .../devicetree/bindings/iio/adc/mt6577_auxadc.txt |1 + drivers/iio/adc/mt6577_auxadc.c| 38 2 files changed, 39 insertions(+) -- 1.7.9.5
[PATCH v2 1/3] dt-bindings: adc: mt7622: add binding document
The commit adds mt7622 compatible node in binding document. Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com> --- .../devicetree/bindings/iio/adc/mt6577_auxadc.txt |1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt b/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt index 68c45cb..64dc484 100644 --- a/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt +++ b/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt @@ -12,6 +12,7 @@ for the Thermal Controller which holds a phandle to the AUXADC. Required properties: - compatible: Should be one of: - "mediatek,mt2701-auxadc": For MT2701 family of SoCs +- "mediatek,mt7622-auxadc": For MT7622 family of SoCs - "mediatek,mt8173-auxadc": For MT8173 family of SoCs - reg: Address range of the AUXADC unit. - clocks: Should contain a clock specifier for each entry in clock-names -- 1.7.9.5
[PATCH v2 0/3] ADC: Mediatek auxadc driver for mt7622
This series includes three patches: 1.Add mt7622 compatible node in binding document. 2.Add support for suspend/resume. 3.Add mt7622 compatible node in auxadc driver. Changes in patch v2: 1).Change compatible node as numeric order perhaps. 2).Add "CONFIG_PM_SLEEP" and "__maybe_unused" for suspend/resume. 3).Change "dev_pm_ops" to "SIMPLE_DEV_PM_OPS". Zhiyong Tao (3): dt-bindings: adc: mt7622: add binding document iio: adc: mt7622: add support for suspend/resume. iio: adc: mt7622: Add compatible node for mt7622. .../devicetree/bindings/iio/adc/mt6577_auxadc.txt |1 + drivers/iio/adc/mt6577_auxadc.c| 39 2 files changed, 40 insertions(+) -- 1.7.9.5
[PATCH v2 2/3] iio: adc: mt7622: add support for suspend/resume.
This patch supports auxadc suspend/resume flow.
Disable auxadc clk and power in suspend function.
Enable axuadc clk and power in resume function.
Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
---
drivers/iio/adc/mt6577_auxadc.c | 38 ++
1 file changed, 38 insertions(+)
diff --git a/drivers/iio/adc/mt6577_auxadc.c b/drivers/iio/adc/mt6577_auxadc.c
index 2d104c8..c174b73 100644
--- a/drivers/iio/adc/mt6577_auxadc.c
+++ b/drivers/iio/adc/mt6577_auxadc.c
@@ -184,6 +184,39 @@ static int mt6577_auxadc_read_raw(struct iio_dev
*indio_dev,
.read_raw = _auxadc_read_raw,
};
+#ifdef CONFIG_PM_SLEEP
+static int __maybe_unused mt6577_auxadc_resume(struct device *dev)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev);
+ int ret;
+
+ ret = clk_prepare_enable(adc_dev->adc_clk);
+ if (ret) {
+ pr_err("failed to enable auxadc clock\n");
+ return ret;
+ }
+
+ mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
+ MT6577_AUXADC_PDN_EN, 0);
+ mdelay(MT6577_AUXADC_POWER_READY_MS);
+
+ return 0;
+}
+
+static int __maybe_unused mt6577_auxadc_suspend(struct device *dev)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev);
+
+ mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
+ 0, MT6577_AUXADC_PDN_EN);
+ clk_disable_unprepare(adc_dev->adc_clk);
+
+ return 0;
+}
+#endif
+
static int mt6577_auxadc_probe(struct platform_device *pdev)
{
struct mt6577_auxadc_device *adc_dev;
@@ -269,6 +302,10 @@ static int mt6577_auxadc_remove(struct platform_device
*pdev)
return 0;
}
+static SIMPLE_DEV_PM_OPS(mt6577_auxadc_pm_ops,
+mt6577_auxadc_suspend,
+mt6577_auxadc_resume);
+
static const struct of_device_id mt6577_auxadc_of_match[] = {
{ .compatible = "mediatek,mt2701-auxadc", },
{ .compatible = "mediatek,mt8173-auxadc", },
@@ -280,6 +317,7 @@ static int mt6577_auxadc_remove(struct platform_device
*pdev)
.driver = {
.name = "mt6577-auxadc",
.of_match_table = mt6577_auxadc_of_match,
+ .pm = _auxadc_pm_ops,
},
.probe = mt6577_auxadc_probe,
.remove = mt6577_auxadc_remove,
--
1.7.9.5
[PATCH v2 3/3] iio: adc: mt7622: Add compatible node for mt7622.
This commit adds mt7622 compatible node.
Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
---
drivers/iio/adc/mt6577_auxadc.c |1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iio/adc/mt6577_auxadc.c b/drivers/iio/adc/mt6577_auxadc.c
index c174b73..4224fc0 100644
--- a/drivers/iio/adc/mt6577_auxadc.c
+++ b/drivers/iio/adc/mt6577_auxadc.c
@@ -308,6 +308,7 @@ static SIMPLE_DEV_PM_OPS(mt6577_auxadc_pm_ops,
static const struct of_device_id mt6577_auxadc_of_match[] = {
{ .compatible = "mediatek,mt2701-auxadc", },
+ { .compatible = "mediatek,mt7622-auxadc", },
{ .compatible = "mediatek,mt8173-auxadc", },
{ }
};
--
1.7.9.5
Re: [PATCH 3/3] iio: adc: mt7622: Add compatible node for mt7622.
On Sat, 2017-06-24 at 21:02 +0100, Jonathan Cameron wrote:
> On Thu, 22 Jun 2017 13:44:34 +0800
> Zhiyong Tao <zhiyong@mediatek.com> wrote:
>
> > This commit adds mt7622 compatible node.
> >
> > Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
> > ---
> > drivers/iio/adc/mt6577_auxadc.c |1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/iio/adc/mt6577_auxadc.c
> > b/drivers/iio/adc/mt6577_auxadc.c
> > index 2dd7c74..4a2cd9e 100644
> > --- a/drivers/iio/adc/mt6577_auxadc.c
> > +++ b/drivers/iio/adc/mt6577_auxadc.c
> > @@ -308,6 +308,7 @@ static int mt6577_auxadc_remove(struct platform_device
> > *pdev)
> > static const struct of_device_id mt6577_auxadc_of_match[] = {
> > { .compatible = "mediatek,mt2701-auxadc", },
> > { .compatible = "mediatek,mt8173-auxadc", },
> > + { .compatible = "mediatek,mt7622-auxadc", },
> Keep them in numeric order perhaps?
>
> Might become a worthwhile step if this logic gets used for lot more parts in
> future!
>
> Jonathan
==>Ok, we will change them in numeric order perhaps in v2.
Thanks.
> > { }
> > };
> > MODULE_DEVICE_TABLE(of, mt6577_auxadc_of_match);
>
Re: [PATCH 2/3] iio: adc: mt7622: add support for suspend/resume.
On Sat, 2017-06-24 at 21:00 +0100, Jonathan Cameron wrote:
> On Thu, 22 Jun 2017 13:44:33 +0800
> Zhiyong Tao <zhiyong@mediatek.com> wrote:
>
> > This patch supports auxadc suspend/resume flow.
> > Disable auxadc clk and power in suspend function.
> > Enable axuadc clk and power in resume function.
> >
> > Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
> Worth handling the cases where power management is not configured into the
> kernel properly.
>
> So a few minor suggestions. Otherwise looks good to me.
> > ---
> > drivers/iio/adc/mt6577_auxadc.c | 37
> > +
> > 1 file changed, 37 insertions(+)
> >
> > diff --git a/drivers/iio/adc/mt6577_auxadc.c
> > b/drivers/iio/adc/mt6577_auxadc.c
> > index 2d104c8..2dd7c74 100644
> > --- a/drivers/iio/adc/mt6577_auxadc.c
> > +++ b/drivers/iio/adc/mt6577_auxadc.c
> > @@ -184,6 +184,37 @@ static int mt6577_auxadc_read_raw(struct iio_dev
> > *indio_dev,
> > .read_raw = _auxadc_read_raw,
> > };
> >
> > +static int mt6577_auxadc_resume(struct device *dev)
> > +{
> > + struct iio_dev *indio_dev = dev_get_drvdata(dev);
> > + struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev);
> > + int ret;
> > +
> > + ret = clk_prepare_enable(adc_dev->adc_clk);
> > + if (ret) {
> > + pr_err("failed to enable auxadc clock\n");
> > + return ret;
> > + }
> > +
> > + mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
> > + MT6577_AUXADC_PDN_EN, 0);
> > + mdelay(MT6577_AUXADC_POWER_READY_MS);
> > +
> > + return 0;
> > +}
> > +
> > +static int mt6577_auxadc_suspend(struct device *dev)
> Mark these __maybe_unused for the CONFIG_PM but not CONFIG_PM_SLEEP case.
==> ok, We will add CONFIG_PM_SLEEP for the suspend/resume case in v2.
thanks!
> > +{
> > + struct iio_dev *indio_dev = dev_get_drvdata(dev);
> > + struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev);
> > +
> > + mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
> > + 0, MT6577_AUXADC_PDN_EN);
> > + clk_disable_unprepare(adc_dev->adc_clk);
> > +
> > + return 0;
> > +}
> > +
> > static int mt6577_auxadc_probe(struct platform_device *pdev)
> > {
> > struct mt6577_auxadc_device *adc_dev;
> > @@ -269,6 +300,11 @@ static int mt6577_auxadc_remove(struct platform_device
> > *pdev)
> > return 0;
> > }
> >
> > +static const struct dev_pm_ops mt6577_auxadc_pm_ops = {
> > + .suspend = mt6577_auxadc_suspend,
> > + .resume = mt6577_auxadc_resume,
> > +};
> > +
> Use the SIMPLE_SYSTEM_PM_OPS macro to make these assignments magically go away
> if PM_CONFIG_SLEEP is not defined.
==> ok, We will use SIMPLE_DEV_PM_OPS macro to change it in v2. Thanks.
>> static const struct of_device_id mt6577_auxadc_of_match[] = {
> > { .compatible = "mediatek,mt2701-auxadc", },
> > { .compatible = "mediatek,mt8173-auxadc", },
> > @@ -280,6 +316,7 @@ static int mt6577_auxadc_remove(struct platform_device
> > *pdev)
> > .driver = {
> > .name = "mt6577-auxadc",
> > .of_match_table = mt6577_auxadc_of_match,
> > + .pm = _auxadc_pm_ops,
> > },
> > .probe = mt6577_auxadc_probe,
> > .remove = mt6577_auxadc_remove,
>
Re: [PATCH 1/3] dt-bindings: adc: mt7622: add binding document
On Sat, 2017-06-24 at 21:02 +0100, Jonathan Cameron wrote: > On Thu, 22 Jun 2017 13:44:32 +0800 > Zhiyong Tao <zhiyong@mediatek.com> wrote: > > > The commit adds mt7622 compatible node in binding document. > > > > Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com> > > --- > > .../devicetree/bindings/iio/adc/mt6577_auxadc.txt |1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt > > b/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt > > index 68c45cb..e6aa30a 100644 > > --- a/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt > > +++ b/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt > > @@ -13,6 +13,7 @@ Required properties: > >- compatible: Should be one of: > > - "mediatek,mt2701-auxadc": For MT2701 family of SoCs > > - "mediatek,mt8173-auxadc": For MT8173 family of SoCs > > +- "mediatek,mt7622-auxadc": For MT7622 family of SoCs > numeric order? ==> yes, we have changed it as numeric order in v2. Thanks. > >- reg: Address range of the AUXADC unit. > >- clocks: Should contain a clock specifier for each entry in clock-names > >- clock-names: Should contain "main". >
[PATCH 1/3] dt-bindings: adc: mt2712: add binding document
The commit adds mt2712 compatible node in binding document. Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com> --- .../devicetree/bindings/iio/adc/mt6577_auxadc.txt |1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt b/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt index 64dc484..0df9bef 100644 --- a/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt +++ b/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt @@ -12,6 +12,7 @@ for the Thermal Controller which holds a phandle to the AUXADC. Required properties: - compatible: Should be one of: - "mediatek,mt2701-auxadc": For MT2701 family of SoCs +- "mediatek,mt2712-auxadc": For MT2712 family of SoCs - "mediatek,mt7622-auxadc": For MT7622 family of SoCs - "mediatek,mt8173-auxadc": For MT8173 family of SoCs - reg: Address range of the AUXADC unit. -- 1.7.9.5
[PATCH 2/3] iio: adc: mt2712: Add compatible node for mt2712.
This commit adds mt2712 compatible node.
Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
---
drivers/iio/adc/mt6577_auxadc.c |1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iio/adc/mt6577_auxadc.c b/drivers/iio/adc/mt6577_auxadc.c
index 414cf44..70bfa1e 100644
--- a/drivers/iio/adc/mt6577_auxadc.c
+++ b/drivers/iio/adc/mt6577_auxadc.c
@@ -306,6 +306,7 @@ static SIMPLE_DEV_PM_OPS(mt6577_auxadc_pm_ops,
static const struct of_device_id mt6577_auxadc_of_match[] = {
{ .compatible = "mediatek,mt2701-auxadc", },
+ { .compatible = "mediatek,mt2712-auxadc", },
{ .compatible = "mediatek,mt7622-auxadc", },
{ .compatible = "mediatek,mt8173-auxadc", },
{ }
--
1.7.9.5
[PATCH 3/3] arm64: dts: mt2712: Add auxadc device node.
Add auxadc device node for MT2712.
Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
---
This patch dependents on "Mediatek MT2712 clock and scpsys support"[1].
Please accept this patch together with [1].
[1]http://lists.infradead.org/pipermail/linux-mediatek/2017-September/010461.html
---
arch/arm64/boot/dts/mediatek/mt2712-evb.dts |4
arch/arm64/boot/dts/mediatek/mt2712e.dtsi |9 +
2 files changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
index 14163b9..76cbf4a 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
@@ -28,6 +28,10 @@
};
};
+ {
+ status = "okay";
+};
+
{
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index 3232e4e..bf65c92 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -225,6 +225,15 @@
(GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ auxadc: adc@11001000 {
+ compatible = "mediatek,mt2712-auxadc";
+ reg = <0 0x11001000 0 0x1000>;
+ clocks = < CLK_PERI_AUXADC>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,mt2712-uart",
"mediatek,mt6577-uart";
--
1.7.9.5
[PATCH 0/3] AUXADC: Mediatek auxadc driver for mt2712
This series includes three patches: 1.Add mt2712 auxadc compatible node in binding document. 2.Add mt2712 auxadc compatible node in "mt6577_auxadc.c". 2.Add mt2712 auxadc device node. Zhiyong Tao (3): dt-bindings: adc: mt2712: add binding document iio: adc: mt2712: Add compatible node for mt2712. arm64: dts: mt2712: Add auxadc device node. .../devicetree/bindings/iio/adc/mt6577_auxadc.txt |1 + arch/arm64/boot/dts/mediatek/mt2712-evb.dts|4 arch/arm64/boot/dts/mediatek/mt2712e.dtsi |9 + drivers/iio/adc/mt6577_auxadc.c|1 + 4 files changed, 15 insertions(+) -- 1.7.9.5
Re: [PATCH 3/3] pinctrl: add mt2712 pinctrl driver
On Thu, 2017-08-03 at 10:00 +0800, Yingjoe Chen wrote:
> On Wed, 2017-08-02 at 14:03 +0800, Zhiyong Tao wrote:
> > On Tue, 2017-08-01 at 17:14 +0800, Yingjoe Chen wrote:
> > >
> > > Hi Zhiyong,
> > >
> > >
> > >
> > > On Mon, 2017-07-31 at 16:22 +0800, Zhiyong Tao wrote:
> > > <...>
> > > > 3)Add "spec_dir_set" and "spec_dir_get" in "mtk_pinctrl_devdata".
> > > > 4)Change "spec_dir_set" and add "spec_dir_get" in "pinctrl-mt2701.c"
> > > > and "pinctrl-mtk-common.c".
> > >
> > > I think these deserve another patch.
> > > Please also explain why we need this.
> >
> > ==> ok, I will separate it in another patch in the next version.
> > Because we should control another gpio base register for gpio16 and 17
> > in mt2712 E1. It is special for the direction control in gpio16 and
> > gpio17.
> > >
> > >
> > > > 5)Change "port_mask" from "7" to "6" for EINT.
> > >
> > > I'm assuming this is a bug fix for mt2701?
> > > If yes, this should be a separate patch.
> >
> > ==> yes, it is a bug fix for mt2701. When I use EINT bothe edge triggle,
> > offset can't get the offset address which offset address is 1/3/5/7.
> > I will separate it in another patch in the next version.
> > >
> > > > 6)Remove generic pull config condition in "mtk_pconf_set_pull_select".
> > > > 7)Change "arg" to "MTK_PUPD_SET_R1R0_00" of "mtk_pconf_set_pull_select".
> > >
> > > Why we need to change arg?
> >
> > ==> to parse the "bias-disable" property in dts for special pins.
> >
> > >
> > >
> > > >
> > > > Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
> > > > ---
> > > > drivers/pinctrl/mediatek/Kconfig |8 +
> > > > drivers/pinctrl/mediatek/Makefile |1 +
> > > > drivers/pinctrl/mediatek/pinctrl-mt2701.c | 21 +-
> > > > drivers/pinctrl/mediatek/pinctrl-mt2712.c | 670 +
> > > > drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 16 +-
> > > > drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 44 +-
> > > > drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h | 1858
> > > > +
> > > > 7 files changed, 2586 insertions(+), 32 deletions(-)
> > > > create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt2712.c
> > > > create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h
> > > >
> > >
> > > <...>
> > >
> > > > diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2701.c
> > > > b/drivers/pinctrl/mediatek/pinctrl-mt2701.c
> > > > index f86f3b3..4a43f5c 100644
> > > > --- a/drivers/pinctrl/mediatek/pinctrl-mt2701.c
> > > > +++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c
> > > > @@ -503,10 +503,26 @@ static void mt2701_spec_pinmux_set(struct regmap
> > > > *reg, unsigned int pin,
> > > > regmap_update_bits(reg, mt2701_spec_pinmux[i].offset, mask,
> > > > value);
> > > > }
> > > >
> > > > -static void mt2701_spec_dir_set(unsigned int *reg_addr, unsigned int
> > > > pin)
> > > > +static int mt2701_spec_dir_set(struct mtk_pinctrl *pctl,
> > > > + unsigned int *reg_addr,
> > > > + unsigned int pin,
> > > > + bool input)
> > > > {
> > > > if (pin > 175)
> > > > *reg_addr += 0x10;
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +static int mt2701_spec_dir_get(struct mtk_pinctrl *pctl,
> > > > + unsigned int *reg_addr,
> > > > + unsigned int pin,
> > > > + bool input)
> > >
> > > incorrect prototype?
> > >
> > > > +{
> > > > + if (pin > 175)
> > > > + *reg_addr += 0x10;
> > > > +
> > > > + return 0;
> > > > }
> > > >
> > > > static const struct mtk_pinctrl_devdata mt2701_pinctrl_data = {
> > > > @@ -520,6 +536,7 @
[PATCH v2 1/4] arm64: dts: mt2712: add pintcrl file
This patch adds pinctrl file for mt2712. Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h | 1129 + 1 file changed, 1129 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h diff --git a/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h new file mode 100644 index 000..44f8ca2 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h @@ -0,0 +1,1129 @@ +/* + * Copyright (C) 2015 MediaTek Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __DTS_MT2712_PINFUNC_H +#define __DTS_MT2712_PINFUNC_H + +#include + +#define MT2712_PIN_0_EINT0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define MT2712_PIN_0_EINT0__FUNC_EINT0 (MTK_PIN_NO(0) | 1) +#define MT2712_PIN_0_EINT0__FUNC_MBIST_DIAG_SCANOUT (MTK_PIN_NO(0) | 2) +#define MT2712_PIN_0_EINT0__FUNC_DSIA_TE (MTK_PIN_NO(0) | 3) +#define MT2712_PIN_0_EINT0__FUNC_DSIC_TE (MTK_PIN_NO(0) | 4) +#define MT2712_PIN_0_EINT0__FUNC_DIN_D3 (MTK_PIN_NO(0) | 5) +#define MT2712_PIN_0_EINT0__FUNC_PURE_HW_PROTECT (MTK_PIN_NO(0) | 6) + +#define MT2712_PIN_1_EINT1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define MT2712_PIN_1_EINT1__FUNC_EINT1 (MTK_PIN_NO(1) | 1) +#define MT2712_PIN_1_EINT1__FUNC_IR_IN (MTK_PIN_NO(1) | 2) +#define MT2712_PIN_1_EINT1__FUNC_DSIB_TE (MTK_PIN_NO(1) | 3) +#define MT2712_PIN_1_EINT1__FUNC_DSID_TE (MTK_PIN_NO(1) | 4) +#define MT2712_PIN_1_EINT1__FUNC_DIN_D4 (MTK_PIN_NO(1) | 5) + +#define MT2712_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define MT2712_PIN_2_EINT2__FUNC_EINT2 (MTK_PIN_NO(2) | 1) +#define MT2712_PIN_2_EINT2__FUNC_IR_IN (MTK_PIN_NO(2) | 2) +#define MT2712_PIN_2_EINT2__FUNC_LCM_RST1 (MTK_PIN_NO(2) | 3) +#define MT2712_PIN_2_EINT2__FUNC_DIN_D5 (MTK_PIN_NO(2) | 5) + +#define MT2712_PIN_3_EINT3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define MT2712_PIN_3_EINT3__FUNC_EINT3 (MTK_PIN_NO(3) | 1) +#define MT2712_PIN_3_EINT3__FUNC_IR_IN (MTK_PIN_NO(3) | 2) +#define MT2712_PIN_3_EINT3__FUNC_LCM_RST0 (MTK_PIN_NO(3) | 3) +#define MT2712_PIN_3_EINT3__FUNC_DIN_D6 (MTK_PIN_NO(3) | 5) + +#define MT2712_PIN_4_PWM0__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define MT2712_PIN_4_PWM0__FUNC_PWM0 (MTK_PIN_NO(4) | 1) +#define MT2712_PIN_4_PWM0__FUNC_DISP0_PWM (MTK_PIN_NO(4) | 2) +#define MT2712_PIN_4_PWM0__FUNC_DISP1_PWM (MTK_PIN_NO(4) | 3) +#define MT2712_PIN_4_PWM0__FUNC_DIN_CLK (MTK_PIN_NO(4) | 5) + +#define MT2712_PIN_5_PWM1__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define MT2712_PIN_5_PWM1__FUNC_PWM1 (MTK_PIN_NO(5) | 1) +#define MT2712_PIN_5_PWM1__FUNC_DISP1_PWM (MTK_PIN_NO(5) | 2) +#define MT2712_PIN_5_PWM1__FUNC_DISP0_PWM (MTK_PIN_NO(5) | 3) +#define MT2712_PIN_5_PWM1__FUNC_DIN_VSYNC (MTK_PIN_NO(5) | 5) + +#define MT2712_PIN_6_PWM2__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define MT2712_PIN_6_PWM2__FUNC_PWM2 (MTK_PIN_NO(6) | 1) +#define MT2712_PIN_6_PWM2__FUNC_DISP0_PWM (MTK_PIN_NO(6) | 2) +#define MT2712_PIN_6_PWM2__FUNC_DISP1_PWM (MTK_PIN_NO(6) | 3) +#define MT2712_PIN_6_PWM2__FUNC_DISP2_PWM (MTK_PIN_NO(6) | 4) +#define MT2712_PIN_6_PWM2__FUNC_DIN_HSYNC (MTK_PIN_NO(6) | 5) + +#define MT2712_PIN_7_PWM3__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define MT2712_PIN_7_PWM3__FUNC_PWM3 (MTK_PIN_NO(7) | 1) +#define MT2712_PIN_7_PWM3__FUNC_DISP1_PWM (MTK_PIN_NO(7) | 2) +#define MT2712_PIN_7_PWM3__FUNC_DISP0_PWM (MTK_PIN_NO(7) | 3) +#define MT2712_PIN_7_PWM3__FUNC_LCM_RST2 (MTK_PIN_NO(7) | 4) +#define MT2712_PIN_7_PWM3__FUNC_DIN_D0 (MTK_PIN_NO(7) | 5) + +#define MT2712_PIN_8_PWM4__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define MT2712_PIN_8_PWM4__FUNC_PWM4 (MTK_PIN_NO(8) | 1) +#define MT2712_PIN_8_PWM4__FUNC_DISP0_PWM (MTK_PIN_NO(8) | 2) +#define MT2712_PIN_8_PWM4__FUNC_DISP1_PWM (MTK_PIN_NO(8) | 3) +#define MT2712_PIN_8_PWM4__FUNC_DSIA_TE (MTK_PIN_NO(8) | 4) +#define MT2712_PIN_8_PWM4__FUNC_DIN_D1 (MTK_PIN_NO(8) | 5) + +#define MT2712_PIN_9_PWM5__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define MT2712_PIN_9_PWM5__FUNC_PWM5 (MTK_PIN_NO(9) | 1) +#define MT2712_PIN_9_PWM5__FUNC_DISP1_PWM (MTK_PIN_NO(9) | 2) +#define MT2712_PIN_9_PWM5__FUNC_DISP0_PWM (MTK_PIN_NO(9) | 3) +#define MT2712_PIN_9_PWM5__FUNC_DSIB_TE (MTK_PIN_NO(9) | 4) +#define MT2712_PIN_9_PWM5__FUNC_DIN_D2 (MTK_PIN_NO(9) | 5) + +#define MT2712_PIN_10_PWM6__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define MT2712_PIN_10_PWM6__FUNC_PWM6 (MTK_PIN_NO(10) | 1) +#define MT2712_PIN_10_PWM6__FUNC_DISP0_PWM (MTK_PIN_NO(10) | 2) +#define MT2712_PIN_10_PWM6__FUNC_DISP1_PWM (MTK_PIN_NO(10) | 3) +#define MT2712_PIN_10_PWM6__FUNC_LCM_RST0 (MTK_PIN_NO(10) | 4) + +#define MT2712_PIN_11_PWM7__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#
[PATCH v2 0/4] PINCTRL: Mediatek pinctrl driver for mt2712
This series includes four patches: 1.Add mt2712 pintcrl head file 2.Add mt2712 pinctrl device node. 3.Add mt2712 pinctrl driver. 4.Support bias-disable of generic and special pins simultaneously Changes in patch v2: 1)Separate patch4 for supporting bias-disable of generic and special pins. 2)GPIO16~17 direction setting is changed as generic pins in mt2712 E2, So remove GPIO16~17 special direction setting and remove apmixedsys node in pinctrl device node. 3)Add pinmux define in "mt2712-pinfunc.h" and "pinctrl-mtk-mt2712.h" for mt2712 E2 design. Zhiyong Tao (4): arm64: dts: mt2712: add pintcrl file arm64: dts: mt2712: add pintcrl device node. pinctrl: add mt2712 pinctrl driver pintcrl: support bias-disable of generic and special pins simultaneously arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h | 1129 ++ arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 18 + drivers/pinctrl/mediatek/Kconfig |7 + drivers/pinctrl/mediatek/Makefile |1 + drivers/pinctrl/mediatek/pinctrl-mt2712.c | 639 drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 13 +- drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h | 1973 + 7 files changed, 3778 insertions(+), 2 deletions(-) create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt2712.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h -- 1.8.1.1.dirty
[PATCH v2 3/4] pinctrl: add mt2712 pinctrl driver
The commit includes mt2712 pinctrl driver.
Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
---
drivers/pinctrl/mediatek/Kconfig |7 +
drivers/pinctrl/mediatek/Makefile |1 +
drivers/pinctrl/mediatek/pinctrl-mt2712.c | 639
drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h | 1973 +
4 files changed, 2620 insertions(+)
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt2712.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 3e59874..b24bc76 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -32,6 +32,13 @@ config PINCTRL_MT8127
select PINCTRL_MTK
# For ARMv8 SoCs
+config PINCTRL_MT2712
+ bool "Mediatek MT2712 pin control"
+ depends on OF
+ depends on ARM64 || COMPILE_TEST
+ default ARM64 && ARCH_MEDIATEK
+ select PINCTRL_MTK
+
config PINCTRL_MT7622
bool "MediaTek MT7622 pin control"
depends on OF
diff --git a/drivers/pinctrl/mediatek/Makefile
b/drivers/pinctrl/mediatek/Makefile
index ed7d2b2..7959e77 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
# SoC Drivers
obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o
+obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o
obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2712.c
b/drivers/pinctrl/mediatek/pinctrl-mt2712.c
new file mode 100644
index 000..b6ae71b
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt2712.c
@@ -0,0 +1,639 @@
+/*
+ * Copyright (c) 2014-2015 MediaTek Inc.
+ * Author: Hongzhou.Yang <hongzhou.y...@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pinctrl-mtk-common.h"
+#include "pinctrl-mtk-mt2712.h"
+
+static const struct mtk_pin_spec_pupd_set_samereg mt2712_spec_pupd[] = {
+ MTK_PIN_PUPD_SPEC_SR(18, 0xe50, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(19, 0xe60, 12, 11, 10),
+ MTK_PIN_PUPD_SPEC_SR(20, 0xe50, 5, 4, 3),
+ MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 15, 14, 13),
+ MTK_PIN_PUPD_SPEC_SR(22, 0xe50, 8, 7, 6),
+ MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 2, 1, 0),
+
+ MTK_PIN_PUPD_SPEC_SR(30, 0xf30, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(31, 0xf30, 6, 5, 4),
+ MTK_PIN_PUPD_SPEC_SR(32, 0xf30, 10, 9, 8),
+ MTK_PIN_PUPD_SPEC_SR(33, 0xf30, 14, 13, 12),
+ MTK_PIN_PUPD_SPEC_SR(34, 0xf40, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(35, 0xf40, 6, 5, 4),
+ MTK_PIN_PUPD_SPEC_SR(36, 0xf40, 10, 9, 8),
+ MTK_PIN_PUPD_SPEC_SR(37, 0xc40, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(38, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(39, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(40, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(41, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(42, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(43, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(44, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(45, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(46, 0xc50, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(47, 0xda0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(48, 0xd90, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(49, 0xdf0, 14, 13, 12),
+ MTK_PIN_PUPD_SPEC_SR(50, 0xdf0, 10, 9, 8),
+ MTK_PIN_PUPD_SPEC_SR(51, 0xdf0, 6, 5, 4),
+ MTK_PIN_PUPD_SPEC_SR(52, 0xdf0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(53, 0xd50, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(54, 0xd80, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(55, 0xe00, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(56, 0xd40, 2, 1, 0),
+
+ MTK_PIN_PUPD_SPEC_SR(63, 0xc80, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(64, 0xdb0, 14, 13, 12),
+ MTK_PIN_PUPD_SPEC_SR(65, 0xdb0, 6, 5, 4),
+ MTK_PIN_PUPD_SPEC_SR(66, 0xdb0, 10, 9, 8),
+ MTK_PIN_PUPD_SPEC_SR(67, 0xcd0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(68, 0xdb0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(69, 0xc90, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(70, 0xcc0, 2, 1, 0),
+
+ MTK_PIN_PUPD_SPEC_SR(89, 0xce0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(90, 0xdd0, 14, 13, 12),
+ MTK_PIN_PUPD_SPEC_SR(91, 0xdd0, 10, 9, 8),
+ MTK_PIN_PUPD_SPEC_SR(92, 0xdd0, 6, 5, 4),
+ MTK_PIN_PU
[PATCH v2 2/4] arm64: dts: mt2712: add pintcrl device node.
This patch adds pintcrl device node for mt2712.
Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index d7688bc..fb3b051 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -9,6 +9,7 @@
#include
#include
#include
+#include "mt2712-pinfunc.h"
/ {
compatible = "mediatek,mt2712";
@@ -258,6 +259,23 @@
#clock-cells = <1>;
};
+ syscfg_pctl_a: syscfg_pctl_a@10005000 {
+ compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon";
+ reg = <0 0x10005000 0 0x1000>;
+ };
+
+ pio: pinctrl@10005000 {
+ compatible = "mediatek,mt2712-pinctrl";
+ reg = <0 0x1000b000 0 0x1000>;
+ mediatek,pctl-regmap = <_pctl_a>;
+ pins-are-numbered;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = ;
+ };
+
scpsys: scpsys@10006000 {
compatible = "mediatek,mt2712-scpsys", "syscon";
#power-domain-cells = <1>;
--
1.9.1
[PATCH v2 4/4] pintcrl: support bias-disable of generic and special pins simultaneously
For generic pins, parameter "arg" is 0 or 1.
For special pins, bias-disable is set by R0R1,
so we need transmited "00" to set bias-disable
When we set "bias-disable" as high-z property,
the parameter should be "MTK_PUPD_SET_R1R0_00".
Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
---
drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index 3cf384f..e88ba04 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -301,8 +301,17 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl
*pctl,
* resistor bit, so we need this special handle.
*/
if (pctl->devdata->spec_pull_set) {
- ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
- pin, pctl->devdata->port_align, isup, arg);
+ if (enable) {
+ ret = pctl->devdata->spec_pull_set(
+ mtk_get_regmap(pctl, pin), pin,
+ pctl->devdata->port_align, isup,
+ arg);
+ } else {
+ ret = pctl->devdata->spec_pull_set(
+ mtk_get_regmap(pctl, pin), pin,
+ pctl->devdata->port_align, isup,
+ MTK_PUPD_SET_R1R0_00);
+ }
if (!ret)
return 0;
}
--
1.9.1
Re: [PATCH v2 4/4] pintcrl: support bias-disable of generic and special pins simultaneously
On Wed, 2018-02-28 at 15:49 +0800, Zhiyong Tao wrote:
> On Wed, 2018-02-28 at 15:33 +0800, Sean Wang wrote:
> > On Mon, 2018-02-26 at 16:34 +0800, Zhiyong Tao wrote:
> > > For generic pins, parameter "arg" is 0 or 1.
> > > For special pins, bias-disable is set by R0R1,
> > > so we need transmited "00" to set bias-disable
> > > When we set "bias-disable" as high-z property,
> > > the parameter should be "MTK_PUPD_SET_R1R0_00".
> > >
> > > Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
> > > ---
> > > drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 13 +++--
> > > 1 file changed, 11 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
> > > b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
> > > index 3cf384f..e88ba04 100644
> > > --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
> > > +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
> > > @@ -301,8 +301,17 @@ static int mtk_pconf_set_pull_select(struct
> > > mtk_pinctrl *pctl,
> > >* resistor bit, so we need this special handle.
> > >*/
> > > if (pctl->devdata->spec_pull_set) {
> > > - ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
> > > - pin, pctl->devdata->port_align, isup, arg);
> > > + if (enable) {
> > > + ret = pctl->devdata->spec_pull_set(
> > > + mtk_get_regmap(pctl, pin), pin,
> > > + pctl->devdata->port_align, isup,
> > > + arg);
> > > + } else {
> > > + ret = pctl->devdata->spec_pull_set(
> > > + mtk_get_regmap(pctl, pin), pin,
> > > + pctl->devdata->port_align, isup,
> > > + MTK_PUPD_SET_R1R0_00);
> > > + }
> >
> >
> > it looks like you can use as following snippet with reusing original
> > logic and less effort on maintaining these common code (?)
> ==> Thanks for your suggestion very much. It seems better.
> I will change it in v3.
==>
Hi sean,
we try it in our site. we can't change like this.
Because we will check "arg" after setting "arg = MTK_PUPD_SET_R1R0_00;".
following snippet which check "arg" value is o or 1. If it not, which
will print error. so we can't change like this.
/* For generic pull config, default arg value should be 0 or 1. */
if (arg != 0 && arg != 1) {
dev_err(pctl->dev, "invalid pull-up argument %d on pin %d .\n", arg,
pin);
return -EINVAL;
}
Thanks.
> >
> >
> > if (pctl->devdata->spec_pull_set) {
> > + if (!enable)
> > + arg = MTK_PUPD_SET_R1R0_00;
> >
> > ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
> > pin, pctl->devdata->port_align, isup, arg);
> >
> >
> > Also, it's better to add more comments to such kind of special path for
> > allowing future SoCs to follow and extend more easily.
>
> ==> Thanks for your suggestion very much. I will add more comments here.
> >
> > > if (!ret)
> > > return 0;
> > > }
> >
> >
>
[PATCH v4 3/5] pinctrl: add mt2712 pinctrl driver
The commit includes mt2712 pinctrl driver.
Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
---
drivers/pinctrl/mediatek/Kconfig |7 +
drivers/pinctrl/mediatek/Makefile |1 +
drivers/pinctrl/mediatek/pinctrl-mt2712.c | 634 +
drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h | 1757 +
4 files changed, 2399 insertions(+)
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt2712.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 3e59874..862c5db 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -32,6 +32,13 @@ config PINCTRL_MT8127
select PINCTRL_MTK
# For ARMv8 SoCs
+config PINCTRL_MT2712
+ bool "MediaTek MT2712 pin control"
+ depends on OF
+ depends on ARM64 || COMPILE_TEST
+ default ARM64 && ARCH_MEDIATEK
+ select PINCTRL_MTK
+
config PINCTRL_MT7622
bool "MediaTek MT7622 pin control"
depends on OF
diff --git a/drivers/pinctrl/mediatek/Makefile
b/drivers/pinctrl/mediatek/Makefile
index ed7d2b2..7959e77 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
# SoC Drivers
obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o
+obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o
obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2712.c
b/drivers/pinctrl/mediatek/pinctrl-mt2712.c
new file mode 100644
index 000..d14511f
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt2712.c
@@ -0,0 +1,634 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Zhiyong Tao <zhiyong@mediatek.com>
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pinctrl-mtk-common.h"
+#include "pinctrl-mtk-mt2712.h"
+
+static const struct mtk_pin_spec_pupd_set_samereg mt2712_spec_pupd[] = {
+ MTK_PIN_PUPD_SPEC_SR(18, 0xe50, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(19, 0xe60, 12, 11, 10),
+ MTK_PIN_PUPD_SPEC_SR(20, 0xe50, 5, 4, 3),
+ MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 15, 14, 13),
+ MTK_PIN_PUPD_SPEC_SR(22, 0xe50, 8, 7, 6),
+ MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 2, 1, 0),
+
+ MTK_PIN_PUPD_SPEC_SR(30, 0xf30, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(31, 0xf30, 6, 5, 4),
+ MTK_PIN_PUPD_SPEC_SR(32, 0xf30, 10, 9, 8),
+ MTK_PIN_PUPD_SPEC_SR(33, 0xf30, 14, 13, 12),
+ MTK_PIN_PUPD_SPEC_SR(34, 0xf40, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(35, 0xf40, 6, 5, 4),
+ MTK_PIN_PUPD_SPEC_SR(36, 0xf40, 10, 9, 8),
+ MTK_PIN_PUPD_SPEC_SR(37, 0xc40, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(38, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(39, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(40, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(41, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(42, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(43, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(44, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(45, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(46, 0xc50, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(47, 0xda0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(48, 0xd90, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(49, 0xdf0, 14, 13, 12),
+ MTK_PIN_PUPD_SPEC_SR(50, 0xdf0, 10, 9, 8),
+ MTK_PIN_PUPD_SPEC_SR(51, 0xdf0, 6, 5, 4),
+ MTK_PIN_PUPD_SPEC_SR(52, 0xdf0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(53, 0xd50, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(54, 0xd80, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(55, 0xe00, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(56, 0xd40, 2, 1, 0),
+
+ MTK_PIN_PUPD_SPEC_SR(63, 0xc80, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(64, 0xdb0, 14, 13, 12),
+ MTK_PIN_PUPD_SPEC_SR(65, 0xdb0, 6, 5, 4),
+ MTK_PIN_PUPD_SPEC_SR(66, 0xdb0, 10, 9, 8),
+ MTK_PIN_PUPD_SPEC_SR(67, 0xcd0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(68, 0xdb0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(69, 0xc90, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(70, 0xcc0, 2, 1, 0),
+
+ MTK_PIN_PUPD_SPEC_SR(89, 0xce0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(90, 0xdd0, 14, 13, 12),
+ MTK_PIN_PUPD_SPEC_SR(91, 0xdd0, 10, 9, 8),
+ MTK_PIN_PUPD_SPEC_SR(92, 0xdd0, 6, 5, 4),
+ MTK_PIN_PUPD_SPEC_SR(93, 0xdd0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(94, 0xd20, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(95, 0xcf0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(96, 0xd30, 2, 1, 0),
+
+ MTK_PIN_PUPD_SPEC_SR(135, 0xe50, 11, 10, 9),
+ MTK_PIN_PUPD_SPEC_SR(136, 0xe50, 14, 13, 12),
+ MTK_PIN_PUPD_SPEC_SR(137, 0xe70, 5, 4, 3),
+ MTK_PIN_PUPD_SPEC_SR(138, 0xe70, 8, 7, 6),
+ MTK_PIN_PUPD_
[PATCH v4 4/5] pintcrl: support bias-disable of generic and special pins simultaneously
For generic pins, parameter "arg" is 0 or 1.
For special pins, bias-disable is set by R0R1,
so we need transmited "00" to set bias-disable
When we set "bias-disable" as high-z property,
the parameter should be "MTK_PUPD_SET_R1R0_00".
Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
---
drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index 3cf384f..f991ff3 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -293,7 +293,7 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl
*pctl,
unsigned int pin, bool enable, bool isup, unsigned int arg)
{
unsigned int bit;
- unsigned int reg_pullen, reg_pullsel;
+ unsigned int reg_pullen, reg_pullsel, r1r0;
int ret;
/* Some pins' pull setting are very different,
@@ -301,8 +301,12 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl
*pctl,
* resistor bit, so we need this special handle.
*/
if (pctl->devdata->spec_pull_set) {
+ /* For special pins, bias-disable is set by R1R0,
+* the parameter should be "MTK_PUPD_SET_R1R0_00".
+*/
+ r1r0 = enable ? arg : MTK_PUPD_SET_R1R0_00;
ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
- pin, pctl->devdata->port_align, isup, arg);
+ pin, pctl->devdata->port_align, isup, r1r0);
if (!ret)
return 0;
}
--
1.9.1
[PATCH v4 1/5] arm64: dts: mt2712: add pintcrl file
This patch adds pinctrl file for mt2712. Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com> Reviewed-by: Rob Herring <r...@kernel.org> --- arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h | 1123 + 1 file changed, 1123 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h diff --git a/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h new file mode 100644 index 000..1b4cb0c --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h @@ -0,0 +1,1123 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + * Author: Zhiyong Tao <zhiyong@mediatek.com> + * + */ +#ifndef __DTS_MT2712_PINFUNC_H +#define __DTS_MT2712_PINFUNC_H + +#include + +#define MT2712_PIN_0_EINT0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define MT2712_PIN_0_EINT0__FUNC_EINT0 (MTK_PIN_NO(0) | 1) +#define MT2712_PIN_0_EINT0__FUNC_MBIST_DIAG_SCANOUT (MTK_PIN_NO(0) | 2) +#define MT2712_PIN_0_EINT0__FUNC_DSIA_TE (MTK_PIN_NO(0) | 3) +#define MT2712_PIN_0_EINT0__FUNC_DSIC_TE (MTK_PIN_NO(0) | 4) +#define MT2712_PIN_0_EINT0__FUNC_DIN_D3 (MTK_PIN_NO(0) | 5) +#define MT2712_PIN_0_EINT0__FUNC_PURE_HW_PROTECT (MTK_PIN_NO(0) | 6) + +#define MT2712_PIN_1_EINT1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define MT2712_PIN_1_EINT1__FUNC_EINT1 (MTK_PIN_NO(1) | 1) +#define MT2712_PIN_1_EINT1__FUNC_IR_IN (MTK_PIN_NO(1) | 2) +#define MT2712_PIN_1_EINT1__FUNC_DSIB_TE (MTK_PIN_NO(1) | 3) +#define MT2712_PIN_1_EINT1__FUNC_DSID_TE (MTK_PIN_NO(1) | 4) +#define MT2712_PIN_1_EINT1__FUNC_DIN_D4 (MTK_PIN_NO(1) | 5) + +#define MT2712_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define MT2712_PIN_2_EINT2__FUNC_EINT2 (MTK_PIN_NO(2) | 1) +#define MT2712_PIN_2_EINT2__FUNC_IR_IN (MTK_PIN_NO(2) | 2) +#define MT2712_PIN_2_EINT2__FUNC_LCM_RST1 (MTK_PIN_NO(2) | 3) +#define MT2712_PIN_2_EINT2__FUNC_DIN_D5 (MTK_PIN_NO(2) | 5) + +#define MT2712_PIN_3_EINT3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define MT2712_PIN_3_EINT3__FUNC_EINT3 (MTK_PIN_NO(3) | 1) +#define MT2712_PIN_3_EINT3__FUNC_IR_IN (MTK_PIN_NO(3) | 2) +#define MT2712_PIN_3_EINT3__FUNC_LCM_RST0 (MTK_PIN_NO(3) | 3) +#define MT2712_PIN_3_EINT3__FUNC_DIN_D6 (MTK_PIN_NO(3) | 5) + +#define MT2712_PIN_4_PWM0__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define MT2712_PIN_4_PWM0__FUNC_PWM0 (MTK_PIN_NO(4) | 1) +#define MT2712_PIN_4_PWM0__FUNC_DISP0_PWM (MTK_PIN_NO(4) | 2) +#define MT2712_PIN_4_PWM0__FUNC_DISP1_PWM (MTK_PIN_NO(4) | 3) +#define MT2712_PIN_4_PWM0__FUNC_DIN_CLK (MTK_PIN_NO(4) | 5) + +#define MT2712_PIN_5_PWM1__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define MT2712_PIN_5_PWM1__FUNC_PWM1 (MTK_PIN_NO(5) | 1) +#define MT2712_PIN_5_PWM1__FUNC_DISP1_PWM (MTK_PIN_NO(5) | 2) +#define MT2712_PIN_5_PWM1__FUNC_DISP0_PWM (MTK_PIN_NO(5) | 3) +#define MT2712_PIN_5_PWM1__FUNC_DIN_VSYNC (MTK_PIN_NO(5) | 5) + +#define MT2712_PIN_6_PWM2__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define MT2712_PIN_6_PWM2__FUNC_PWM2 (MTK_PIN_NO(6) | 1) +#define MT2712_PIN_6_PWM2__FUNC_DISP0_PWM (MTK_PIN_NO(6) | 2) +#define MT2712_PIN_6_PWM2__FUNC_DISP1_PWM (MTK_PIN_NO(6) | 3) +#define MT2712_PIN_6_PWM2__FUNC_DISP2_PWM (MTK_PIN_NO(6) | 4) +#define MT2712_PIN_6_PWM2__FUNC_DIN_HSYNC (MTK_PIN_NO(6) | 5) + +#define MT2712_PIN_7_PWM3__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define MT2712_PIN_7_PWM3__FUNC_PWM3 (MTK_PIN_NO(7) | 1) +#define MT2712_PIN_7_PWM3__FUNC_DISP1_PWM (MTK_PIN_NO(7) | 2) +#define MT2712_PIN_7_PWM3__FUNC_DISP0_PWM (MTK_PIN_NO(7) | 3) +#define MT2712_PIN_7_PWM3__FUNC_LCM_RST2 (MTK_PIN_NO(7) | 4) +#define MT2712_PIN_7_PWM3__FUNC_DIN_D0 (MTK_PIN_NO(7) | 5) + +#define MT2712_PIN_8_PWM4__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define MT2712_PIN_8_PWM4__FUNC_PWM4 (MTK_PIN_NO(8) | 1) +#define MT2712_PIN_8_PWM4__FUNC_DISP0_PWM (MTK_PIN_NO(8) | 2) +#define MT2712_PIN_8_PWM4__FUNC_DISP1_PWM (MTK_PIN_NO(8) | 3) +#define MT2712_PIN_8_PWM4__FUNC_DSIA_TE (MTK_PIN_NO(8) | 4) +#define MT2712_PIN_8_PWM4__FUNC_DIN_D1 (MTK_PIN_NO(8) | 5) + +#define MT2712_PIN_9_PWM5__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define MT2712_PIN_9_PWM5__FUNC_PWM5 (MTK_PIN_NO(9) | 1) +#define MT2712_PIN_9_PWM5__FUNC_DISP1_PWM (MTK_PIN_NO(9) | 2) +#define MT2712_PIN_9_PWM5__FUNC_DISP0_PWM (MTK_PIN_NO(9) | 3) +#define MT2712_PIN_9_PWM5__FUNC_DSIB_TE (MTK_PIN_NO(9) | 4) +#define MT2712_PIN_9_PWM5__FUNC_DIN_D2 (MTK_PIN_NO(9) | 5) + +#define MT2712_PIN_10_PWM6__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define MT2712_PIN_10_PWM6__FUNC_PWM6 (MTK_PIN_NO(10) | 1) +#define MT2712_PIN_10_PWM6__FUNC_DISP0_PWM (MTK_PIN_NO(10) | 2) +#define MT2712_PIN_10_PWM6__FUNC_DISP1_PWM (MTK_PIN_NO(10) | 3) +#define MT2712_PIN_10_PWM6__FUNC_LCM_RST0 (MTK_PIN_NO(10) | 4) + +#define MT2712_PIN_11_PWM7__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define MT2712_PIN_11_PWM7__FUNC_PWM7 (MTK_PIN_NO(11) | 1) +#define MT2712_PIN_11_PWM7__FUNC_DISP1_PWM (MTK_PIN_NO(11) | 2) +#define MT2712_PIN_11_PWM7__FUNC_DISP0_PWM (MTK_PIN_NO(11) | 3) +#define MT2712_PIN_11_PWM7__FUNC_LCM_RST1 (MTK_PIN_NO(11) | 4) + +#define MT2712_PIN_12_IDDIG_P0__FUNC_GPIO12 (
[PATCH v4 2/5] arm64: dts: mt2712: add pintcrl device node.
This patch adds pintcrl device node for mt2712.
Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index d7688bc..fb3b051 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -9,6 +9,7 @@
#include
#include
#include
+#include "mt2712-pinfunc.h"
/ {
compatible = "mediatek,mt2712";
@@ -258,6 +259,23 @@
#clock-cells = <1>;
};
+ syscfg_pctl_a: syscfg_pctl_a@10005000 {
+ compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon";
+ reg = <0 0x10005000 0 0x1000>;
+ };
+
+ pio: pinctrl@10005000 {
+ compatible = "mediatek,mt2712-pinctrl";
+ reg = <0 0x1000b000 0 0x1000>;
+ mediatek,pctl-regmap = <_pctl_a>;
+ pins-are-numbered;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = ;
+ };
+
scpsys: scpsys@10006000 {
compatible = "mediatek,mt2712-scpsys", "syscon";
#power-domain-cells = <1>;
--
1.9.1
[PATCH v4 0/5] PINCTRL: Mediatek pinctrl driver for mt2712
This series includes five patches: 1.Add mt2712 pintcrl head file. 2.Add mt2712 pinctrl device node. 3.Add mt2712 pinctrl driver. 4.Support bias-disable of generic and special pins simultaneously. 5.fix check warnings. Changes in patch v4: 1)fix check warnings for mt2712. 2)add fix check warnings patch for other ICs. Changes in patch v3: 1)Use SPDX identifiers for all new files. 2)Use right data for Copyright and Author. 3)Correct some spelling mistake. 4)Reusing original logic and change solution to support bias-disable of generic and special pins simultaneously. 5)Add some comments for the speical path of special pins bias-disable. Changes in patch v2: 1)Separate patch4 for supporting bias-disable of generic and special pins. 2)GPIO16~17 direction setting is changed as generic pins in mt2712 E2, So remove GPIO16~17 special direction setting and remove apmixedsys node in pinctrl device node. 3)Add pinmux define in "mt2712-pinfunc.h" and "pinctrl-mtk-mt2712.h" for mt2712 E2 design. Zhiyong Tao (5): arm64: dts: mt2712: add pintcrl file arm64: dts: mt2712: add pintcrl device node. pinctrl: add mt2712 pinctrl driver pintcrl: support bias-disable of generic and special pins simultaneously pinctrl: fix check warnings. arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h | 1123 arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 18 + drivers/pinctrl/mediatek/Kconfig |7 + drivers/pinctrl/mediatek/Makefile |1 + drivers/pinctrl/mediatek/pinctrl-mt2712.c | 634 + drivers/pinctrl/mediatek/pinctrl-mtk-common.c |8 +- drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h | 840 drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h | 1757 + drivers/pinctrl/mediatek/pinctrl-mtk-mt6397.h | 123 +- drivers/pinctrl/mediatek/pinctrl-mtk-mt8127.h | 429 ++ drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h | 609 +++-- drivers/pinctrl/mediatek/pinctrl-mtk-mt8173.h | 405 ++ 12 files changed, 4348 insertions(+), 1606 deletions(-) create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt2712.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h -- 2.6.4
Re: [PATCH v2 4/4] pintcrl: support bias-disable of generic and special pins simultaneously
On Thu, 2018-03-01 at 15:43 +0800, Sean Wang wrote:
> On Thu, 2018-03-01 at 11:47 +0800, Zhiyong Tao wrote:
> > On Wed, 2018-02-28 at 15:49 +0800, Zhiyong Tao wrote:
> > > On Wed, 2018-02-28 at 15:33 +0800, Sean Wang wrote:
> > > > On Mon, 2018-02-26 at 16:34 +0800, Zhiyong Tao wrote:
> > > > > For generic pins, parameter "arg" is 0 or 1.
> > > > > For special pins, bias-disable is set by R0R1,
> > > > > so we need transmited "00" to set bias-disable
> > > > > When we set "bias-disable" as high-z property,
> > > > > the parameter should be "MTK_PUPD_SET_R1R0_00".
> > > > >
> > > > > Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
> > > > > ---
> > > > > drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 13 +++--
> > > > > 1 file changed, 11 insertions(+), 2 deletions(-)
> > > > >
> > > > > diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
> > > > > b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
> > > > > index 3cf384f..e88ba04 100644
> > > > > --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
> > > > > +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
> > > > > @@ -301,8 +301,17 @@ static int mtk_pconf_set_pull_select(struct
> > > > > mtk_pinctrl *pctl,
> > > > >* resistor bit, so we need this special handle.
> > > > >*/
> > > > > if (pctl->devdata->spec_pull_set) {
> > > > > - ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl,
> > > > > pin),
> > > > > - pin, pctl->devdata->port_align, isup, arg);
> > > > > + if (enable) {
> > > > > + ret = pctl->devdata->spec_pull_set(
> > > > > + mtk_get_regmap(pctl, pin), pin,
> > > > > + pctl->devdata->port_align, isup,
> > > > > + arg);
> > > > > + } else {
> > > > > + ret = pctl->devdata->spec_pull_set(
> > > > > + mtk_get_regmap(pctl, pin), pin,
> > > > > + pctl->devdata->port_align, isup,
> > > > > + MTK_PUPD_SET_R1R0_00);
> > > > > + }
> > > >
> > > >
> > > > it looks like you can use as following snippet with reusing original
> > > > logic and less effort on maintaining these common code (?)
> > > ==> Thanks for your suggestion very much. It seems better.
> > > I will change it in v3.
> >
> > ==>
> > Hi sean,
> >
> > we try it in our site. we can't change like this.
> > Because we will check "arg" after setting "arg = MTK_PUPD_SET_R1R0_00;".
> > following snippet which check "arg" value is o or 1. If it not, which
> > will print error. so we can't change like this.
> > /* For generic pull config, default arg value should be 0 or 1. */
> > if (arg != 0 && arg != 1) {
> > dev_err(pctl->dev, "invalid pull-up argument %d on pin %d .\n", arg,
> > pin);
> > return -EINVAL;
> > }
> >
> > Thanks.
>
> why not rewrite it with
==> Hi sean,
Thanks for your comments, we will try to do it. If it is ok, we will
modify it in v3.
>
> @@ -301,8 +301,10 @@ static int mtk_pconf_set_pull_select(struct
> mtk_pinctrl *pctl,
> * resistor bit, so we need this special handle.
> */
> if (pctl->devdata->spec_pull_set) {
> + unsigned int r1r0 = enable ? arg : MTK_PUPD_SET_R1R0_00;
> +
> ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl,
> pin),
> - pin, pctl->devdata->port_align, isup, arg);
> + pin, pctl->devdata->port_align, isup, r1r0);
> if (!ret)
> return 0;
> }
>
> and also I appeared to find another bug in the original code when I had
> a close look at the code path, but it's not related to the patch:
>
> a special pin would still go through the code path to handle
> generic pin when the special pin uses an invalid argument.
>
> It looks like err-code from pctl->devdata->spec_pull_set cannot be
> used directly to judge its pin type. It's also possible to use it as an
> indication of the real failure during special pin is being set up.
>
==>Hi sean,
The function seems ok. it is not related to the patch. We will think
about your comment. If there is better idea to modify the code flow. We
will change it in another patch.
Thanks.
> > > >
> > > >
> > > > if (pctl->devdata->spec_pull_set) {
> > > > + if (!enable)
> > > > + arg = MTK_PUPD_SET_R1R0_00;
> > > >
> > > > ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
> > > > pin, pctl->devdata->port_align, isup, arg);
> > > >
> > > >
> > > > Also, it's better to add more comments to such kind of special path for
> > > > allowing future SoCs to follow and extend more easily.
> > >
> > > ==> Thanks for your suggestion very much. I will add more comments here.
> > > >
> > > > > if (!ret)
> > > > > return 0;
> > > > > }
> > > >
> > > >
> > >
> >
> >
>
>
[PATCH v3 1/4] arm64: dts: mt2712: add pintcrl file
This patch adds pinctrl file for mt2712. Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h | 1123 + 1 file changed, 1123 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h diff --git a/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h new file mode 100644 index 000..1b4cb0c --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h @@ -0,0 +1,1123 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + * Author: Zhiyong Tao <zhiyong@mediatek.com> + * + */ +#ifndef __DTS_MT2712_PINFUNC_H +#define __DTS_MT2712_PINFUNC_H + +#include + +#define MT2712_PIN_0_EINT0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define MT2712_PIN_0_EINT0__FUNC_EINT0 (MTK_PIN_NO(0) | 1) +#define MT2712_PIN_0_EINT0__FUNC_MBIST_DIAG_SCANOUT (MTK_PIN_NO(0) | 2) +#define MT2712_PIN_0_EINT0__FUNC_DSIA_TE (MTK_PIN_NO(0) | 3) +#define MT2712_PIN_0_EINT0__FUNC_DSIC_TE (MTK_PIN_NO(0) | 4) +#define MT2712_PIN_0_EINT0__FUNC_DIN_D3 (MTK_PIN_NO(0) | 5) +#define MT2712_PIN_0_EINT0__FUNC_PURE_HW_PROTECT (MTK_PIN_NO(0) | 6) + +#define MT2712_PIN_1_EINT1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define MT2712_PIN_1_EINT1__FUNC_EINT1 (MTK_PIN_NO(1) | 1) +#define MT2712_PIN_1_EINT1__FUNC_IR_IN (MTK_PIN_NO(1) | 2) +#define MT2712_PIN_1_EINT1__FUNC_DSIB_TE (MTK_PIN_NO(1) | 3) +#define MT2712_PIN_1_EINT1__FUNC_DSID_TE (MTK_PIN_NO(1) | 4) +#define MT2712_PIN_1_EINT1__FUNC_DIN_D4 (MTK_PIN_NO(1) | 5) + +#define MT2712_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define MT2712_PIN_2_EINT2__FUNC_EINT2 (MTK_PIN_NO(2) | 1) +#define MT2712_PIN_2_EINT2__FUNC_IR_IN (MTK_PIN_NO(2) | 2) +#define MT2712_PIN_2_EINT2__FUNC_LCM_RST1 (MTK_PIN_NO(2) | 3) +#define MT2712_PIN_2_EINT2__FUNC_DIN_D5 (MTK_PIN_NO(2) | 5) + +#define MT2712_PIN_3_EINT3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define MT2712_PIN_3_EINT3__FUNC_EINT3 (MTK_PIN_NO(3) | 1) +#define MT2712_PIN_3_EINT3__FUNC_IR_IN (MTK_PIN_NO(3) | 2) +#define MT2712_PIN_3_EINT3__FUNC_LCM_RST0 (MTK_PIN_NO(3) | 3) +#define MT2712_PIN_3_EINT3__FUNC_DIN_D6 (MTK_PIN_NO(3) | 5) + +#define MT2712_PIN_4_PWM0__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define MT2712_PIN_4_PWM0__FUNC_PWM0 (MTK_PIN_NO(4) | 1) +#define MT2712_PIN_4_PWM0__FUNC_DISP0_PWM (MTK_PIN_NO(4) | 2) +#define MT2712_PIN_4_PWM0__FUNC_DISP1_PWM (MTK_PIN_NO(4) | 3) +#define MT2712_PIN_4_PWM0__FUNC_DIN_CLK (MTK_PIN_NO(4) | 5) + +#define MT2712_PIN_5_PWM1__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define MT2712_PIN_5_PWM1__FUNC_PWM1 (MTK_PIN_NO(5) | 1) +#define MT2712_PIN_5_PWM1__FUNC_DISP1_PWM (MTK_PIN_NO(5) | 2) +#define MT2712_PIN_5_PWM1__FUNC_DISP0_PWM (MTK_PIN_NO(5) | 3) +#define MT2712_PIN_5_PWM1__FUNC_DIN_VSYNC (MTK_PIN_NO(5) | 5) + +#define MT2712_PIN_6_PWM2__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define MT2712_PIN_6_PWM2__FUNC_PWM2 (MTK_PIN_NO(6) | 1) +#define MT2712_PIN_6_PWM2__FUNC_DISP0_PWM (MTK_PIN_NO(6) | 2) +#define MT2712_PIN_6_PWM2__FUNC_DISP1_PWM (MTK_PIN_NO(6) | 3) +#define MT2712_PIN_6_PWM2__FUNC_DISP2_PWM (MTK_PIN_NO(6) | 4) +#define MT2712_PIN_6_PWM2__FUNC_DIN_HSYNC (MTK_PIN_NO(6) | 5) + +#define MT2712_PIN_7_PWM3__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define MT2712_PIN_7_PWM3__FUNC_PWM3 (MTK_PIN_NO(7) | 1) +#define MT2712_PIN_7_PWM3__FUNC_DISP1_PWM (MTK_PIN_NO(7) | 2) +#define MT2712_PIN_7_PWM3__FUNC_DISP0_PWM (MTK_PIN_NO(7) | 3) +#define MT2712_PIN_7_PWM3__FUNC_LCM_RST2 (MTK_PIN_NO(7) | 4) +#define MT2712_PIN_7_PWM3__FUNC_DIN_D0 (MTK_PIN_NO(7) | 5) + +#define MT2712_PIN_8_PWM4__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define MT2712_PIN_8_PWM4__FUNC_PWM4 (MTK_PIN_NO(8) | 1) +#define MT2712_PIN_8_PWM4__FUNC_DISP0_PWM (MTK_PIN_NO(8) | 2) +#define MT2712_PIN_8_PWM4__FUNC_DISP1_PWM (MTK_PIN_NO(8) | 3) +#define MT2712_PIN_8_PWM4__FUNC_DSIA_TE (MTK_PIN_NO(8) | 4) +#define MT2712_PIN_8_PWM4__FUNC_DIN_D1 (MTK_PIN_NO(8) | 5) + +#define MT2712_PIN_9_PWM5__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define MT2712_PIN_9_PWM5__FUNC_PWM5 (MTK_PIN_NO(9) | 1) +#define MT2712_PIN_9_PWM5__FUNC_DISP1_PWM (MTK_PIN_NO(9) | 2) +#define MT2712_PIN_9_PWM5__FUNC_DISP0_PWM (MTK_PIN_NO(9) | 3) +#define MT2712_PIN_9_PWM5__FUNC_DSIB_TE (MTK_PIN_NO(9) | 4) +#define MT2712_PIN_9_PWM5__FUNC_DIN_D2 (MTK_PIN_NO(9) | 5) + +#define MT2712_PIN_10_PWM6__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define MT2712_PIN_10_PWM6__FUNC_PWM6 (MTK_PIN_NO(10) | 1) +#define MT2712_PIN_10_PWM6__FUNC_DISP0_PWM (MTK_PIN_NO(10) | 2) +#define MT2712_PIN_10_PWM6__FUNC_DISP1_PWM (MTK_PIN_NO(10) | 3) +#define MT2712_PIN_10_PWM6__FUNC_LCM_RST0 (MTK_PIN_NO(10) | 4) + +#define MT2712_PIN_11_PWM7__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define MT2712_PIN_11_PWM7__FUNC_PWM7 (MTK_PIN_NO(11) | 1) +#define MT2712_PIN_11_PWM7__FUNC_DISP1_PWM (MTK_PIN_NO(11) | 2) +#define MT2712_PIN_11_PWM7__FUNC_DISP0_PWM (MTK_PIN_NO(11) | 3) +#define MT2712_PIN_11_PWM7__FUNC_LCM_RST1 (MTK_PIN_NO(11) | 4) + +#define MT2712_PIN_12_IDDIG_P0__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define MT2712_PIN_12_IDDIG_P0__
[PATCH v3 0/4] PINCTRL: Mediatek pinctrl driver for mt2712
This series includes four patches: 1.Add mt2712 pintcrl head file. 2.Add mt2712 pinctrl device node. 3.Add mt2712 pinctrl driver. 4.Support bias-disable of generic and special pins simultaneously. Changes in patch v3: 1)Use SPDX identifiers for all new files. 2)Use right data for Copyright and Author. 3)Correct some spelling mistake. 4)Reusing original logic and change solution to support bias-disable of generic and special pins simultaneously. 5)Add some comments for the speical path of special pins bias-disable. Changes in patch v2: 1)Separate patch4 for supporting bias-disable of generic and special pins. 2)GPIO16~17 direction setting is changed as generic pins in mt2712 E2, So remove GPIO16~17 special direction setting and remove apmixedsys node in pinctrl device node. 3)Add pinmux define in "mt2712-pinfunc.h" and "pinctrl-mtk-mt2712.h" for mt2712 E2 design. Zhiyong Tao (4): arm64: dts: mt2712: add pintcrl file arm64: dts: mt2712: add pintcrl device node. pinctrl: add mt2712 pinctrl driver pintcrl: support bias-disable of generic and special pins simultaneously arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h | 1123 ++ arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 18 + drivers/pinctrl/mediatek/Kconfig |7 + drivers/pinctrl/mediatek/Makefile |1 + drivers/pinctrl/mediatek/pinctrl-mt2712.c | 632 drivers/pinctrl/mediatek/pinctrl-mtk-common.c |6 + drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h | 1967 + 7 files changed, 3754 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt2712.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h -- 2.6.4
[PATCH v3 3/4] pinctrl: add mt2712 pinctrl driver
The commit includes mt2712 pinctrl driver.
Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
---
drivers/pinctrl/mediatek/Kconfig |7 +
drivers/pinctrl/mediatek/Makefile |1 +
drivers/pinctrl/mediatek/pinctrl-mt2712.c | 632
drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h | 1967 +
4 files changed, 2607 insertions(+)
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt2712.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 3e59874..862c5db 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -32,6 +32,13 @@ config PINCTRL_MT8127
select PINCTRL_MTK
# For ARMv8 SoCs
+config PINCTRL_MT2712
+ bool "MediaTek MT2712 pin control"
+ depends on OF
+ depends on ARM64 || COMPILE_TEST
+ default ARM64 && ARCH_MEDIATEK
+ select PINCTRL_MTK
+
config PINCTRL_MT7622
bool "MediaTek MT7622 pin control"
depends on OF
diff --git a/drivers/pinctrl/mediatek/Makefile
b/drivers/pinctrl/mediatek/Makefile
index ed7d2b2..7959e77 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
# SoC Drivers
obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o
+obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o
obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2712.c
b/drivers/pinctrl/mediatek/pinctrl-mt2712.c
new file mode 100644
index 000..5595e90
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt2712.c
@@ -0,0 +1,632 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Zhiyong Tao <zhiyong@mediatek.com>
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pinctrl-mtk-common.h"
+#include "pinctrl-mtk-mt2712.h"
+
+static const struct mtk_pin_spec_pupd_set_samereg mt2712_spec_pupd[] = {
+ MTK_PIN_PUPD_SPEC_SR(18, 0xe50, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(19, 0xe60, 12, 11, 10),
+ MTK_PIN_PUPD_SPEC_SR(20, 0xe50, 5, 4, 3),
+ MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 15, 14, 13),
+ MTK_PIN_PUPD_SPEC_SR(22, 0xe50, 8, 7, 6),
+ MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 2, 1, 0),
+
+ MTK_PIN_PUPD_SPEC_SR(30, 0xf30, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(31, 0xf30, 6, 5, 4),
+ MTK_PIN_PUPD_SPEC_SR(32, 0xf30, 10, 9, 8),
+ MTK_PIN_PUPD_SPEC_SR(33, 0xf30, 14, 13, 12),
+ MTK_PIN_PUPD_SPEC_SR(34, 0xf40, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(35, 0xf40, 6, 5, 4),
+ MTK_PIN_PUPD_SPEC_SR(36, 0xf40, 10, 9, 8),
+ MTK_PIN_PUPD_SPEC_SR(37, 0xc40, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(38, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(39, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(40, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(41, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(42, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(43, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(44, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(45, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(46, 0xc50, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(47, 0xda0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(48, 0xd90, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(49, 0xdf0, 14, 13, 12),
+ MTK_PIN_PUPD_SPEC_SR(50, 0xdf0, 10, 9, 8),
+ MTK_PIN_PUPD_SPEC_SR(51, 0xdf0, 6, 5, 4),
+ MTK_PIN_PUPD_SPEC_SR(52, 0xdf0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(53, 0xd50, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(54, 0xd80, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(55, 0xe00, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(56, 0xd40, 2, 1, 0),
+
+ MTK_PIN_PUPD_SPEC_SR(63, 0xc80, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(64, 0xdb0, 14, 13, 12),
+ MTK_PIN_PUPD_SPEC_SR(65, 0xdb0, 6, 5, 4),
+ MTK_PIN_PUPD_SPEC_SR(66, 0xdb0, 10, 9, 8),
+ MTK_PIN_PUPD_SPEC_SR(67, 0xcd0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(68, 0xdb0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(69, 0xc90, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(70, 0xcc0, 2, 1, 0),
+
+ MTK_PIN_PUPD_SPEC_SR(89, 0xce0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(90, 0xdd0, 14, 13, 12),
+ MTK_PIN_PUPD_SPEC_SR(91, 0xdd0, 10, 9, 8),
+ MTK_PIN_PUPD_SPEC_SR(92, 0xdd0, 6, 5, 4),
+ MTK_PIN_PUPD_SPEC_SR(93, 0xdd0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(94, 0xd20, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(95, 0xcf0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(96, 0xd30, 2, 1, 0),
+
+ MTK_PIN_PUPD_SPEC_SR(135, 0xe50, 11, 10, 9),
+ MTK_PIN_PUPD_SPEC_SR(136, 0xe50, 14, 13, 12),
+ MTK_PIN_PUPD_SPEC_SR(137, 0xe70, 5, 4, 3),
+ MTK_PIN_PUPD_SPEC_SR(138, 0xe70, 8, 7, 6),
+ MTK_PIN_PUPD_
[PATCH v3 4/4] pintcrl: support bias-disable of generic and special pins simultaneously
For generic pins, parameter "arg" is 0 or 1.
For special pins, bias-disable is set by R0R1,
so we need transmited "00" to set bias-disable
When we set "bias-disable" as high-z property,
the parameter should be "MTK_PUPD_SET_R1R0_00".
Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
---
drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index 3cf384f..f991ff3 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -293,7 +293,7 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl
*pctl,
unsigned int pin, bool enable, bool isup, unsigned int arg)
{
unsigned int bit;
- unsigned int reg_pullen, reg_pullsel;
+ unsigned int reg_pullen, reg_pullsel, r1r0;
int ret;
/* Some pins' pull setting are very different,
@@ -301,8 +301,12 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl
*pctl,
* resistor bit, so we need this special handle.
*/
if (pctl->devdata->spec_pull_set) {
+ /* For special pins, bias-disable is set by R1R0,
+* the parameter should be "MTK_PUPD_SET_R1R0_00".
+*/
+ r1r0 = enable ? arg : MTK_PUPD_SET_R1R0_00;
ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
- pin, pctl->devdata->port_align, isup, arg);
+ pin, pctl->devdata->port_align, isup, r1r0);
if (!ret)
return 0;
}
--
1.9.1
[PATCH v3 2/4] arm64: dts: mt2712: add pintcrl device node.
This patch adds pintcrl device node for mt2712.
Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index d7688bc..fb3b051 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -9,6 +9,7 @@
#include
#include
#include
+#include "mt2712-pinfunc.h"
/ {
compatible = "mediatek,mt2712";
@@ -258,6 +259,23 @@
#clock-cells = <1>;
};
+ syscfg_pctl_a: syscfg_pctl_a@10005000 {
+ compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon";
+ reg = <0 0x10005000 0 0x1000>;
+ };
+
+ pio: pinctrl@10005000 {
+ compatible = "mediatek,mt2712-pinctrl";
+ reg = <0 0x1000b000 0 0x1000>;
+ mediatek,pctl-regmap = <_pctl_a>;
+ pins-are-numbered;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = ;
+ };
+
scpsys: scpsys@10006000 {
compatible = "mediatek,mt2712-scpsys", "syscon";
#power-domain-cells = <1>;
--
1.9.1
Re: [PATCH v2 3/4] pinctrl: add mt2712 pinctrl driver
On Wed, 2018-02-28 at 15:14 +0800, Sean Wang wrote: > Hi, Zhiyong > > all seems better than v1, but some nitpicking is addressed as below > > Sean > > On Mon, 2018-02-26 at 16:34 +0800, Zhiyong Tao wrote: > > The commit includes mt2712 pinctrl driver. > > > > Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com> > > --- > > drivers/pinctrl/mediatek/Kconfig |7 + > > drivers/pinctrl/mediatek/Makefile |1 + > > drivers/pinctrl/mediatek/pinctrl-mt2712.c | 639 > > drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h | 1973 > > + > > 4 files changed, 2620 insertions(+) > > create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt2712.c > > create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h > > > > diff --git a/drivers/pinctrl/mediatek/Kconfig > > b/drivers/pinctrl/mediatek/Kconfig > > index 3e59874..b24bc76 100644 > > --- a/drivers/pinctrl/mediatek/Kconfig > > +++ b/drivers/pinctrl/mediatek/Kconfig > > @@ -32,6 +32,13 @@ config PINCTRL_MT8127 > > select PINCTRL_MTK > > > > # For ARMv8 SoCs > > +config PINCTRL_MT2712 > > + bool "Mediatek MT2712 pin control" > > > should be MediaTek for normal ==> Thanks for your suggestion. We will correct it in v3. > > > + depends on OF > > + depends on ARM64 || COMPILE_TEST > > + default ARM64 && ARCH_MEDIATEK > > + select PINCTRL_MTK > > + > > config PINCTRL_MT7622 > > bool "MediaTek MT7622 pin control" > > depends on OF > > diff --git a/drivers/pinctrl/mediatek/Makefile > > b/drivers/pinctrl/mediatek/Makefile > > index ed7d2b2..7959e77 100644 > > --- a/drivers/pinctrl/mediatek/Makefile > > +++ b/drivers/pinctrl/mediatek/Makefile > > @@ -4,6 +4,7 @@ obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o > > > > # SoC Drivers > > obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o > > +obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o > > obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o > > obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o > > obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o > > diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2712.c > > b/drivers/pinctrl/mediatek/pinctrl-mt2712.c > > new file mode 100644 > > index 000..b6ae71b > > --- /dev/null > > +++ b/drivers/pinctrl/mediatek/pinctrl-mt2712.c > > @@ -0,0 +1,639 @@ > > +/* > > + * Copyright (c) 2014-2015 MediaTek Inc. > > + * Author: Hongzhou.Yang <hongzhou.y...@mediatek.com> > > + * > > + * This program is free software; you can redistribute it and/or modify > > + * it under the terms of the GNU General Public License version 2 as > > + * published by the Free Software Foundation. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + */ > > + > > suggest to consider more on using SPDX identifiers and > using right data for both fields Copyright and Author ==> Thanks for your suggestion. We will correct it in v3. > > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#include "pinctrl-mtk-common.h" > > +#include "pinctrl-mtk-mt2712.h" > > + > > <...> > > > diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h > > b/drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h > > new file mode 100644 > > index 000..71f4190 > > --- /dev/null > > +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h > > @@ -0,0 +1,1973 @@ > > +/* > > + * Copyright (C) 2015 MediaTek Inc. > > + * > > + * This program is free software: you can redistribute it and/or modify > > + * it under the terms of the GNU General Public License version 2 as > > + * published by the Free Software Foundation. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + */ > > Ditto > > > +#ifndef PINCTRL_MTK_MT2712_H > > +#define PINCTRL_MTK_MT2712_H > > + > > <...> > > > + > > +#endif /* __PINCTRL_MTK_MT2712_H */ > >
Re: [PATCH v2 1/4] arm64: dts: mt2712: add pintcrl file
On Wed, 2018-02-28 at 14:42 +0800, Sean Wang wrote: > On Mon, 2018-02-26 at 16:33 +0800, Zhiyong Tao wrote: > > This patch adds pinctrl file for mt2712. > > > > Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com> > > --- > > arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h | 1129 > > + > > 1 file changed, 1129 insertions(+) > > create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h > > b/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h > > new file mode 100644 > > index 000..44f8ca2 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h > > @@ -0,0 +1,1129 @@ > > +/* > > + * Copyright (C) 2015 MediaTek Inc. > > + * > > + * This program is free software: you can redistribute it and/or modify > > + * it under the terms of the GNU General Public License version 2 as > > + * published by the Free Software Foundation. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + */ > > suggest to consider more on using SPDX identifiers ==> Thanks for your suggestion. We will use SPDX identifiers in V3. > > > +#ifndef __DTS_MT2712_PINFUNC_H > > +#define __DTS_MT2712_PINFUNC_H > > + > > +#include > > + > > +#define MT2712_PIN_0_EINT0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) > > +#define MT2712_PIN_0_EINT0__FUNC_EINT0 (MTK_PIN_NO(0) | 1) > > +#define MT2712_PIN_0_EINT0__FUNC_MBIST_DIAG_SCANOUT (MTK_PIN_NO(0) | 2) > > +#define MT2712_PIN_0_EINT0__FUNC_DSIA_TE (MTK_PIN_NO(0) | 3) > > +#define MT2712_PIN_0_EINT0__FUNC_DSIC_TE (MTK_PIN_NO(0) | 4) > > +#define MT2712_PIN_0_EINT0__FUNC_DIN_D3 (MTK_PIN_NO(0) | 5) > > +#define MT2712_PIN_0_EINT0__FUNC_PURE_HW_PROTECT (MTK_PIN_NO(0) | 6) > > + > > +#define MT2712_PIN_1_EINT1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) > > +#define MT2712_PIN_1_EINT1__FUNC_EINT1 (MTK_PIN_NO(1) | 1) > > +#define MT2712_PIN_1_EINT1__FUNC_IR_IN (MTK_PIN_NO(1) | 2) > > +#define MT2712_PIN_1_EINT1__FUNC_DSIB_TE (MTK_PIN_NO(1) | 3) > > +#define MT2712_PIN_1_EINT1__FUNC_DSID_TE (MTK_PIN_NO(1) | 4) > > +#define MT2712_PIN_1_EINT1__FUNC_DIN_D4 (MTK_PIN_NO(1) | 5) > > + > > +#define MT2712_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) > > +#define MT2712_PIN_2_EINT2__FUNC_EINT2 (MTK_PIN_NO(2) | 1) > > +#define MT2712_PIN_2_EINT2__FUNC_IR_IN (MTK_PIN_NO(2) | 2) > > +#define MT2712_PIN_2_EINT2__FUNC_LCM_RST1 (MTK_PIN_NO(2) | 3) > > +#define MT2712_PIN_2_EINT2__FUNC_DIN_D5 (MTK_PIN_NO(2) | 5) > > + > > +#define MT2712_PIN_3_EINT3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) > > +#define MT2712_PIN_3_EINT3__FUNC_EINT3 (MTK_PIN_NO(3) | 1) > > +#define MT2712_PIN_3_EINT3__FUNC_IR_IN (MTK_PIN_NO(3) | 2) > > +#define MT2712_PIN_3_EINT3__FUNC_LCM_RST0 (MTK_PIN_NO(3) | 3) > > +#define MT2712_PIN_3_EINT3__FUNC_DIN_D6 (MTK_PIN_NO(3) | 5) > > + > > +#define MT2712_PIN_4_PWM0__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) > > +#define MT2712_PIN_4_PWM0__FUNC_PWM0 (MTK_PIN_NO(4) | 1) > > +#define MT2712_PIN_4_PWM0__FUNC_DISP0_PWM (MTK_PIN_NO(4) | 2) > > +#define MT2712_PIN_4_PWM0__FUNC_DISP1_PWM (MTK_PIN_NO(4) | 3) > > +#define MT2712_PIN_4_PWM0__FUNC_DIN_CLK (MTK_PIN_NO(4) | 5) > > + > > +#define MT2712_PIN_5_PWM1__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) > > +#define MT2712_PIN_5_PWM1__FUNC_PWM1 (MTK_PIN_NO(5) | 1) > > +#define MT2712_PIN_5_PWM1__FUNC_DISP1_PWM (MTK_PIN_NO(5) | 2) > > +#define MT2712_PIN_5_PWM1__FUNC_DISP0_PWM (MTK_PIN_NO(5) | 3) > > +#define MT2712_PIN_5_PWM1__FUNC_DIN_VSYNC (MTK_PIN_NO(5) | 5) > > + > > +#define MT2712_PIN_6_PWM2__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) > > +#define MT2712_PIN_6_PWM2__FUNC_PWM2 (MTK_PIN_NO(6) | 1) > > +#define MT2712_PIN_6_PWM2__FUNC_DISP0_PWM (MTK_PIN_NO(6) | 2) > > +#define MT2712_PIN_6_PWM2__FUNC_DISP1_PWM (MTK_PIN_NO(6) | 3) > > +#define MT2712_PIN_6_PWM2__FUNC_DISP2_PWM (MTK_PIN_NO(6) | 4) > > +#define MT2712_PIN_6_PWM2__FUNC_DIN_HSYNC (MTK_PIN_NO(6) | 5) > > + > > +#define MT2712_PIN_7_PWM3__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) > > +#define MT2712_PIN_7_PWM3__FUNC_PWM3 (MTK_PIN_NO(7) | 1) > > +#define MT2712_PIN_7_PWM3__FUNC_DISP1_PWM (MTK_PIN_NO(7) | 2) > > +#define MT2712_PIN_7_PWM3__FUNC_DISP0_PWM (MTK_PIN_NO(7) | 3) > > +#define MT2712_PIN_7_PWM3__FUNC_LCM_RST2 (MTK_PIN_NO(7) | 4) > > +#define MT2712_PIN_7_PWM3__FUNC_DIN_D0 (MTK_PIN_NO(7) | 5) > &
Re: [PATCH v2 4/4] pintcrl: support bias-disable of generic and special pins simultaneously
On Wed, 2018-02-28 at 15:33 +0800, Sean Wang wrote:
> On Mon, 2018-02-26 at 16:34 +0800, Zhiyong Tao wrote:
> > For generic pins, parameter "arg" is 0 or 1.
> > For special pins, bias-disable is set by R0R1,
> > so we need transmited "00" to set bias-disable
> > When we set "bias-disable" as high-z property,
> > the parameter should be "MTK_PUPD_SET_R1R0_00".
> >
> > Signed-off-by: Zhiyong Tao <zhiyong@mediatek.com>
> > ---
> > drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 13 +++--
> > 1 file changed, 11 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
> > b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
> > index 3cf384f..e88ba04 100644
> > --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
> > +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
> > @@ -301,8 +301,17 @@ static int mtk_pconf_set_pull_select(struct
> > mtk_pinctrl *pctl,
> > * resistor bit, so we need this special handle.
> > */
> > if (pctl->devdata->spec_pull_set) {
> > - ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
> > - pin, pctl->devdata->port_align, isup, arg);
> > + if (enable) {
> > + ret = pctl->devdata->spec_pull_set(
> > + mtk_get_regmap(pctl, pin), pin,
> > + pctl->devdata->port_align, isup,
> > + arg);
> > + } else {
> > + ret = pctl->devdata->spec_pull_set(
> > + mtk_get_regmap(pctl, pin), pin,
> > + pctl->devdata->port_align, isup,
> > + MTK_PUPD_SET_R1R0_00);
> > + }
>
>
> it looks like you can use as following snippet with reusing original
> logic and less effort on maintaining these common code (?)
==> Thanks for your suggestion very much. It seems better.
I will change it in v3.
>
>
> if (pctl->devdata->spec_pull_set) {
> + if (!enable)
> + arg = MTK_PUPD_SET_R1R0_00;
>
> ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
> pin, pctl->devdata->port_align, isup, arg);
>
>
> Also, it's better to add more comments to such kind of special path for
> allowing future SoCs to follow and extend more easily.
==> Thanks for your suggestion very much. I will add more comments here.
>
> > if (!ret)
> > return 0;
> > }
>
>
Re: [PATCH v2 4/4] pintcrl: support bias-disable of generic and special pins simultaneously
On Wed, 2018-02-28 at 15:49 +0800, Zhiyong Tao wrote:
> On Wed, 2018-02-28 at 15:33 +0800, Sean Wang wrote:
> > On Mon, 2018-02-26 at 16:34 +0800, Zhiyong Tao wrote:
> > > For generic pins, parameter "arg" is 0 or 1.
> > > For special pins, bias-disable is set by R0R1,
> > > so we need transmited "00" to set bias-disable
> > > When we set "bias-disable" as high-z property,
> > > the parameter should be "MTK_PUPD_SET_R1R0_00".
> > >
> > > Signed-off-by: Zhiyong Tao
> > > ---
> > > drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 13 +++--
> > > 1 file changed, 11 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
> > > b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
> > > index 3cf384f..e88ba04 100644
> > > --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
> > > +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
> > > @@ -301,8 +301,17 @@ static int mtk_pconf_set_pull_select(struct
> > > mtk_pinctrl *pctl,
> > >* resistor bit, so we need this special handle.
> > >*/
> > > if (pctl->devdata->spec_pull_set) {
> > > - ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
> > > - pin, pctl->devdata->port_align, isup, arg);
> > > + if (enable) {
> > > + ret = pctl->devdata->spec_pull_set(
> > > + mtk_get_regmap(pctl, pin), pin,
> > > + pctl->devdata->port_align, isup,
> > > + arg);
> > > + } else {
> > > + ret = pctl->devdata->spec_pull_set(
> > > + mtk_get_regmap(pctl, pin), pin,
> > > + pctl->devdata->port_align, isup,
> > > + MTK_PUPD_SET_R1R0_00);
> > > + }
> >
> >
> > it looks like you can use as following snippet with reusing original
> > logic and less effort on maintaining these common code (?)
> ==> Thanks for your suggestion very much. It seems better.
> I will change it in v3.
==>
Hi sean,
we try it in our site. we can't change like this.
Because we will check "arg" after setting "arg = MTK_PUPD_SET_R1R0_00;".
following snippet which check "arg" value is o or 1. If it not, which
will print error. so we can't change like this.
/* For generic pull config, default arg value should be 0 or 1. */
if (arg != 0 && arg != 1) {
dev_err(pctl->dev, "invalid pull-up argument %d on pin %d .\n", arg,
pin);
return -EINVAL;
}
Thanks.
> >
> >
> > if (pctl->devdata->spec_pull_set) {
> > + if (!enable)
> > + arg = MTK_PUPD_SET_R1R0_00;
> >
> > ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
> > pin, pctl->devdata->port_align, isup, arg);
> >
> >
> > Also, it's better to add more comments to such kind of special path for
> > allowing future SoCs to follow and extend more easily.
>
> ==> Thanks for your suggestion very much. I will add more comments here.
> >
> > > if (!ret)
> > > return 0;
> > > }
> >
> >
>
[PATCH v4 1/5] arm64: dts: mt2712: add pintcrl file
This patch adds pinctrl file for mt2712. Signed-off-by: Zhiyong Tao Reviewed-by: Rob Herring --- arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h | 1123 + 1 file changed, 1123 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h diff --git a/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h new file mode 100644 index 000..1b4cb0c --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h @@ -0,0 +1,1123 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + * Author: Zhiyong Tao + * + */ +#ifndef __DTS_MT2712_PINFUNC_H +#define __DTS_MT2712_PINFUNC_H + +#include + +#define MT2712_PIN_0_EINT0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define MT2712_PIN_0_EINT0__FUNC_EINT0 (MTK_PIN_NO(0) | 1) +#define MT2712_PIN_0_EINT0__FUNC_MBIST_DIAG_SCANOUT (MTK_PIN_NO(0) | 2) +#define MT2712_PIN_0_EINT0__FUNC_DSIA_TE (MTK_PIN_NO(0) | 3) +#define MT2712_PIN_0_EINT0__FUNC_DSIC_TE (MTK_PIN_NO(0) | 4) +#define MT2712_PIN_0_EINT0__FUNC_DIN_D3 (MTK_PIN_NO(0) | 5) +#define MT2712_PIN_0_EINT0__FUNC_PURE_HW_PROTECT (MTK_PIN_NO(0) | 6) + +#define MT2712_PIN_1_EINT1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define MT2712_PIN_1_EINT1__FUNC_EINT1 (MTK_PIN_NO(1) | 1) +#define MT2712_PIN_1_EINT1__FUNC_IR_IN (MTK_PIN_NO(1) | 2) +#define MT2712_PIN_1_EINT1__FUNC_DSIB_TE (MTK_PIN_NO(1) | 3) +#define MT2712_PIN_1_EINT1__FUNC_DSID_TE (MTK_PIN_NO(1) | 4) +#define MT2712_PIN_1_EINT1__FUNC_DIN_D4 (MTK_PIN_NO(1) | 5) + +#define MT2712_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define MT2712_PIN_2_EINT2__FUNC_EINT2 (MTK_PIN_NO(2) | 1) +#define MT2712_PIN_2_EINT2__FUNC_IR_IN (MTK_PIN_NO(2) | 2) +#define MT2712_PIN_2_EINT2__FUNC_LCM_RST1 (MTK_PIN_NO(2) | 3) +#define MT2712_PIN_2_EINT2__FUNC_DIN_D5 (MTK_PIN_NO(2) | 5) + +#define MT2712_PIN_3_EINT3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define MT2712_PIN_3_EINT3__FUNC_EINT3 (MTK_PIN_NO(3) | 1) +#define MT2712_PIN_3_EINT3__FUNC_IR_IN (MTK_PIN_NO(3) | 2) +#define MT2712_PIN_3_EINT3__FUNC_LCM_RST0 (MTK_PIN_NO(3) | 3) +#define MT2712_PIN_3_EINT3__FUNC_DIN_D6 (MTK_PIN_NO(3) | 5) + +#define MT2712_PIN_4_PWM0__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define MT2712_PIN_4_PWM0__FUNC_PWM0 (MTK_PIN_NO(4) | 1) +#define MT2712_PIN_4_PWM0__FUNC_DISP0_PWM (MTK_PIN_NO(4) | 2) +#define MT2712_PIN_4_PWM0__FUNC_DISP1_PWM (MTK_PIN_NO(4) | 3) +#define MT2712_PIN_4_PWM0__FUNC_DIN_CLK (MTK_PIN_NO(4) | 5) + +#define MT2712_PIN_5_PWM1__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define MT2712_PIN_5_PWM1__FUNC_PWM1 (MTK_PIN_NO(5) | 1) +#define MT2712_PIN_5_PWM1__FUNC_DISP1_PWM (MTK_PIN_NO(5) | 2) +#define MT2712_PIN_5_PWM1__FUNC_DISP0_PWM (MTK_PIN_NO(5) | 3) +#define MT2712_PIN_5_PWM1__FUNC_DIN_VSYNC (MTK_PIN_NO(5) | 5) + +#define MT2712_PIN_6_PWM2__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define MT2712_PIN_6_PWM2__FUNC_PWM2 (MTK_PIN_NO(6) | 1) +#define MT2712_PIN_6_PWM2__FUNC_DISP0_PWM (MTK_PIN_NO(6) | 2) +#define MT2712_PIN_6_PWM2__FUNC_DISP1_PWM (MTK_PIN_NO(6) | 3) +#define MT2712_PIN_6_PWM2__FUNC_DISP2_PWM (MTK_PIN_NO(6) | 4) +#define MT2712_PIN_6_PWM2__FUNC_DIN_HSYNC (MTK_PIN_NO(6) | 5) + +#define MT2712_PIN_7_PWM3__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define MT2712_PIN_7_PWM3__FUNC_PWM3 (MTK_PIN_NO(7) | 1) +#define MT2712_PIN_7_PWM3__FUNC_DISP1_PWM (MTK_PIN_NO(7) | 2) +#define MT2712_PIN_7_PWM3__FUNC_DISP0_PWM (MTK_PIN_NO(7) | 3) +#define MT2712_PIN_7_PWM3__FUNC_LCM_RST2 (MTK_PIN_NO(7) | 4) +#define MT2712_PIN_7_PWM3__FUNC_DIN_D0 (MTK_PIN_NO(7) | 5) + +#define MT2712_PIN_8_PWM4__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define MT2712_PIN_8_PWM4__FUNC_PWM4 (MTK_PIN_NO(8) | 1) +#define MT2712_PIN_8_PWM4__FUNC_DISP0_PWM (MTK_PIN_NO(8) | 2) +#define MT2712_PIN_8_PWM4__FUNC_DISP1_PWM (MTK_PIN_NO(8) | 3) +#define MT2712_PIN_8_PWM4__FUNC_DSIA_TE (MTK_PIN_NO(8) | 4) +#define MT2712_PIN_8_PWM4__FUNC_DIN_D1 (MTK_PIN_NO(8) | 5) + +#define MT2712_PIN_9_PWM5__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define MT2712_PIN_9_PWM5__FUNC_PWM5 (MTK_PIN_NO(9) | 1) +#define MT2712_PIN_9_PWM5__FUNC_DISP1_PWM (MTK_PIN_NO(9) | 2) +#define MT2712_PIN_9_PWM5__FUNC_DISP0_PWM (MTK_PIN_NO(9) | 3) +#define MT2712_PIN_9_PWM5__FUNC_DSIB_TE (MTK_PIN_NO(9) | 4) +#define MT2712_PIN_9_PWM5__FUNC_DIN_D2 (MTK_PIN_NO(9) | 5) + +#define MT2712_PIN_10_PWM6__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define MT2712_PIN_10_PWM6__FUNC_PWM6 (MTK_PIN_NO(10) | 1) +#define MT2712_PIN_10_PWM6__FUNC_DISP0_PWM (MTK_PIN_NO(10) | 2) +#define MT2712_PIN_10_PWM6__FUNC_DISP1_PWM (MTK_PIN_NO(10) | 3) +#define MT2712_PIN_10_PWM6__FUNC_LCM_RST0 (MTK_PIN_NO(10) | 4) + +#define MT2712_PIN_11_PWM7__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define MT2712_PIN_11_PWM7__FUNC_PWM7 (MTK_PIN_NO(11) | 1) +#define MT2712_PIN_11_PWM7__FUNC_DISP1_PWM (MTK_PIN_NO(11) | 2) +#define MT2712_PIN_11_PWM7__FUNC_DISP0_PWM (MTK_PIN_NO(11) | 3) +#define MT2712_PIN_11_PWM7__FUNC_LCM_RST1 (MTK_PIN_NO(11) | 4) + +#define MT2712_PIN_12_IDDIG_P0__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define MT2712_PIN_12_IDDIG_P0__FUNC_IDDIG_A (MTK_PIN_NO(12) | 1
[PATCH v4 2/5] arm64: dts: mt2712: add pintcrl device node.
This patch adds pintcrl device node for mt2712.
Signed-off-by: Zhiyong Tao
---
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index d7688bc..fb3b051 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -9,6 +9,7 @@
#include
#include
#include
+#include "mt2712-pinfunc.h"
/ {
compatible = "mediatek,mt2712";
@@ -258,6 +259,23 @@
#clock-cells = <1>;
};
+ syscfg_pctl_a: syscfg_pctl_a@10005000 {
+ compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon";
+ reg = <0 0x10005000 0 0x1000>;
+ };
+
+ pio: pinctrl@10005000 {
+ compatible = "mediatek,mt2712-pinctrl";
+ reg = <0 0x1000b000 0 0x1000>;
+ mediatek,pctl-regmap = <_pctl_a>;
+ pins-are-numbered;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = ;
+ };
+
scpsys: scpsys@10006000 {
compatible = "mediatek,mt2712-scpsys", "syscon";
#power-domain-cells = <1>;
--
1.9.1
[PATCH v4 0/5] PINCTRL: Mediatek pinctrl driver for mt2712
This series includes five patches: 1.Add mt2712 pintcrl head file. 2.Add mt2712 pinctrl device node. 3.Add mt2712 pinctrl driver. 4.Support bias-disable of generic and special pins simultaneously. 5.fix check warnings. Changes in patch v4: 1)fix check warnings for mt2712. 2)add fix check warnings patch for other ICs. Changes in patch v3: 1)Use SPDX identifiers for all new files. 2)Use right data for Copyright and Author. 3)Correct some spelling mistake. 4)Reusing original logic and change solution to support bias-disable of generic and special pins simultaneously. 5)Add some comments for the speical path of special pins bias-disable. Changes in patch v2: 1)Separate patch4 for supporting bias-disable of generic and special pins. 2)GPIO16~17 direction setting is changed as generic pins in mt2712 E2, So remove GPIO16~17 special direction setting and remove apmixedsys node in pinctrl device node. 3)Add pinmux define in "mt2712-pinfunc.h" and "pinctrl-mtk-mt2712.h" for mt2712 E2 design. Zhiyong Tao (5): arm64: dts: mt2712: add pintcrl file arm64: dts: mt2712: add pintcrl device node. pinctrl: add mt2712 pinctrl driver pintcrl: support bias-disable of generic and special pins simultaneously pinctrl: fix check warnings. arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h | 1123 arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 18 + drivers/pinctrl/mediatek/Kconfig |7 + drivers/pinctrl/mediatek/Makefile |1 + drivers/pinctrl/mediatek/pinctrl-mt2712.c | 634 + drivers/pinctrl/mediatek/pinctrl-mtk-common.c |8 +- drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h | 840 drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h | 1757 + drivers/pinctrl/mediatek/pinctrl-mtk-mt6397.h | 123 +- drivers/pinctrl/mediatek/pinctrl-mtk-mt8127.h | 429 ++ drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h | 609 +++-- drivers/pinctrl/mediatek/pinctrl-mtk-mt8173.h | 405 ++ 12 files changed, 4348 insertions(+), 1606 deletions(-) create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt2712.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h -- 2.6.4
[PATCH v4 3/5] pinctrl: add mt2712 pinctrl driver
The commit includes mt2712 pinctrl driver.
Signed-off-by: Zhiyong Tao
---
drivers/pinctrl/mediatek/Kconfig |7 +
drivers/pinctrl/mediatek/Makefile |1 +
drivers/pinctrl/mediatek/pinctrl-mt2712.c | 634 +
drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h | 1757 +
4 files changed, 2399 insertions(+)
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt2712.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 3e59874..862c5db 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -32,6 +32,13 @@ config PINCTRL_MT8127
select PINCTRL_MTK
# For ARMv8 SoCs
+config PINCTRL_MT2712
+ bool "MediaTek MT2712 pin control"
+ depends on OF
+ depends on ARM64 || COMPILE_TEST
+ default ARM64 && ARCH_MEDIATEK
+ select PINCTRL_MTK
+
config PINCTRL_MT7622
bool "MediaTek MT7622 pin control"
depends on OF
diff --git a/drivers/pinctrl/mediatek/Makefile
b/drivers/pinctrl/mediatek/Makefile
index ed7d2b2..7959e77 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
# SoC Drivers
obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o
+obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o
obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2712.c
b/drivers/pinctrl/mediatek/pinctrl-mt2712.c
new file mode 100644
index 000..d14511f
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt2712.c
@@ -0,0 +1,634 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Zhiyong Tao
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pinctrl-mtk-common.h"
+#include "pinctrl-mtk-mt2712.h"
+
+static const struct mtk_pin_spec_pupd_set_samereg mt2712_spec_pupd[] = {
+ MTK_PIN_PUPD_SPEC_SR(18, 0xe50, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(19, 0xe60, 12, 11, 10),
+ MTK_PIN_PUPD_SPEC_SR(20, 0xe50, 5, 4, 3),
+ MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 15, 14, 13),
+ MTK_PIN_PUPD_SPEC_SR(22, 0xe50, 8, 7, 6),
+ MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 2, 1, 0),
+
+ MTK_PIN_PUPD_SPEC_SR(30, 0xf30, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(31, 0xf30, 6, 5, 4),
+ MTK_PIN_PUPD_SPEC_SR(32, 0xf30, 10, 9, 8),
+ MTK_PIN_PUPD_SPEC_SR(33, 0xf30, 14, 13, 12),
+ MTK_PIN_PUPD_SPEC_SR(34, 0xf40, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(35, 0xf40, 6, 5, 4),
+ MTK_PIN_PUPD_SPEC_SR(36, 0xf40, 10, 9, 8),
+ MTK_PIN_PUPD_SPEC_SR(37, 0xc40, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(38, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(39, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(40, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(41, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(42, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(43, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(44, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(45, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(46, 0xc50, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(47, 0xda0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(48, 0xd90, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(49, 0xdf0, 14, 13, 12),
+ MTK_PIN_PUPD_SPEC_SR(50, 0xdf0, 10, 9, 8),
+ MTK_PIN_PUPD_SPEC_SR(51, 0xdf0, 6, 5, 4),
+ MTK_PIN_PUPD_SPEC_SR(52, 0xdf0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(53, 0xd50, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(54, 0xd80, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(55, 0xe00, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(56, 0xd40, 2, 1, 0),
+
+ MTK_PIN_PUPD_SPEC_SR(63, 0xc80, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(64, 0xdb0, 14, 13, 12),
+ MTK_PIN_PUPD_SPEC_SR(65, 0xdb0, 6, 5, 4),
+ MTK_PIN_PUPD_SPEC_SR(66, 0xdb0, 10, 9, 8),
+ MTK_PIN_PUPD_SPEC_SR(67, 0xcd0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(68, 0xdb0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(69, 0xc90, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(70, 0xcc0, 2, 1, 0),
+
+ MTK_PIN_PUPD_SPEC_SR(89, 0xce0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(90, 0xdd0, 14, 13, 12),
+ MTK_PIN_PUPD_SPEC_SR(91, 0xdd0, 10, 9, 8),
+ MTK_PIN_PUPD_SPEC_SR(92, 0xdd0, 6, 5, 4),
+ MTK_PIN_PUPD_SPEC_SR(93, 0xdd0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(94, 0xd20, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(95, 0xcf0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(96, 0xd30, 2, 1, 0),
+
+ MTK_PIN_PUPD_SPEC_SR(135, 0xe50, 11, 10, 9),
+ MTK_PIN_PUPD_SPEC_SR(136, 0xe50, 14, 13, 12),
+ MTK_PIN_PUPD_SPEC_SR(137, 0xe70, 5, 4, 3),
+ MTK_PIN_PUPD_SPEC_SR(138, 0xe70, 8, 7, 6),
+ MTK_PIN_PUPD_SPEC_SR(139, 0xe70, 11, 10, 9),
+ MTK_PIN_PUPD_SPEC_SR(140,
[PATCH v4 4/5] pintcrl: support bias-disable of generic and special pins simultaneously
For generic pins, parameter "arg" is 0 or 1.
For special pins, bias-disable is set by R0R1,
so we need transmited "00" to set bias-disable
When we set "bias-disable" as high-z property,
the parameter should be "MTK_PUPD_SET_R1R0_00".
Signed-off-by: Zhiyong Tao
---
drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index 3cf384f..f991ff3 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -293,7 +293,7 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl
*pctl,
unsigned int pin, bool enable, bool isup, unsigned int arg)
{
unsigned int bit;
- unsigned int reg_pullen, reg_pullsel;
+ unsigned int reg_pullen, reg_pullsel, r1r0;
int ret;
/* Some pins' pull setting are very different,
@@ -301,8 +301,12 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl
*pctl,
* resistor bit, so we need this special handle.
*/
if (pctl->devdata->spec_pull_set) {
+ /* For special pins, bias-disable is set by R1R0,
+* the parameter should be "MTK_PUPD_SET_R1R0_00".
+*/
+ r1r0 = enable ? arg : MTK_PUPD_SET_R1R0_00;
ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
- pin, pctl->devdata->port_align, isup, arg);
+ pin, pctl->devdata->port_align, isup, r1r0);
if (!ret)
return 0;
}
--
1.9.1
[PATCH 3/3] pinctrl: add mt2712 pinctrl driver
The commit includes changes:
1)Add mt2712 pinctrl driver.
2)Arrange "mtk_pinctrl" before "mtk_pinctrl_devdata"
in "pinctrl-mtk-common.h".
3)Add "spec_dir_set" and "spec_dir_get" in "mtk_pinctrl_devdata".
4)Change "spec_dir_set" and add "spec_dir_get" in "pinctrl-mt2701.c"
and "pinctrl-mtk-common.c".
5)Change "port_mask" from "7" to "6" for EINT.
6)Remove generic pull config condition in "mtk_pconf_set_pull_select".
7)Change "arg" to "MTK_PUPD_SET_R1R0_00" of "mtk_pconf_set_pull_select".
Signed-off-by: Zhiyong Tao
---
drivers/pinctrl/mediatek/Kconfig |8 +
drivers/pinctrl/mediatek/Makefile |1 +
drivers/pinctrl/mediatek/pinctrl-mt2701.c | 21 +-
drivers/pinctrl/mediatek/pinctrl-mt2712.c | 670 +
drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 16 +-
drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 44 +-
drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h | 1858 +
7 files changed, 2586 insertions(+), 32 deletions(-)
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt2712.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index fac9866..2e7be73 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -31,6 +31,14 @@ config PINCTRL_MT8127
select PINCTRL_MTK
# For ARMv8 SoCs
+
+config PINCTRL_MT2712
+ bool "Mediatek MT2712 pin control"
+ depends on OF
+ depends on ARM64 || COMPILE_TEST
+ default ARM64 && ARCH_MEDIATEK
+ select PINCTRL_MTK
+
config PINCTRL_MT8173
bool "Mediatek MT8173 pin control"
depends on OF
diff --git a/drivers/pinctrl/mediatek/Makefile
b/drivers/pinctrl/mediatek/Makefile
index e59c613..26c7435 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -3,6 +3,7 @@ obj-y += pinctrl-mtk-common.o
# SoC Drivers
obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o
+obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o
obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2701.c
b/drivers/pinctrl/mediatek/pinctrl-mt2701.c
index f86f3b3..4a43f5c 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt2701.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c
@@ -503,10 +503,26 @@ static void mt2701_spec_pinmux_set(struct regmap *reg,
unsigned int pin,
regmap_update_bits(reg, mt2701_spec_pinmux[i].offset, mask, value);
}
-static void mt2701_spec_dir_set(unsigned int *reg_addr, unsigned int pin)
+static int mt2701_spec_dir_set(struct mtk_pinctrl *pctl,
+ unsigned int *reg_addr,
+ unsigned int pin,
+ bool input)
{
if (pin > 175)
*reg_addr += 0x10;
+
+ return 0;
+}
+
+static int mt2701_spec_dir_get(struct mtk_pinctrl *pctl,
+ unsigned int *reg_addr,
+ unsigned int pin,
+ bool input)
+{
+ if (pin > 175)
+ *reg_addr += 0x10;
+
+ return 0;
}
static const struct mtk_pinctrl_devdata mt2701_pinctrl_data = {
@@ -520,6 +536,7 @@ static void mt2701_spec_dir_set(unsigned int *reg_addr,
unsigned int pin)
.spec_ies_smt_set = mt2701_ies_smt_set,
.spec_pinmux_set = mt2701_spec_pinmux_set,
.spec_dir_set = mt2701_spec_dir_set,
+ .spec_dir_get = mt2701_spec_dir_get,
.dir_offset = 0x,
.pullen_offset = 0x0150,
.pullsel_offset = 0x0280,
@@ -551,7 +568,7 @@ static void mt2701_spec_dir_set(unsigned int *reg_addr,
unsigned int pin)
.dbnc_ctrl = 0x500,
.dbnc_set = 0x600,
.dbnc_clr = 0x700,
- .port_mask = 6,
+ .port_mask = 7,
.ports = 6,
},
.ap_num = 169,
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2712.c
b/drivers/pinctrl/mediatek/pinctrl-mt2712.c
new file mode 100644
index 000..c933b75
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt2712.c
@@ -0,0 +1,670 @@
+/*
+ * Copyright (c) 2014-2015 MediaTek Inc.
+ * Author: Hongzhou.Yang
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GN
[PATCH 0/3] PINCTRL: Mediatek pinctrl driver for mt2712
This series includes three patches: 1.Add mt2712 compatible node in binding document. 2.Add mt2712 pinctrl device node. 3.Add mt2712 pinctrl driver. Zhiyong Tao (3): dt-bindings: pinctrl: mt2712: add binding document arm64: dts: mt2712: add pintcrl device node. pinctrl: add mt2712 pinctrl driver .../devicetree/bindings/pinctrl/pinctrl-mt65xx.txt |1 + arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h | 1014 +++ arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 18 + drivers/pinctrl/mediatek/Kconfig |8 + drivers/pinctrl/mediatek/Makefile |1 + drivers/pinctrl/mediatek/pinctrl-mt2701.c | 21 +- drivers/pinctrl/mediatek/pinctrl-mt2712.c | 670 +++ drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 16 +- drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 44 +- drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h | 1858 10 files changed, 3619 insertions(+), 32 deletions(-) create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt2712.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h -- 1.9.1
[PATCH 2/3] arm64: dts: mt2712: add pintcrl device node.
The commit includes two change: 1)add pintcrl device node for mt2712. 2)add pinfunc file for mt2712. Signed-off-by: Zhiyong Tao --- arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h | 1014 + arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 18 + 2 files changed, 1032 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h diff --git a/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h new file mode 100644 index 000..fe9d7bd --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h @@ -0,0 +1,1014 @@ +/* + * Copyright (C) 2015 MediaTek Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __DTS_MT2712_PINFUNC_H +#define __DTS_MT2712_PINFUNC_H + +#include + +#define MT2712_PIN_0_EINT0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define MT2712_PIN_0_EINT0__FUNC_EINT0 (MTK_PIN_NO(0) | 1) +#define MT2712_PIN_0_EINT0__FUNC_MBIST_DIAG_SCANOUT (MTK_PIN_NO(0) | 2) +#define MT2712_PIN_0_EINT0__FUNC_DSIA_TE (MTK_PIN_NO(0) | 3) +#define MT2712_PIN_0_EINT0__FUNC_DIN_D3 (MTK_PIN_NO(0) | 5) + +#define MT2712_PIN_1_EINT1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define MT2712_PIN_1_EINT1__FUNC_EINT1 (MTK_PIN_NO(1) | 1) +#define MT2712_PIN_1_EINT1__FUNC_IR_IN (MTK_PIN_NO(1) | 2) +#define MT2712_PIN_1_EINT1__FUNC_DSIB_TE (MTK_PIN_NO(1) | 3) +#define MT2712_PIN_1_EINT1__FUNC_DIN_D4 (MTK_PIN_NO(1) | 5) + +#define MT2712_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define MT2712_PIN_2_EINT2__FUNC_EINT2 (MTK_PIN_NO(2) | 1) +#define MT2712_PIN_2_EINT2__FUNC_IR_IN (MTK_PIN_NO(2) | 2) +#define MT2712_PIN_2_EINT2__FUNC_LCM_RST1 (MTK_PIN_NO(2) | 3) +#define MT2712_PIN_2_EINT2__FUNC_DIN_D5 (MTK_PIN_NO(2) | 5) + +#define MT2712_PIN_3_EINT3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define MT2712_PIN_3_EINT3__FUNC_EINT3 (MTK_PIN_NO(3) | 1) +#define MT2712_PIN_3_EINT3__FUNC_IR_IN (MTK_PIN_NO(3) | 2) +#define MT2712_PIN_3_EINT3__FUNC_LCM_RST0 (MTK_PIN_NO(3) | 3) +#define MT2712_PIN_3_EINT3__FUNC_DIN_D6 (MTK_PIN_NO(3) | 5) + +#define MT2712_PIN_4_PWM0__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define MT2712_PIN_4_PWM0__FUNC_PWM0 (MTK_PIN_NO(4) | 1) +#define MT2712_PIN_4_PWM0__FUNC_DISP0_PWM (MTK_PIN_NO(4) | 2) +#define MT2712_PIN_4_PWM0__FUNC_DISP1_PWM (MTK_PIN_NO(4) | 3) +#define MT2712_PIN_4_PWM0__FUNC_DIN_CLK (MTK_PIN_NO(4) | 5) + +#define MT2712_PIN_5_PWM1__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define MT2712_PIN_5_PWM1__FUNC_PWM1 (MTK_PIN_NO(5) | 1) +#define MT2712_PIN_5_PWM1__FUNC_DISP1_PWM (MTK_PIN_NO(5) | 2) +#define MT2712_PIN_5_PWM1__FUNC_DISP0_PWM (MTK_PIN_NO(5) | 3) +#define MT2712_PIN_5_PWM1__FUNC_DIN_VSYNC (MTK_PIN_NO(5) | 5) + +#define MT2712_PIN_6_PWM2__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define MT2712_PIN_6_PWM2__FUNC_PWM2 (MTK_PIN_NO(6) | 1) +#define MT2712_PIN_6_PWM2__FUNC_DISP0_PWM (MTK_PIN_NO(6) | 2) +#define MT2712_PIN_6_PWM2__FUNC_DISP1_PWM (MTK_PIN_NO(6) | 3) +#define MT2712_PIN_6_PWM2__FUNC_DIN_HSYNC (MTK_PIN_NO(6) | 5) + +#define MT2712_PIN_7_PWM3__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define MT2712_PIN_7_PWM3__FUNC_PWM3 (MTK_PIN_NO(7) | 1) +#define MT2712_PIN_7_PWM3__FUNC_DISP1_PWM (MTK_PIN_NO(7) | 2) +#define MT2712_PIN_7_PWM3__FUNC_DISP0_PWM (MTK_PIN_NO(7) | 3) +#define MT2712_PIN_7_PWM3__FUNC_DIN_D0 (MTK_PIN_NO(7) | 5) + +#define MT2712_PIN_8_PWM4__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define MT2712_PIN_8_PWM4__FUNC_PWM4 (MTK_PIN_NO(8) | 1) +#define MT2712_PIN_8_PWM4__FUNC_DISP0_PWM (MTK_PIN_NO(8) | 2) +#define MT2712_PIN_8_PWM4__FUNC_DISP1_PWM (MTK_PIN_NO(8) | 3) +#define MT2712_PIN_8_PWM4__FUNC_DSIA_TE (MTK_PIN_NO(8) | 4) +#define MT2712_PIN_8_PWM4__FUNC_DIN_D1 (MTK_PIN_NO(8) | 5) + +#define MT2712_PIN_9_PWM5__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define MT2712_PIN_9_PWM5__FUNC_PWM5 (MTK_PIN_NO(9) | 1) +#define MT2712_PIN_9_PWM5__FUNC_DISP1_PWM (MTK_PIN_NO(9) | 2) +#define MT2712_PIN_9_PWM5__FUNC_DISP0_PWM (MTK_PIN_NO(9) | 3) +#define MT2712_PIN_9_PWM5__FUNC_DSIB_TE (MTK_PIN_NO(9) | 4) +#define MT2712_PIN_9_PWM5__FUNC_DIN_D2 (MTK_PIN_NO(9) | 5) + +#define MT2712_PIN_10_PWM6__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define MT2712_PIN_10_PWM6__FUNC_PWM6 (MTK_PIN_NO(10) | 1) +#define MT2712_PIN_10_PWM6__FUNC_DISP0_PWM (MTK_PIN_NO(10) | 2) +#define MT2712_PIN_10_PWM6__FUNC_DISP1_PWM (MTK_PIN_NO(10) | 3) +#define MT2712_PIN_10_PWM6__FUNC_LCM_RST0 (MTK_PIN_NO(10) | 4) + +#define MT2712_PIN_11_PWM7__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define MT2712_PIN_11_PWM7__FUNC_PWM7 (MTK_PIN_NO(11) | 1) +#define MT2712_PIN_11_PWM7__FUNC_DISP1_PWM (MTK_PIN_NO(11) | 2) +#define MT2712_PIN_11_PWM7__FUNC_DISP0_PWM (MTK_PIN_NO(11) | 3) +#define MT2712_PIN_11_PWM7__FUNC_LCM_RST1
[PATCH 1/3] dt-bindings: pinctrl: mt2712: add binding document
The commit adds mt2712 compatible node in binding document. Signed-off-by: Zhiyong Tao --- .../devicetree/bindings/pinctrl/pinctrl-mt65xx.txt |1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt index 17631d0..37d7447 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt @@ -5,6 +5,7 @@ The Mediatek's Pin controller is used to control SoC pins. Required properties: - compatible: value should be one of the following. "mediatek,mt2701-pinctrl", compatible with mt2701 pinctrl. + "mediatek,mt2712-pinctrl", compatible with mt2712 pinctrl. "mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl. "mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl. "mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl. -- 1.7.9.5
Re: [PATCH 3/3] pinctrl: add mt2712 pinctrl driver
On Thu, 2017-08-03 at 10:00 +0800, Yingjoe Chen wrote:
> On Wed, 2017-08-02 at 14:03 +0800, Zhiyong Tao wrote:
> > On Tue, 2017-08-01 at 17:14 +0800, Yingjoe Chen wrote:
> > >
> > > Hi Zhiyong,
> > >
> > >
> > >
> > > On Mon, 2017-07-31 at 16:22 +0800, Zhiyong Tao wrote:
> > > <...>
> > > > 3)Add "spec_dir_set" and "spec_dir_get" in "mtk_pinctrl_devdata".
> > > > 4)Change "spec_dir_set" and add "spec_dir_get" in "pinctrl-mt2701.c"
> > > > and "pinctrl-mtk-common.c".
> > >
> > > I think these deserve another patch.
> > > Please also explain why we need this.
> >
> > ==> ok, I will separate it in another patch in the next version.
> > Because we should control another gpio base register for gpio16 and 17
> > in mt2712 E1. It is special for the direction control in gpio16 and
> > gpio17.
> > >
> > >
> > > > 5)Change "port_mask" from "7" to "6" for EINT.
> > >
> > > I'm assuming this is a bug fix for mt2701?
> > > If yes, this should be a separate patch.
> >
> > ==> yes, it is a bug fix for mt2701. When I use EINT bothe edge triggle,
> > offset can't get the offset address which offset address is 1/3/5/7.
> > I will separate it in another patch in the next version.
> > >
> > > > 6)Remove generic pull config condition in "mtk_pconf_set_pull_select".
> > > > 7)Change "arg" to "MTK_PUPD_SET_R1R0_00" of "mtk_pconf_set_pull_select".
> > >
> > > Why we need to change arg?
> >
> > ==> to parse the "bias-disable" property in dts for special pins.
> >
> > >
> > >
> > > >
> > > > Signed-off-by: Zhiyong Tao
> > > > ---
> > > > drivers/pinctrl/mediatek/Kconfig |8 +
> > > > drivers/pinctrl/mediatek/Makefile |1 +
> > > > drivers/pinctrl/mediatek/pinctrl-mt2701.c | 21 +-
> > > > drivers/pinctrl/mediatek/pinctrl-mt2712.c | 670 +
> > > > drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 16 +-
> > > > drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 44 +-
> > > > drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h | 1858
> > > > +
> > > > 7 files changed, 2586 insertions(+), 32 deletions(-)
> > > > create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt2712.c
> > > > create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h
> > > >
> > >
> > > <...>
> > >
> > > > diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2701.c
> > > > b/drivers/pinctrl/mediatek/pinctrl-mt2701.c
> > > > index f86f3b3..4a43f5c 100644
> > > > --- a/drivers/pinctrl/mediatek/pinctrl-mt2701.c
> > > > +++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c
> > > > @@ -503,10 +503,26 @@ static void mt2701_spec_pinmux_set(struct regmap
> > > > *reg, unsigned int pin,
> > > > regmap_update_bits(reg, mt2701_spec_pinmux[i].offset, mask,
> > > > value);
> > > > }
> > > >
> > > > -static void mt2701_spec_dir_set(unsigned int *reg_addr, unsigned int
> > > > pin)
> > > > +static int mt2701_spec_dir_set(struct mtk_pinctrl *pctl,
> > > > + unsigned int *reg_addr,
> > > > + unsigned int pin,
> > > > + bool input)
> > > > {
> > > > if (pin > 175)
> > > > *reg_addr += 0x10;
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +static int mt2701_spec_dir_get(struct mtk_pinctrl *pctl,
> > > > + unsigned int *reg_addr,
> > > > + unsigned int pin,
> > > > + bool input)
> > >
> > > incorrect prototype?
> > >
> > > > +{
> > > > + if (pin > 175)
> > > > + *reg_addr += 0x10;
> > > > +
> > > > + return 0;
> > > > }
> > > >
> > > > static const struct mtk_pinctrl_devdata mt2701_pinctrl_data = {
> > > > @@ -520,6 +536,7 @@ stat
[PATCH 1/3] dt-bindings: adc: mt2712: add binding document
The commit adds mt2712 compatible node in binding document. Signed-off-by: Zhiyong Tao --- .../devicetree/bindings/iio/adc/mt6577_auxadc.txt |1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt b/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt index 64dc484..0df9bef 100644 --- a/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt +++ b/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt @@ -12,6 +12,7 @@ for the Thermal Controller which holds a phandle to the AUXADC. Required properties: - compatible: Should be one of: - "mediatek,mt2701-auxadc": For MT2701 family of SoCs +- "mediatek,mt2712-auxadc": For MT2712 family of SoCs - "mediatek,mt7622-auxadc": For MT7622 family of SoCs - "mediatek,mt8173-auxadc": For MT8173 family of SoCs - reg: Address range of the AUXADC unit. -- 1.7.9.5
[PATCH 2/3] iio: adc: mt2712: Add compatible node for mt2712.
This commit adds mt2712 compatible node.
Signed-off-by: Zhiyong Tao
---
drivers/iio/adc/mt6577_auxadc.c |1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iio/adc/mt6577_auxadc.c b/drivers/iio/adc/mt6577_auxadc.c
index 414cf44..70bfa1e 100644
--- a/drivers/iio/adc/mt6577_auxadc.c
+++ b/drivers/iio/adc/mt6577_auxadc.c
@@ -306,6 +306,7 @@ static SIMPLE_DEV_PM_OPS(mt6577_auxadc_pm_ops,
static const struct of_device_id mt6577_auxadc_of_match[] = {
{ .compatible = "mediatek,mt2701-auxadc", },
+ { .compatible = "mediatek,mt2712-auxadc", },
{ .compatible = "mediatek,mt7622-auxadc", },
{ .compatible = "mediatek,mt8173-auxadc", },
{ }
--
1.7.9.5
[PATCH 3/3] arm64: dts: mt2712: Add auxadc device node.
Add auxadc device node for MT2712.
Signed-off-by: Zhiyong Tao
---
This patch dependents on "Mediatek MT2712 clock and scpsys support"[1].
Please accept this patch together with [1].
[1]http://lists.infradead.org/pipermail/linux-mediatek/2017-September/010461.html
---
arch/arm64/boot/dts/mediatek/mt2712-evb.dts |4
arch/arm64/boot/dts/mediatek/mt2712e.dtsi |9 +
2 files changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
index 14163b9..76cbf4a 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
@@ -28,6 +28,10 @@
};
};
+ {
+ status = "okay";
+};
+
{
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index 3232e4e..bf65c92 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -225,6 +225,15 @@
(GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ auxadc: adc@11001000 {
+ compatible = "mediatek,mt2712-auxadc";
+ reg = <0 0x11001000 0 0x1000>;
+ clocks = < CLK_PERI_AUXADC>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,mt2712-uart",
"mediatek,mt6577-uart";
--
1.7.9.5
[PATCH 0/3] AUXADC: Mediatek auxadc driver for mt2712
This series includes three patches: 1.Add mt2712 auxadc compatible node in binding document. 2.Add mt2712 auxadc compatible node in "mt6577_auxadc.c". 2.Add mt2712 auxadc device node. Zhiyong Tao (3): dt-bindings: adc: mt2712: add binding document iio: adc: mt2712: Add compatible node for mt2712. arm64: dts: mt2712: Add auxadc device node. .../devicetree/bindings/iio/adc/mt6577_auxadc.txt |1 + arch/arm64/boot/dts/mediatek/mt2712-evb.dts|4 arch/arm64/boot/dts/mediatek/mt2712e.dtsi |9 + drivers/iio/adc/mt6577_auxadc.c|1 + 4 files changed, 15 insertions(+) -- 1.7.9.5
Re: [PATCH 0/3] PINCTRL: Mediatek pinctrl driver for mt2712
On Tue, 2017-08-01 at 16:44 +0800, Yingjoe Chen wrote: > On Mon, 2017-07-31 at 16:22 +0800, Zhiyong Tao wrote: > > This series includes three patches: > > 1.Add mt2712 compatible node in binding document. > > 2.Add mt2712 pinctrl device node. > > 3.Add mt2712 pinctrl driver. > > > > Zhiyong Tao (3): > > dt-bindings: pinctrl: mt2712: add binding document > > arm64: dts: mt2712: add pintcrl device node. > > pinctrl: add mt2712 pinctrl driver > > > > .../devicetree/bindings/pinctrl/pinctrl-mt65xx.txt |1 + > > arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h | 1014 +++ > > arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 18 + > > mt2712e.dtsi doesn't exists in v4.13-rc1. > What's the base for this series? > > > > ==> This patch is based on http://lists.infradead.org/pipermail/linux-mediatek/2017-July/009618.html I forgot to add the comment, I will add it in the next version. Thanks.
Re: [PATCH 3/3] pinctrl: add mt2712 pinctrl driver
On Tue, 2017-08-01 at 17:14 +0800, Yingjoe Chen wrote:
>
> Hi Zhiyong,
>
>
>
> On Mon, 2017-07-31 at 16:22 +0800, Zhiyong Tao wrote:
> <...>
> > 3)Add "spec_dir_set" and "spec_dir_get" in "mtk_pinctrl_devdata".
> > 4)Change "spec_dir_set" and add "spec_dir_get" in "pinctrl-mt2701.c"
> > and "pinctrl-mtk-common.c".
>
> I think these deserve another patch.
> Please also explain why we need this.
==> ok, I will separate it in another patch in the next version.
Because we should control another gpio base register for gpio16 and 17
in mt2712 E1. It is special for the direction control in gpio16 and
gpio17.
>
>
> > 5)Change "port_mask" from "7" to "6" for EINT.
>
> I'm assuming this is a bug fix for mt2701?
> If yes, this should be a separate patch.
==> yes, it is a bug fix for mt2701. When I use EINT bothe edge triggle,
offset can't get the offset address which offset address is 1/3/5/7.
I will separate it in another patch in the next version.
>
> > 6)Remove generic pull config condition in "mtk_pconf_set_pull_select".
> > 7)Change "arg" to "MTK_PUPD_SET_R1R0_00" of "mtk_pconf_set_pull_select".
>
> Why we need to change arg?
==> to parse the "bias-disable" property in dts for special pins.
>
>
> >
> > Signed-off-by: Zhiyong Tao
> > ---
> > drivers/pinctrl/mediatek/Kconfig |8 +
> > drivers/pinctrl/mediatek/Makefile |1 +
> > drivers/pinctrl/mediatek/pinctrl-mt2701.c | 21 +-
> > drivers/pinctrl/mediatek/pinctrl-mt2712.c | 670 +
> > drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 16 +-
> > drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 44 +-
> > drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h | 1858
> > +
> > 7 files changed, 2586 insertions(+), 32 deletions(-)
> > create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt2712.c
> > create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h
> >
>
> <...>
>
> > diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2701.c
> > b/drivers/pinctrl/mediatek/pinctrl-mt2701.c
> > index f86f3b3..4a43f5c 100644
> > --- a/drivers/pinctrl/mediatek/pinctrl-mt2701.c
> > +++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c
> > @@ -503,10 +503,26 @@ static void mt2701_spec_pinmux_set(struct regmap
> > *reg, unsigned int pin,
> > regmap_update_bits(reg, mt2701_spec_pinmux[i].offset, mask, value);
> > }
> >
> > -static void mt2701_spec_dir_set(unsigned int *reg_addr, unsigned int pin)
> > +static int mt2701_spec_dir_set(struct mtk_pinctrl *pctl,
> > + unsigned int *reg_addr,
> > + unsigned int pin,
> > + bool input)
> > {
> > if (pin > 175)
> > *reg_addr += 0x10;
> > +
> > + return 0;
> > +}
> > +
> > +static int mt2701_spec_dir_get(struct mtk_pinctrl *pctl,
> > + unsigned int *reg_addr,
> > + unsigned int pin,
> > + bool input)
>
> incorrect prototype?
>
> > +{
> > + if (pin > 175)
> > + *reg_addr += 0x10;
> > +
> > + return 0;
> > }
> >
> > static const struct mtk_pinctrl_devdata mt2701_pinctrl_data = {
> > @@ -520,6 +536,7 @@ static void mt2701_spec_dir_set(unsigned int *reg_addr,
> > unsigned int pin)
> > .spec_ies_smt_set = mt2701_ies_smt_set,
> > .spec_pinmux_set = mt2701_spec_pinmux_set,
> > .spec_dir_set = mt2701_spec_dir_set,
> > + .spec_dir_get = mt2701_spec_dir_get,
> > .dir_offset = 0x,
> > .pullen_offset = 0x0150,
> > .pullsel_offset = 0x0280,
> > @@ -551,7 +568,7 @@ static void mt2701_spec_dir_set(unsigned int *reg_addr,
> > unsigned int pin)
> > .dbnc_ctrl = 0x500,
> > .dbnc_set = 0x600,
> > .dbnc_clr = 0x700,
> > - .port_mask = 6,
> > + .port_mask = 7,
> > .ports = 6,
> > },
> > .ap_num = 169,
> > diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2712.c
> > b/drivers/pinctrl/mediatek/pinctrl-mt2712.c
> > new file mode 100644
> > index 000..c933b75
> > --- /dev/null
> > +++ b/drivers/pinctrl/mediatek/pinctrl-mt2712.c
>
> <...>
>
> > +
> > +static int mt2712_spec_dir_set(stru
[PATCH v2 4/4] pintcrl: support bias-disable of generic and special pins simultaneously
For generic pins, parameter "arg" is 0 or 1.
For special pins, bias-disable is set by R0R1,
so we need transmited "00" to set bias-disable
When we set "bias-disable" as high-z property,
the parameter should be "MTK_PUPD_SET_R1R0_00".
Signed-off-by: Zhiyong Tao
---
drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index 3cf384f..e88ba04 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -301,8 +301,17 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl
*pctl,
* resistor bit, so we need this special handle.
*/
if (pctl->devdata->spec_pull_set) {
- ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
- pin, pctl->devdata->port_align, isup, arg);
+ if (enable) {
+ ret = pctl->devdata->spec_pull_set(
+ mtk_get_regmap(pctl, pin), pin,
+ pctl->devdata->port_align, isup,
+ arg);
+ } else {
+ ret = pctl->devdata->spec_pull_set(
+ mtk_get_regmap(pctl, pin), pin,
+ pctl->devdata->port_align, isup,
+ MTK_PUPD_SET_R1R0_00);
+ }
if (!ret)
return 0;
}
--
1.9.1
[PATCH v2 0/4] PINCTRL: Mediatek pinctrl driver for mt2712
This series includes four patches: 1.Add mt2712 pintcrl head file 2.Add mt2712 pinctrl device node. 3.Add mt2712 pinctrl driver. 4.Support bias-disable of generic and special pins simultaneously Changes in patch v2: 1)Separate patch4 for supporting bias-disable of generic and special pins. 2)GPIO16~17 direction setting is changed as generic pins in mt2712 E2, So remove GPIO16~17 special direction setting and remove apmixedsys node in pinctrl device node. 3)Add pinmux define in "mt2712-pinfunc.h" and "pinctrl-mtk-mt2712.h" for mt2712 E2 design. Zhiyong Tao (4): arm64: dts: mt2712: add pintcrl file arm64: dts: mt2712: add pintcrl device node. pinctrl: add mt2712 pinctrl driver pintcrl: support bias-disable of generic and special pins simultaneously arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h | 1129 ++ arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 18 + drivers/pinctrl/mediatek/Kconfig |7 + drivers/pinctrl/mediatek/Makefile |1 + drivers/pinctrl/mediatek/pinctrl-mt2712.c | 639 drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 13 +- drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h | 1973 + 7 files changed, 3778 insertions(+), 2 deletions(-) create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt2712.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h -- 1.8.1.1.dirty
[PATCH v2 3/4] pinctrl: add mt2712 pinctrl driver
The commit includes mt2712 pinctrl driver.
Signed-off-by: Zhiyong Tao
---
drivers/pinctrl/mediatek/Kconfig |7 +
drivers/pinctrl/mediatek/Makefile |1 +
drivers/pinctrl/mediatek/pinctrl-mt2712.c | 639
drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h | 1973 +
4 files changed, 2620 insertions(+)
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt2712.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 3e59874..b24bc76 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -32,6 +32,13 @@ config PINCTRL_MT8127
select PINCTRL_MTK
# For ARMv8 SoCs
+config PINCTRL_MT2712
+ bool "Mediatek MT2712 pin control"
+ depends on OF
+ depends on ARM64 || COMPILE_TEST
+ default ARM64 && ARCH_MEDIATEK
+ select PINCTRL_MTK
+
config PINCTRL_MT7622
bool "MediaTek MT7622 pin control"
depends on OF
diff --git a/drivers/pinctrl/mediatek/Makefile
b/drivers/pinctrl/mediatek/Makefile
index ed7d2b2..7959e77 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
# SoC Drivers
obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o
+obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o
obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2712.c
b/drivers/pinctrl/mediatek/pinctrl-mt2712.c
new file mode 100644
index 000..b6ae71b
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt2712.c
@@ -0,0 +1,639 @@
+/*
+ * Copyright (c) 2014-2015 MediaTek Inc.
+ * Author: Hongzhou.Yang
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pinctrl-mtk-common.h"
+#include "pinctrl-mtk-mt2712.h"
+
+static const struct mtk_pin_spec_pupd_set_samereg mt2712_spec_pupd[] = {
+ MTK_PIN_PUPD_SPEC_SR(18, 0xe50, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(19, 0xe60, 12, 11, 10),
+ MTK_PIN_PUPD_SPEC_SR(20, 0xe50, 5, 4, 3),
+ MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 15, 14, 13),
+ MTK_PIN_PUPD_SPEC_SR(22, 0xe50, 8, 7, 6),
+ MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 2, 1, 0),
+
+ MTK_PIN_PUPD_SPEC_SR(30, 0xf30, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(31, 0xf30, 6, 5, 4),
+ MTK_PIN_PUPD_SPEC_SR(32, 0xf30, 10, 9, 8),
+ MTK_PIN_PUPD_SPEC_SR(33, 0xf30, 14, 13, 12),
+ MTK_PIN_PUPD_SPEC_SR(34, 0xf40, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(35, 0xf40, 6, 5, 4),
+ MTK_PIN_PUPD_SPEC_SR(36, 0xf40, 10, 9, 8),
+ MTK_PIN_PUPD_SPEC_SR(37, 0xc40, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(38, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(39, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(40, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(41, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(42, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(43, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(44, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(45, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(46, 0xc50, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(47, 0xda0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(48, 0xd90, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(49, 0xdf0, 14, 13, 12),
+ MTK_PIN_PUPD_SPEC_SR(50, 0xdf0, 10, 9, 8),
+ MTK_PIN_PUPD_SPEC_SR(51, 0xdf0, 6, 5, 4),
+ MTK_PIN_PUPD_SPEC_SR(52, 0xdf0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(53, 0xd50, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(54, 0xd80, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(55, 0xe00, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(56, 0xd40, 2, 1, 0),
+
+ MTK_PIN_PUPD_SPEC_SR(63, 0xc80, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(64, 0xdb0, 14, 13, 12),
+ MTK_PIN_PUPD_SPEC_SR(65, 0xdb0, 6, 5, 4),
+ MTK_PIN_PUPD_SPEC_SR(66, 0xdb0, 10, 9, 8),
+ MTK_PIN_PUPD_SPEC_SR(67, 0xcd0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(68, 0xdb0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(69, 0xc90, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(70, 0xcc0, 2, 1, 0),
+
+ MTK_PIN_PUPD_SPEC_SR(89, 0xce0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(90, 0xdd0, 14, 13, 12),
+ MTK_PIN_PUPD_SPEC_SR(91, 0xdd0, 10, 9, 8),
+ MTK_PIN_PUPD_SPEC_SR(92, 0xdd0, 6, 5, 4),
+ MTK_PIN_PUPD_SPEC_SR(93, 0xdd0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(94,
[PATCH v2 1/4] arm64: dts: mt2712: add pintcrl file
This patch adds pinctrl file for mt2712. Signed-off-by: Zhiyong Tao --- arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h | 1129 + 1 file changed, 1129 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h diff --git a/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h new file mode 100644 index 000..44f8ca2 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h @@ -0,0 +1,1129 @@ +/* + * Copyright (C) 2015 MediaTek Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __DTS_MT2712_PINFUNC_H +#define __DTS_MT2712_PINFUNC_H + +#include + +#define MT2712_PIN_0_EINT0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define MT2712_PIN_0_EINT0__FUNC_EINT0 (MTK_PIN_NO(0) | 1) +#define MT2712_PIN_0_EINT0__FUNC_MBIST_DIAG_SCANOUT (MTK_PIN_NO(0) | 2) +#define MT2712_PIN_0_EINT0__FUNC_DSIA_TE (MTK_PIN_NO(0) | 3) +#define MT2712_PIN_0_EINT0__FUNC_DSIC_TE (MTK_PIN_NO(0) | 4) +#define MT2712_PIN_0_EINT0__FUNC_DIN_D3 (MTK_PIN_NO(0) | 5) +#define MT2712_PIN_0_EINT0__FUNC_PURE_HW_PROTECT (MTK_PIN_NO(0) | 6) + +#define MT2712_PIN_1_EINT1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define MT2712_PIN_1_EINT1__FUNC_EINT1 (MTK_PIN_NO(1) | 1) +#define MT2712_PIN_1_EINT1__FUNC_IR_IN (MTK_PIN_NO(1) | 2) +#define MT2712_PIN_1_EINT1__FUNC_DSIB_TE (MTK_PIN_NO(1) | 3) +#define MT2712_PIN_1_EINT1__FUNC_DSID_TE (MTK_PIN_NO(1) | 4) +#define MT2712_PIN_1_EINT1__FUNC_DIN_D4 (MTK_PIN_NO(1) | 5) + +#define MT2712_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define MT2712_PIN_2_EINT2__FUNC_EINT2 (MTK_PIN_NO(2) | 1) +#define MT2712_PIN_2_EINT2__FUNC_IR_IN (MTK_PIN_NO(2) | 2) +#define MT2712_PIN_2_EINT2__FUNC_LCM_RST1 (MTK_PIN_NO(2) | 3) +#define MT2712_PIN_2_EINT2__FUNC_DIN_D5 (MTK_PIN_NO(2) | 5) + +#define MT2712_PIN_3_EINT3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define MT2712_PIN_3_EINT3__FUNC_EINT3 (MTK_PIN_NO(3) | 1) +#define MT2712_PIN_3_EINT3__FUNC_IR_IN (MTK_PIN_NO(3) | 2) +#define MT2712_PIN_3_EINT3__FUNC_LCM_RST0 (MTK_PIN_NO(3) | 3) +#define MT2712_PIN_3_EINT3__FUNC_DIN_D6 (MTK_PIN_NO(3) | 5) + +#define MT2712_PIN_4_PWM0__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define MT2712_PIN_4_PWM0__FUNC_PWM0 (MTK_PIN_NO(4) | 1) +#define MT2712_PIN_4_PWM0__FUNC_DISP0_PWM (MTK_PIN_NO(4) | 2) +#define MT2712_PIN_4_PWM0__FUNC_DISP1_PWM (MTK_PIN_NO(4) | 3) +#define MT2712_PIN_4_PWM0__FUNC_DIN_CLK (MTK_PIN_NO(4) | 5) + +#define MT2712_PIN_5_PWM1__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define MT2712_PIN_5_PWM1__FUNC_PWM1 (MTK_PIN_NO(5) | 1) +#define MT2712_PIN_5_PWM1__FUNC_DISP1_PWM (MTK_PIN_NO(5) | 2) +#define MT2712_PIN_5_PWM1__FUNC_DISP0_PWM (MTK_PIN_NO(5) | 3) +#define MT2712_PIN_5_PWM1__FUNC_DIN_VSYNC (MTK_PIN_NO(5) | 5) + +#define MT2712_PIN_6_PWM2__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define MT2712_PIN_6_PWM2__FUNC_PWM2 (MTK_PIN_NO(6) | 1) +#define MT2712_PIN_6_PWM2__FUNC_DISP0_PWM (MTK_PIN_NO(6) | 2) +#define MT2712_PIN_6_PWM2__FUNC_DISP1_PWM (MTK_PIN_NO(6) | 3) +#define MT2712_PIN_6_PWM2__FUNC_DISP2_PWM (MTK_PIN_NO(6) | 4) +#define MT2712_PIN_6_PWM2__FUNC_DIN_HSYNC (MTK_PIN_NO(6) | 5) + +#define MT2712_PIN_7_PWM3__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define MT2712_PIN_7_PWM3__FUNC_PWM3 (MTK_PIN_NO(7) | 1) +#define MT2712_PIN_7_PWM3__FUNC_DISP1_PWM (MTK_PIN_NO(7) | 2) +#define MT2712_PIN_7_PWM3__FUNC_DISP0_PWM (MTK_PIN_NO(7) | 3) +#define MT2712_PIN_7_PWM3__FUNC_LCM_RST2 (MTK_PIN_NO(7) | 4) +#define MT2712_PIN_7_PWM3__FUNC_DIN_D0 (MTK_PIN_NO(7) | 5) + +#define MT2712_PIN_8_PWM4__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define MT2712_PIN_8_PWM4__FUNC_PWM4 (MTK_PIN_NO(8) | 1) +#define MT2712_PIN_8_PWM4__FUNC_DISP0_PWM (MTK_PIN_NO(8) | 2) +#define MT2712_PIN_8_PWM4__FUNC_DISP1_PWM (MTK_PIN_NO(8) | 3) +#define MT2712_PIN_8_PWM4__FUNC_DSIA_TE (MTK_PIN_NO(8) | 4) +#define MT2712_PIN_8_PWM4__FUNC_DIN_D1 (MTK_PIN_NO(8) | 5) + +#define MT2712_PIN_9_PWM5__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define MT2712_PIN_9_PWM5__FUNC_PWM5 (MTK_PIN_NO(9) | 1) +#define MT2712_PIN_9_PWM5__FUNC_DISP1_PWM (MTK_PIN_NO(9) | 2) +#define MT2712_PIN_9_PWM5__FUNC_DISP0_PWM (MTK_PIN_NO(9) | 3) +#define MT2712_PIN_9_PWM5__FUNC_DSIB_TE (MTK_PIN_NO(9) | 4) +#define MT2712_PIN_9_PWM5__FUNC_DIN_D2 (MTK_PIN_NO(9) | 5) + +#define MT2712_PIN_10_PWM6__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define MT2712_PIN_10_PWM6__FUNC_PWM6 (MTK_PIN_NO(10) | 1) +#define MT2712_PIN_10_PWM6__FUNC_DISP0_PWM (MTK_PIN_NO(10) | 2) +#define MT2712_PIN_10_PWM6__FUNC_DISP1_PWM (MTK_PIN_NO(10) | 3) +#define MT2712_PIN_10_PWM6__FUNC_LCM_RST0 (MTK_PIN_NO(10) | 4) + +#define MT2712_PIN_11_PWM7__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define MT2712_PIN_11_PWM7__FUNC_PWM7
[PATCH v2 2/4] arm64: dts: mt2712: add pintcrl device node.
This patch adds pintcrl device node for mt2712.
Signed-off-by: Zhiyong Tao
---
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index d7688bc..fb3b051 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -9,6 +9,7 @@
#include
#include
#include
+#include "mt2712-pinfunc.h"
/ {
compatible = "mediatek,mt2712";
@@ -258,6 +259,23 @@
#clock-cells = <1>;
};
+ syscfg_pctl_a: syscfg_pctl_a@10005000 {
+ compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon";
+ reg = <0 0x10005000 0 0x1000>;
+ };
+
+ pio: pinctrl@10005000 {
+ compatible = "mediatek,mt2712-pinctrl";
+ reg = <0 0x1000b000 0 0x1000>;
+ mediatek,pctl-regmap = <_pctl_a>;
+ pins-are-numbered;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = ;
+ };
+
scpsys: scpsys@10006000 {
compatible = "mediatek,mt2712-scpsys", "syscon";
#power-domain-cells = <1>;
--
1.9.1
Re: [PATCH v2 4/4] pintcrl: support bias-disable of generic and special pins simultaneously
On Thu, 2018-03-01 at 15:43 +0800, Sean Wang wrote:
> On Thu, 2018-03-01 at 11:47 +0800, Zhiyong Tao wrote:
> > On Wed, 2018-02-28 at 15:49 +0800, Zhiyong Tao wrote:
> > > On Wed, 2018-02-28 at 15:33 +0800, Sean Wang wrote:
> > > > On Mon, 2018-02-26 at 16:34 +0800, Zhiyong Tao wrote:
> > > > > For generic pins, parameter "arg" is 0 or 1.
> > > > > For special pins, bias-disable is set by R0R1,
> > > > > so we need transmited "00" to set bias-disable
> > > > > When we set "bias-disable" as high-z property,
> > > > > the parameter should be "MTK_PUPD_SET_R1R0_00".
> > > > >
> > > > > Signed-off-by: Zhiyong Tao
> > > > > ---
> > > > > drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 13 +++--
> > > > > 1 file changed, 11 insertions(+), 2 deletions(-)
> > > > >
> > > > > diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
> > > > > b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
> > > > > index 3cf384f..e88ba04 100644
> > > > > --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
> > > > > +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
> > > > > @@ -301,8 +301,17 @@ static int mtk_pconf_set_pull_select(struct
> > > > > mtk_pinctrl *pctl,
> > > > >* resistor bit, so we need this special handle.
> > > > >*/
> > > > > if (pctl->devdata->spec_pull_set) {
> > > > > - ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl,
> > > > > pin),
> > > > > - pin, pctl->devdata->port_align, isup, arg);
> > > > > + if (enable) {
> > > > > + ret = pctl->devdata->spec_pull_set(
> > > > > + mtk_get_regmap(pctl, pin), pin,
> > > > > + pctl->devdata->port_align, isup,
> > > > > + arg);
> > > > > + } else {
> > > > > + ret = pctl->devdata->spec_pull_set(
> > > > > + mtk_get_regmap(pctl, pin), pin,
> > > > > + pctl->devdata->port_align, isup,
> > > > > + MTK_PUPD_SET_R1R0_00);
> > > > > + }
> > > >
> > > >
> > > > it looks like you can use as following snippet with reusing original
> > > > logic and less effort on maintaining these common code (?)
> > > ==> Thanks for your suggestion very much. It seems better.
> > > I will change it in v3.
> >
> > ==>
> > Hi sean,
> >
> > we try it in our site. we can't change like this.
> > Because we will check "arg" after setting "arg = MTK_PUPD_SET_R1R0_00;".
> > following snippet which check "arg" value is o or 1. If it not, which
> > will print error. so we can't change like this.
> > /* For generic pull config, default arg value should be 0 or 1. */
> > if (arg != 0 && arg != 1) {
> > dev_err(pctl->dev, "invalid pull-up argument %d on pin %d .\n", arg,
> > pin);
> > return -EINVAL;
> > }
> >
> > Thanks.
>
> why not rewrite it with
==> Hi sean,
Thanks for your comments, we will try to do it. If it is ok, we will
modify it in v3.
>
> @@ -301,8 +301,10 @@ static int mtk_pconf_set_pull_select(struct
> mtk_pinctrl *pctl,
> * resistor bit, so we need this special handle.
> */
> if (pctl->devdata->spec_pull_set) {
> + unsigned int r1r0 = enable ? arg : MTK_PUPD_SET_R1R0_00;
> +
> ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl,
> pin),
> - pin, pctl->devdata->port_align, isup, arg);
> + pin, pctl->devdata->port_align, isup, r1r0);
> if (!ret)
> return 0;
> }
>
> and also I appeared to find another bug in the original code when I had
> a close look at the code path, but it's not related to the patch:
>
> a special pin would still go through the code path to handle
> generic pin when the special pin uses an invalid argument.
>
> It looks like err-code from pctl->devdata->spec_pull_set cannot be
> used directly to judge its pin type. It's also possible to use it as an
> indication of the real failure during special pin is being set up.
>
==>Hi sean,
The function seems ok. it is not related to the patch. We will think
about your comment. If there is better idea to modify the code flow. We
will change it in another patch.
Thanks.
> > > >
> > > >
> > > > if (pctl->devdata->spec_pull_set) {
> > > > + if (!enable)
> > > > + arg = MTK_PUPD_SET_R1R0_00;
> > > >
> > > > ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
> > > > pin, pctl->devdata->port_align, isup, arg);
> > > >
> > > >
> > > > Also, it's better to add more comments to such kind of special path for
> > > > allowing future SoCs to follow and extend more easily.
> > >
> > > ==> Thanks for your suggestion very much. I will add more comments here.
> > > >
> > > > > if (!ret)
> > > > > return 0;
> > > > > }
> > > >
> > > >
> > >
> >
> >
>
>
[PATCH v3 0/4] PINCTRL: Mediatek pinctrl driver for mt2712
This series includes four patches: 1.Add mt2712 pintcrl head file. 2.Add mt2712 pinctrl device node. 3.Add mt2712 pinctrl driver. 4.Support bias-disable of generic and special pins simultaneously. Changes in patch v3: 1)Use SPDX identifiers for all new files. 2)Use right data for Copyright and Author. 3)Correct some spelling mistake. 4)Reusing original logic and change solution to support bias-disable of generic and special pins simultaneously. 5)Add some comments for the speical path of special pins bias-disable. Changes in patch v2: 1)Separate patch4 for supporting bias-disable of generic and special pins. 2)GPIO16~17 direction setting is changed as generic pins in mt2712 E2, So remove GPIO16~17 special direction setting and remove apmixedsys node in pinctrl device node. 3)Add pinmux define in "mt2712-pinfunc.h" and "pinctrl-mtk-mt2712.h" for mt2712 E2 design. Zhiyong Tao (4): arm64: dts: mt2712: add pintcrl file arm64: dts: mt2712: add pintcrl device node. pinctrl: add mt2712 pinctrl driver pintcrl: support bias-disable of generic and special pins simultaneously arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h | 1123 ++ arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 18 + drivers/pinctrl/mediatek/Kconfig |7 + drivers/pinctrl/mediatek/Makefile |1 + drivers/pinctrl/mediatek/pinctrl-mt2712.c | 632 drivers/pinctrl/mediatek/pinctrl-mtk-common.c |6 + drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h | 1967 + 7 files changed, 3754 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt2712.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h -- 2.6.4
[PATCH v3 1/4] arm64: dts: mt2712: add pintcrl file
This patch adds pinctrl file for mt2712. Signed-off-by: Zhiyong Tao --- arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h | 1123 + 1 file changed, 1123 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h diff --git a/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h new file mode 100644 index 000..1b4cb0c --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h @@ -0,0 +1,1123 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + * Author: Zhiyong Tao + * + */ +#ifndef __DTS_MT2712_PINFUNC_H +#define __DTS_MT2712_PINFUNC_H + +#include + +#define MT2712_PIN_0_EINT0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define MT2712_PIN_0_EINT0__FUNC_EINT0 (MTK_PIN_NO(0) | 1) +#define MT2712_PIN_0_EINT0__FUNC_MBIST_DIAG_SCANOUT (MTK_PIN_NO(0) | 2) +#define MT2712_PIN_0_EINT0__FUNC_DSIA_TE (MTK_PIN_NO(0) | 3) +#define MT2712_PIN_0_EINT0__FUNC_DSIC_TE (MTK_PIN_NO(0) | 4) +#define MT2712_PIN_0_EINT0__FUNC_DIN_D3 (MTK_PIN_NO(0) | 5) +#define MT2712_PIN_0_EINT0__FUNC_PURE_HW_PROTECT (MTK_PIN_NO(0) | 6) + +#define MT2712_PIN_1_EINT1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define MT2712_PIN_1_EINT1__FUNC_EINT1 (MTK_PIN_NO(1) | 1) +#define MT2712_PIN_1_EINT1__FUNC_IR_IN (MTK_PIN_NO(1) | 2) +#define MT2712_PIN_1_EINT1__FUNC_DSIB_TE (MTK_PIN_NO(1) | 3) +#define MT2712_PIN_1_EINT1__FUNC_DSID_TE (MTK_PIN_NO(1) | 4) +#define MT2712_PIN_1_EINT1__FUNC_DIN_D4 (MTK_PIN_NO(1) | 5) + +#define MT2712_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define MT2712_PIN_2_EINT2__FUNC_EINT2 (MTK_PIN_NO(2) | 1) +#define MT2712_PIN_2_EINT2__FUNC_IR_IN (MTK_PIN_NO(2) | 2) +#define MT2712_PIN_2_EINT2__FUNC_LCM_RST1 (MTK_PIN_NO(2) | 3) +#define MT2712_PIN_2_EINT2__FUNC_DIN_D5 (MTK_PIN_NO(2) | 5) + +#define MT2712_PIN_3_EINT3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define MT2712_PIN_3_EINT3__FUNC_EINT3 (MTK_PIN_NO(3) | 1) +#define MT2712_PIN_3_EINT3__FUNC_IR_IN (MTK_PIN_NO(3) | 2) +#define MT2712_PIN_3_EINT3__FUNC_LCM_RST0 (MTK_PIN_NO(3) | 3) +#define MT2712_PIN_3_EINT3__FUNC_DIN_D6 (MTK_PIN_NO(3) | 5) + +#define MT2712_PIN_4_PWM0__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define MT2712_PIN_4_PWM0__FUNC_PWM0 (MTK_PIN_NO(4) | 1) +#define MT2712_PIN_4_PWM0__FUNC_DISP0_PWM (MTK_PIN_NO(4) | 2) +#define MT2712_PIN_4_PWM0__FUNC_DISP1_PWM (MTK_PIN_NO(4) | 3) +#define MT2712_PIN_4_PWM0__FUNC_DIN_CLK (MTK_PIN_NO(4) | 5) + +#define MT2712_PIN_5_PWM1__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define MT2712_PIN_5_PWM1__FUNC_PWM1 (MTK_PIN_NO(5) | 1) +#define MT2712_PIN_5_PWM1__FUNC_DISP1_PWM (MTK_PIN_NO(5) | 2) +#define MT2712_PIN_5_PWM1__FUNC_DISP0_PWM (MTK_PIN_NO(5) | 3) +#define MT2712_PIN_5_PWM1__FUNC_DIN_VSYNC (MTK_PIN_NO(5) | 5) + +#define MT2712_PIN_6_PWM2__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define MT2712_PIN_6_PWM2__FUNC_PWM2 (MTK_PIN_NO(6) | 1) +#define MT2712_PIN_6_PWM2__FUNC_DISP0_PWM (MTK_PIN_NO(6) | 2) +#define MT2712_PIN_6_PWM2__FUNC_DISP1_PWM (MTK_PIN_NO(6) | 3) +#define MT2712_PIN_6_PWM2__FUNC_DISP2_PWM (MTK_PIN_NO(6) | 4) +#define MT2712_PIN_6_PWM2__FUNC_DIN_HSYNC (MTK_PIN_NO(6) | 5) + +#define MT2712_PIN_7_PWM3__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define MT2712_PIN_7_PWM3__FUNC_PWM3 (MTK_PIN_NO(7) | 1) +#define MT2712_PIN_7_PWM3__FUNC_DISP1_PWM (MTK_PIN_NO(7) | 2) +#define MT2712_PIN_7_PWM3__FUNC_DISP0_PWM (MTK_PIN_NO(7) | 3) +#define MT2712_PIN_7_PWM3__FUNC_LCM_RST2 (MTK_PIN_NO(7) | 4) +#define MT2712_PIN_7_PWM3__FUNC_DIN_D0 (MTK_PIN_NO(7) | 5) + +#define MT2712_PIN_8_PWM4__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define MT2712_PIN_8_PWM4__FUNC_PWM4 (MTK_PIN_NO(8) | 1) +#define MT2712_PIN_8_PWM4__FUNC_DISP0_PWM (MTK_PIN_NO(8) | 2) +#define MT2712_PIN_8_PWM4__FUNC_DISP1_PWM (MTK_PIN_NO(8) | 3) +#define MT2712_PIN_8_PWM4__FUNC_DSIA_TE (MTK_PIN_NO(8) | 4) +#define MT2712_PIN_8_PWM4__FUNC_DIN_D1 (MTK_PIN_NO(8) | 5) + +#define MT2712_PIN_9_PWM5__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define MT2712_PIN_9_PWM5__FUNC_PWM5 (MTK_PIN_NO(9) | 1) +#define MT2712_PIN_9_PWM5__FUNC_DISP1_PWM (MTK_PIN_NO(9) | 2) +#define MT2712_PIN_9_PWM5__FUNC_DISP0_PWM (MTK_PIN_NO(9) | 3) +#define MT2712_PIN_9_PWM5__FUNC_DSIB_TE (MTK_PIN_NO(9) | 4) +#define MT2712_PIN_9_PWM5__FUNC_DIN_D2 (MTK_PIN_NO(9) | 5) + +#define MT2712_PIN_10_PWM6__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define MT2712_PIN_10_PWM6__FUNC_PWM6 (MTK_PIN_NO(10) | 1) +#define MT2712_PIN_10_PWM6__FUNC_DISP0_PWM (MTK_PIN_NO(10) | 2) +#define MT2712_PIN_10_PWM6__FUNC_DISP1_PWM (MTK_PIN_NO(10) | 3) +#define MT2712_PIN_10_PWM6__FUNC_LCM_RST0 (MTK_PIN_NO(10) | 4) + +#define MT2712_PIN_11_PWM7__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define MT2712_PIN_11_PWM7__FUNC_PWM7 (MTK_PIN_NO(11) | 1) +#define MT2712_PIN_11_PWM7__FUNC_DISP1_PWM (MTK_PIN_NO(11) | 2) +#define MT2712_PIN_11_PWM7__FUNC_DISP0_PWM (MTK_PIN_NO(11) | 3) +#define MT2712_PIN_11_PWM7__FUNC_LCM_RST1 (MTK_PIN_NO(11) | 4) + +#define MT2712_PIN_12_IDDIG_P0__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define MT2712_PIN_12_IDDIG_P0__FUNC_IDDIG_A (MTK_PIN_NO(12) | 1) +#define
[PATCH v3 3/4] pinctrl: add mt2712 pinctrl driver
The commit includes mt2712 pinctrl driver.
Signed-off-by: Zhiyong Tao
---
drivers/pinctrl/mediatek/Kconfig |7 +
drivers/pinctrl/mediatek/Makefile |1 +
drivers/pinctrl/mediatek/pinctrl-mt2712.c | 632
drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h | 1967 +
4 files changed, 2607 insertions(+)
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt2712.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 3e59874..862c5db 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -32,6 +32,13 @@ config PINCTRL_MT8127
select PINCTRL_MTK
# For ARMv8 SoCs
+config PINCTRL_MT2712
+ bool "MediaTek MT2712 pin control"
+ depends on OF
+ depends on ARM64 || COMPILE_TEST
+ default ARM64 && ARCH_MEDIATEK
+ select PINCTRL_MTK
+
config PINCTRL_MT7622
bool "MediaTek MT7622 pin control"
depends on OF
diff --git a/drivers/pinctrl/mediatek/Makefile
b/drivers/pinctrl/mediatek/Makefile
index ed7d2b2..7959e77 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
# SoC Drivers
obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o
+obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o
obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2712.c
b/drivers/pinctrl/mediatek/pinctrl-mt2712.c
new file mode 100644
index 000..5595e90
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt2712.c
@@ -0,0 +1,632 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Zhiyong Tao
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pinctrl-mtk-common.h"
+#include "pinctrl-mtk-mt2712.h"
+
+static const struct mtk_pin_spec_pupd_set_samereg mt2712_spec_pupd[] = {
+ MTK_PIN_PUPD_SPEC_SR(18, 0xe50, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(19, 0xe60, 12, 11, 10),
+ MTK_PIN_PUPD_SPEC_SR(20, 0xe50, 5, 4, 3),
+ MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 15, 14, 13),
+ MTK_PIN_PUPD_SPEC_SR(22, 0xe50, 8, 7, 6),
+ MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 2, 1, 0),
+
+ MTK_PIN_PUPD_SPEC_SR(30, 0xf30, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(31, 0xf30, 6, 5, 4),
+ MTK_PIN_PUPD_SPEC_SR(32, 0xf30, 10, 9, 8),
+ MTK_PIN_PUPD_SPEC_SR(33, 0xf30, 14, 13, 12),
+ MTK_PIN_PUPD_SPEC_SR(34, 0xf40, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(35, 0xf40, 6, 5, 4),
+ MTK_PIN_PUPD_SPEC_SR(36, 0xf40, 10, 9, 8),
+ MTK_PIN_PUPD_SPEC_SR(37, 0xc40, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(38, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(39, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(40, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(41, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(42, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(43, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(44, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(45, 0xc60, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(46, 0xc50, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(47, 0xda0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(48, 0xd90, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(49, 0xdf0, 14, 13, 12),
+ MTK_PIN_PUPD_SPEC_SR(50, 0xdf0, 10, 9, 8),
+ MTK_PIN_PUPD_SPEC_SR(51, 0xdf0, 6, 5, 4),
+ MTK_PIN_PUPD_SPEC_SR(52, 0xdf0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(53, 0xd50, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(54, 0xd80, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(55, 0xe00, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(56, 0xd40, 2, 1, 0),
+
+ MTK_PIN_PUPD_SPEC_SR(63, 0xc80, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(64, 0xdb0, 14, 13, 12),
+ MTK_PIN_PUPD_SPEC_SR(65, 0xdb0, 6, 5, 4),
+ MTK_PIN_PUPD_SPEC_SR(66, 0xdb0, 10, 9, 8),
+ MTK_PIN_PUPD_SPEC_SR(67, 0xcd0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(68, 0xdb0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(69, 0xc90, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(70, 0xcc0, 2, 1, 0),
+
+ MTK_PIN_PUPD_SPEC_SR(89, 0xce0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(90, 0xdd0, 14, 13, 12),
+ MTK_PIN_PUPD_SPEC_SR(91, 0xdd0, 10, 9, 8),
+ MTK_PIN_PUPD_SPEC_SR(92, 0xdd0, 6, 5, 4),
+ MTK_PIN_PUPD_SPEC_SR(93, 0xdd0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(94, 0xd20, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(95, 0xcf0, 2, 1, 0),
+ MTK_PIN_PUPD_SPEC_SR(96, 0xd30, 2, 1, 0),
+
+ MTK_PIN_PUPD_SPEC_SR(135, 0xe50, 11, 10, 9),
+ MTK_PIN_PUPD_SPEC_SR(136, 0xe50, 14, 13, 12),
+ MTK_PIN_PUPD_SPEC_SR(137, 0xe70, 5, 4, 3),
+ MTK_PIN_PUPD_SPEC_SR(138, 0xe70, 8, 7, 6),
+ MTK_PIN_PUPD_SPEC_SR(139, 0xe70, 11, 10, 9),
+ MTK_PIN_PUPD_SPEC_SR(140,
[PATCH v3 2/4] arm64: dts: mt2712: add pintcrl device node.
This patch adds pintcrl device node for mt2712.
Signed-off-by: Zhiyong Tao
---
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index d7688bc..fb3b051 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -9,6 +9,7 @@
#include
#include
#include
+#include "mt2712-pinfunc.h"
/ {
compatible = "mediatek,mt2712";
@@ -258,6 +259,23 @@
#clock-cells = <1>;
};
+ syscfg_pctl_a: syscfg_pctl_a@10005000 {
+ compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon";
+ reg = <0 0x10005000 0 0x1000>;
+ };
+
+ pio: pinctrl@10005000 {
+ compatible = "mediatek,mt2712-pinctrl";
+ reg = <0 0x1000b000 0 0x1000>;
+ mediatek,pctl-regmap = <_pctl_a>;
+ pins-are-numbered;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = ;
+ };
+
scpsys: scpsys@10006000 {
compatible = "mediatek,mt2712-scpsys", "syscon";
#power-domain-cells = <1>;
--
1.9.1
[PATCH v3 4/4] pintcrl: support bias-disable of generic and special pins simultaneously
For generic pins, parameter "arg" is 0 or 1.
For special pins, bias-disable is set by R0R1,
so we need transmited "00" to set bias-disable
When we set "bias-disable" as high-z property,
the parameter should be "MTK_PUPD_SET_R1R0_00".
Signed-off-by: Zhiyong Tao
---
drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index 3cf384f..f991ff3 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -293,7 +293,7 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl
*pctl,
unsigned int pin, bool enable, bool isup, unsigned int arg)
{
unsigned int bit;
- unsigned int reg_pullen, reg_pullsel;
+ unsigned int reg_pullen, reg_pullsel, r1r0;
int ret;
/* Some pins' pull setting are very different,
@@ -301,8 +301,12 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl
*pctl,
* resistor bit, so we need this special handle.
*/
if (pctl->devdata->spec_pull_set) {
+ /* For special pins, bias-disable is set by R1R0,
+* the parameter should be "MTK_PUPD_SET_R1R0_00".
+*/
+ r1r0 = enable ? arg : MTK_PUPD_SET_R1R0_00;
ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
- pin, pctl->devdata->port_align, isup, arg);
+ pin, pctl->devdata->port_align, isup, r1r0);
if (!ret)
return 0;
}
--
1.9.1
Re: [PATCH v2 3/4] pinctrl: add mt2712 pinctrl driver
On Wed, 2018-02-28 at 15:14 +0800, Sean Wang wrote: > Hi, Zhiyong > > all seems better than v1, but some nitpicking is addressed as below > > Sean > > On Mon, 2018-02-26 at 16:34 +0800, Zhiyong Tao wrote: > > The commit includes mt2712 pinctrl driver. > > > > Signed-off-by: Zhiyong Tao > > --- > > drivers/pinctrl/mediatek/Kconfig |7 + > > drivers/pinctrl/mediatek/Makefile |1 + > > drivers/pinctrl/mediatek/pinctrl-mt2712.c | 639 > > drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h | 1973 > > + > > 4 files changed, 2620 insertions(+) > > create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt2712.c > > create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h > > > > diff --git a/drivers/pinctrl/mediatek/Kconfig > > b/drivers/pinctrl/mediatek/Kconfig > > index 3e59874..b24bc76 100644 > > --- a/drivers/pinctrl/mediatek/Kconfig > > +++ b/drivers/pinctrl/mediatek/Kconfig > > @@ -32,6 +32,13 @@ config PINCTRL_MT8127 > > select PINCTRL_MTK > > > > # For ARMv8 SoCs > > +config PINCTRL_MT2712 > > + bool "Mediatek MT2712 pin control" > > > should be MediaTek for normal ==> Thanks for your suggestion. We will correct it in v3. > > > + depends on OF > > + depends on ARM64 || COMPILE_TEST > > + default ARM64 && ARCH_MEDIATEK > > + select PINCTRL_MTK > > + > > config PINCTRL_MT7622 > > bool "MediaTek MT7622 pin control" > > depends on OF > > diff --git a/drivers/pinctrl/mediatek/Makefile > > b/drivers/pinctrl/mediatek/Makefile > > index ed7d2b2..7959e77 100644 > > --- a/drivers/pinctrl/mediatek/Makefile > > +++ b/drivers/pinctrl/mediatek/Makefile > > @@ -4,6 +4,7 @@ obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o > > > > # SoC Drivers > > obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o > > +obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o > > obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o > > obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o > > obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o > > diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2712.c > > b/drivers/pinctrl/mediatek/pinctrl-mt2712.c > > new file mode 100644 > > index 000..b6ae71b > > --- /dev/null > > +++ b/drivers/pinctrl/mediatek/pinctrl-mt2712.c > > @@ -0,0 +1,639 @@ > > +/* > > + * Copyright (c) 2014-2015 MediaTek Inc. > > + * Author: Hongzhou.Yang > > + * > > + * This program is free software; you can redistribute it and/or modify > > + * it under the terms of the GNU General Public License version 2 as > > + * published by the Free Software Foundation. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + */ > > + > > suggest to consider more on using SPDX identifiers and > using right data for both fields Copyright and Author ==> Thanks for your suggestion. We will correct it in v3. > > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#include "pinctrl-mtk-common.h" > > +#include "pinctrl-mtk-mt2712.h" > > + > > <...> > > > diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h > > b/drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h > > new file mode 100644 > > index 000..71f4190 > > --- /dev/null > > +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h > > @@ -0,0 +1,1973 @@ > > +/* > > + * Copyright (C) 2015 MediaTek Inc. > > + * > > + * This program is free software: you can redistribute it and/or modify > > + * it under the terms of the GNU General Public License version 2 as > > + * published by the Free Software Foundation. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + */ > > Ditto > > > +#ifndef PINCTRL_MTK_MT2712_H > > +#define PINCTRL_MTK_MT2712_H > > + > > <...> > > > + > > +#endif /* __PINCTRL_MTK_MT2712_H */ > >
Re: [PATCH v2 1/4] arm64: dts: mt2712: add pintcrl file
On Wed, 2018-02-28 at 14:42 +0800, Sean Wang wrote: > On Mon, 2018-02-26 at 16:33 +0800, Zhiyong Tao wrote: > > This patch adds pinctrl file for mt2712. > > > > Signed-off-by: Zhiyong Tao > > --- > > arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h | 1129 > > + > > 1 file changed, 1129 insertions(+) > > create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h > > b/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h > > new file mode 100644 > > index 000..44f8ca2 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h > > @@ -0,0 +1,1129 @@ > > +/* > > + * Copyright (C) 2015 MediaTek Inc. > > + * > > + * This program is free software: you can redistribute it and/or modify > > + * it under the terms of the GNU General Public License version 2 as > > + * published by the Free Software Foundation. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + */ > > suggest to consider more on using SPDX identifiers ==> Thanks for your suggestion. We will use SPDX identifiers in V3. > > > +#ifndef __DTS_MT2712_PINFUNC_H > > +#define __DTS_MT2712_PINFUNC_H > > + > > +#include > > + > > +#define MT2712_PIN_0_EINT0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) > > +#define MT2712_PIN_0_EINT0__FUNC_EINT0 (MTK_PIN_NO(0) | 1) > > +#define MT2712_PIN_0_EINT0__FUNC_MBIST_DIAG_SCANOUT (MTK_PIN_NO(0) | 2) > > +#define MT2712_PIN_0_EINT0__FUNC_DSIA_TE (MTK_PIN_NO(0) | 3) > > +#define MT2712_PIN_0_EINT0__FUNC_DSIC_TE (MTK_PIN_NO(0) | 4) > > +#define MT2712_PIN_0_EINT0__FUNC_DIN_D3 (MTK_PIN_NO(0) | 5) > > +#define MT2712_PIN_0_EINT0__FUNC_PURE_HW_PROTECT (MTK_PIN_NO(0) | 6) > > + > > +#define MT2712_PIN_1_EINT1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) > > +#define MT2712_PIN_1_EINT1__FUNC_EINT1 (MTK_PIN_NO(1) | 1) > > +#define MT2712_PIN_1_EINT1__FUNC_IR_IN (MTK_PIN_NO(1) | 2) > > +#define MT2712_PIN_1_EINT1__FUNC_DSIB_TE (MTK_PIN_NO(1) | 3) > > +#define MT2712_PIN_1_EINT1__FUNC_DSID_TE (MTK_PIN_NO(1) | 4) > > +#define MT2712_PIN_1_EINT1__FUNC_DIN_D4 (MTK_PIN_NO(1) | 5) > > + > > +#define MT2712_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) > > +#define MT2712_PIN_2_EINT2__FUNC_EINT2 (MTK_PIN_NO(2) | 1) > > +#define MT2712_PIN_2_EINT2__FUNC_IR_IN (MTK_PIN_NO(2) | 2) > > +#define MT2712_PIN_2_EINT2__FUNC_LCM_RST1 (MTK_PIN_NO(2) | 3) > > +#define MT2712_PIN_2_EINT2__FUNC_DIN_D5 (MTK_PIN_NO(2) | 5) > > + > > +#define MT2712_PIN_3_EINT3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) > > +#define MT2712_PIN_3_EINT3__FUNC_EINT3 (MTK_PIN_NO(3) | 1) > > +#define MT2712_PIN_3_EINT3__FUNC_IR_IN (MTK_PIN_NO(3) | 2) > > +#define MT2712_PIN_3_EINT3__FUNC_LCM_RST0 (MTK_PIN_NO(3) | 3) > > +#define MT2712_PIN_3_EINT3__FUNC_DIN_D6 (MTK_PIN_NO(3) | 5) > > + > > +#define MT2712_PIN_4_PWM0__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) > > +#define MT2712_PIN_4_PWM0__FUNC_PWM0 (MTK_PIN_NO(4) | 1) > > +#define MT2712_PIN_4_PWM0__FUNC_DISP0_PWM (MTK_PIN_NO(4) | 2) > > +#define MT2712_PIN_4_PWM0__FUNC_DISP1_PWM (MTK_PIN_NO(4) | 3) > > +#define MT2712_PIN_4_PWM0__FUNC_DIN_CLK (MTK_PIN_NO(4) | 5) > > + > > +#define MT2712_PIN_5_PWM1__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) > > +#define MT2712_PIN_5_PWM1__FUNC_PWM1 (MTK_PIN_NO(5) | 1) > > +#define MT2712_PIN_5_PWM1__FUNC_DISP1_PWM (MTK_PIN_NO(5) | 2) > > +#define MT2712_PIN_5_PWM1__FUNC_DISP0_PWM (MTK_PIN_NO(5) | 3) > > +#define MT2712_PIN_5_PWM1__FUNC_DIN_VSYNC (MTK_PIN_NO(5) | 5) > > + > > +#define MT2712_PIN_6_PWM2__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) > > +#define MT2712_PIN_6_PWM2__FUNC_PWM2 (MTK_PIN_NO(6) | 1) > > +#define MT2712_PIN_6_PWM2__FUNC_DISP0_PWM (MTK_PIN_NO(6) | 2) > > +#define MT2712_PIN_6_PWM2__FUNC_DISP1_PWM (MTK_PIN_NO(6) | 3) > > +#define MT2712_PIN_6_PWM2__FUNC_DISP2_PWM (MTK_PIN_NO(6) | 4) > > +#define MT2712_PIN_6_PWM2__FUNC_DIN_HSYNC (MTK_PIN_NO(6) | 5) > > + > > +#define MT2712_PIN_7_PWM3__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) > > +#define MT2712_PIN_7_PWM3__FUNC_PWM3 (MTK_PIN_NO(7) | 1) > > +#define MT2712_PIN_7_PWM3__FUNC_DISP1_PWM (MTK_PIN_NO(7) | 2) > > +#define MT2712_PIN_7_PWM3__FUNC_DISP0_PWM (MTK_PIN_NO(7) | 3) > > +#define MT2712_PIN_7_PWM3__FUNC_LCM_RST2 (MTK_PIN_NO(7) | 4) > > +#define MT2712_PIN_7_PWM3__FUNC_DIN_D0 (MTK_PIN_NO(7) | 5) > > + > > +#define MT2712_PIN_8_PW
