Hi,
On 2021/4/20 上午10:48, Huang Pei wrote:
Hi,
On Mon, Apr 19, 2021 at 10:21:40PM +0800, Zhou Yanjie wrote:
Hi
On 2021/4/19 下午12:56, Huang Pei wrote:
On Sat, Apr 17, 2021 at 12:45:59AM +0800, Zhou Yanjie wrote:
On 2021/4/16 下午5:20, 黄沛 wrote:
Is there any log about the panic?
Yes, below is
On 2021/4/20 上午10:48, Huang Pei wrote:
Hi,
On Mon, Apr 19, 2021 at 10:21:40PM +0800, Zhou Yanjie wrote:
Hi
On 2021/4/19 下午12:56, Huang Pei wrote:
On Sat, Apr 17, 2021 at 12:45:59AM +0800, Zhou Yanjie wrote:
On 2021/4/16 下午5:20, 黄沛 wrote:
Is there any log about the panic?
Yes, below is
information given by checkpatch.pl?
On 2019年01月26日 01:59, Paul Cercueil wrote:
Hi,
On Fri, Jan 25, 2019 at 6:59 AM, Zhou Yanjie wrote:
Warning is reported when checkpatch indicates that
"static const char * array" should be changed to
"static const char * const".
Signed-off-by:
Add Ingenic X1000 irqchip support.
The interrupt handling method is changed from old-style cascade to
chained_irq which is more appropriate. Also, it can process the
corner situation that more than one irq is coming to a single
chip at the same time.
Signed-off-by: Zhou Yanjie
---
drivers/irqchip/irq-ingenic.c | 49
Add support for probing the irq-ingenic driver on the X1000 Soc.
X1000 is a 1.0GHz processor for IoT. It has MIPS32 XBurst RISC core
with double precision hardware float point unit.
Signed-off-by: Zhou Yanjie
---
drivers/irqchip/irq-ingenic.c | 1 +
1 file changed, 1 insertion(+)
diff --git a
For the sake of uniform style, function "intc_irq_set_mask" is
changed to "ingenic_intc_intc_irq_set_mask".
Signed-off-by: Zhou Yanjie
---
drivers/irqchip/irq-ingenic.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-ingenic.c b
Add support for probing the irq-ingenic driver on the X1000 Soc.
X1000 is a 1.0GHz processor for IoT. It has MIPS32 XBurst RISC core
with double precision hardware float point unit.
Signed-off-by: Zhou Yanjie
---
Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt | 1 +
1
My fault, in the function "generic_handle_irq" should use "bit" instead
of "__fls(irq_reg)".
It will be fixed in the v2.
On 2019年01月27日 18:21, Marc Zyngier wrote:
On Sat, 26 Jan 2019 15:38:40 +,
Zhou Yanjie wrote:
The interrupt handling method is cha
Thanks for your suggestions, It will be deleted in the v2.
On 2019年01月27日 18:14, Marc Zyngier wrote:
On Sat, 26 Jan 2019 15:38:42 +,
Zhou Yanjie wrote:
Add support for probing the irq-ingenic driver on the X1000 Soc.
X1000 is a 1.0GHz processor for IoT. It has MIPS32 XBurst RISC core
with
vi->v2: Replace "__fls(pending)" with "bit" in function "generic_handle_irq".
The interrupt handling method is changed from old-style cascade to
chained_irq which is more appropriate. Also, it can process the
corner situation that more than one irq is coming to a single
chip at the same time.
Signed-off-by: Zhou Yanjie
---
drivers/irqchip/irq-ingenic.c | 48
For the sake of uniform style, function "intc_irq_set_mask" is
changed to "ingenic_intc_intc_irq_set_mask".
Signed-off-by: Zhou Yanjie
---
drivers/irqchip/irq-ingenic.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-ingenic.c b
Add support for probing the irq-ingenic driver on the X1000 Soc.
Signed-off-by: Zhou Yanjie
---
drivers/irqchip/irq-ingenic.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index 32d090a..814c68c 100644
--- a/drivers/irqchip/irq
Add support for probing the irq-ingenic driver on the X1000 Soc.
Signed-off-by: Zhou Yanjie
---
Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
b
Add Ingenic X1000 serial support.
Add support for probing the 8250_ingenic driver on the
X1000 Soc from Ingenic.
Signed-off-by: Zhou Yanjie
---
Documentation/devicetree/bindings/serial/ingenic,uart.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/serial/ingenic,uart.txt
Add support for probing the 8250_ingenic driver on the
X1000 Soc from Ingenic.
Signed-off-by: Zhou Yanjie
---
drivers/tty/serial/8250/8250_ingenic.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/tty/serial/8250/8250_ingenic.c
b/drivers/tty/serial/8250/8250_ingenic.c
My fault, I will fix these in v2.
On 2019年01月28日 17:30, Greg KH wrote:
On Mon, Jan 28, 2019 at 05:19:35PM +0800, Zhou Yanjie wrote:
Add support for probing the 8250_ingenic driver on the
X1000 Soc from Ingenic.
Signed-off-by: Zhou Yanjie
---
drivers/tty/serial/8250/8250_ingenic.c | 10
v1->v2: Remove unnecessary "EARLYCON_DECLARE".
Add support for probing the 8250_ingenic driver on the
X1000 Soc from Ingenic.
Signed-off-by: Zhou Yanjie
---
drivers/tty/serial/8250/8250_ingenic.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/tty/serial/8250/8250_ingenic.c
b/drivers/tty/serial
Add support for probing the 8250_ingenic driver on the
X1000 Soc from Ingenic.
Signed-off-by: Zhou Yanjie
---
Documentation/devicetree/bindings/serial/ingenic,uart.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/serial/ingenic,uart.txt
Thank you for your reply. I am working on v2, and I have removed the
fourth patch in v2,
so there will be no warnings at compile time. But this will cause some
warning messages
when checkpatch, I am confused whether I can ignore these warnings.
On 2019年01月28日 21:59, Linus Walleij wrote:
This s
Fix compile-time warnings.
From: Zhou Yanjie
Delete uart4 and i2c3/4 from JZ4770:
According to the datasheet, only JZ4780 have uart4 and i2c3/4. So we
remove it from the JZ4770 code and add a section corresponding the JZ4780.
Fix bugs in i2c0/1:
The pin number was wrong in the original code.
Fix bugs in uart2:
JZ4770
From: Zhou Yanjie
Add mmc2 for JZ4770 and JZ4780:
According to the datasheet, both JZ4770 and JZ4780 have mmc2. But this
part of the original code is missing. It is worth noting that JZ4770's
mmc2 supports 8bit mode while JZ4780's does not, so we added the
corresponding code for b
From: Zhou Yanjie
In the original code, some function names begin with "ingenic_gpio_",
and some with "gpio_ingenic_". For the sake of uniform style,
all of them are changed to the beginning of "ingenic_gpio_".
Signed-off-by: Zhou Yanjie
---
drivers/
I am very sorry, I understood wrong before.
On 2019年01月29日 00:22, Greg KH wrote:
On Mon, Jan 28, 2019 at 09:57:00PM +0800, Zhou Yanjie wrote:
Add support for probing the 8250_ingenic driver on the
X1000 Soc from Ingenic.
Signed-off-by: Zhou Yanjie
---
drivers/tty/serial/8250/8250_ingenic.c
v1->v2: Remove unnecessary "EARLYCON_DECLARE".
v2->v3: Use different subject line for each patch.
Add support for probing the 8250_ingenic driver on the
X1000 Soc from Ingenic.
Signed-off-by: Zhou Yanjie
---
drivers/tty/serial/8250/8250_ingenic.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/tty/serial/8250/8250_ingenic.c
b/drivers/tty/serial
Add the serial bindings for the X1000 Soc from Ingenic.
Signed-off-by: Zhou Yanjie
---
Documentation/devicetree/bindings/serial/ingenic,uart.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/serial/ingenic,uart.txt
b/Documentation
Add Ingenic X1000 RTC support.
Add support for probing the rtc-jz4740 driver on the
X1000 Soc from Ingenic.
Signed-off-by: Zhou Yanjie
---
drivers/rtc/rtc-jz4740.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/rtc/rtc-jz4740.c b/drivers/rtc/rtc-jz4740.c
index d0a8917..0c7ae65 100644
--- a
Add the RTC bindings for the X1000 Soc from Ingenic.
Signed-off-by: Zhou Yanjie
---
Documentation/devicetree/bindings/rtc/ingenic,jz4740-rtc.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/rtc/ingenic,jz4740-rtc.txt
b/Documentation/devicetree/bindings
Ingenic had changed their product code name.
Latest SoCs had divided to several series such as
T30/M200/X1000 and no longer called JZ47xx.
Signed-off-by: Zhou Yanjie
---
drivers/rtc/Kconfig | 4 ++--
drivers/rtc/rtc-jz4740.c | 15 +++
2 files changed, 5 insertions(+), 14
1.Add the USB PHY bindings for the X1000 SoC and
the X1830 SoC from Ingenic.
2.Add support for probing the phy-jz4770 driver on the
X1000 SoC and the X1830 SoC from Ingenic.
周琰杰 (Zhou Yanjie) (2):
dt-bindings: USB: Add Ingenic X1000 and X1830 bindings.
USB: PHY: JZ4770: Add support for
Add the USB PHY bindings for the X1000 SoC and
the X1830 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Documentation/devicetree/bindings/usb/ingenic,jz4770-phy.yaml | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/usb/ingenic
Add support for probing the phy-jz4770 driver on the
X1000 SoC and the X1830 SoC from Ingenic.
Signed-off-by: qipengzhen
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
drivers/usb/phy/Kconfig | 4 +-
drivers/usb/phy/phy-jz4770.c | 250 +--
2 files changed
Add 'cpus' node to the jz4740.dtsi, jz4770.dtsi, jz4780.dtsi
and x1000.dtsi files.
Tested-by: H. Nikolaus Schaller
Tested-by: Paul Boddie
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v1->v2:
No change.
v2->v3:
No change.
v3->v4:
Rebase on to
Modify DTS, change tcu channel from 2 to 3, channel #0 and #1 for
per core local timer, #2 for clocksource.
Tested-by: H. Nikolaus Schaller
Tested-by: Paul Boddie
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v1->v2:
No change.
v2->v3:
No change.
v3->v4:
Add "CONFIG_SMP=y" and "CONFIG_NR_CPUS=2" to support SMP.
Tested-by: H. Nikolaus Schaller
Tested-by: Paul Boddie
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v1->v2:
No change.
v2->v3:
No change.
v3->v4:
Rebase on top of kernel 5.6
Enable clock event handling on per CPU core basis.
Make sure that interrupts raised on the first core execute
event handlers on the correct CPU core.
Tested-by: H. Nikolaus Schaller
Tested-by: Paul Boddie
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v1->v2:
1.Adjust function naming
Introduce SMP support for MIPS Creator CI20, which is
based on Ingenic JZ4780 SoC.
Introduce SMP support for MIPS Creator CI20, which is
based on Ingenic JZ4780 SoC.
周琰杰 (Zhou Yanjie) (6):
MIPS: JZ4780: Introduce SMP support.
MIPS: CI20: Modify DTS to support high resolution timer for SMP.
clocksource: Ingenic: Add high resolution timer support for SMP.
dt-bindings
Document the available properties for the SoC root node and the
CPU nodes of the devicetree for the Ingenic XBurst SoCs.
Tested-by: H. Nikolaus Schaller
Tested-by: Paul Boddie
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v1->v2:
Change the two Document from txt to yaml.
v2-
Forward port smp support from kernel 3.18.3 of CI20_linux
to upstream kernel 5.6.
Tested-by: H. Nikolaus Schaller
Tested-by: Paul Boddie
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Jiaxun Yang
---
Notes:
v1->v2:
1.Remove unnecessary "plat_irq_dispatch(void)" in irq-ing
Hi Paul,
On 2020年05月20日 03:41, Paul Cercueil wrote:
Hi Zhou,
Le mar. 19 mai 2020 à 22:35, 周琰杰 (Zhou Yanjie)
a écrit :
Forward port smp support from kernel 3.18.3 of CI20_linux
to upstream kernel 5.6.
Tested-by: H. Nikolaus Schaller
Tested-by: Paul Boddie
Signed-off-by: 周琰杰 (Zhou Yanjie
On 2020年05月20日 00:09, Paul Cercueil wrote:
Hi Zhou,
Le mar. 19 mai 2020 à 22:35, 周琰杰 (Zhou Yanjie)
a écrit :
Forward port smp support from kernel 3.18.3 of CI20_linux
to upstream kernel 5.6.
Tested-by: H. Nikolaus Schaller
Tested-by: Paul Boddie
Signed-off-by: 周琰杰 (Zhou Yanjie
在 2020/8/3 下午5:01, Jiaxun Yang 写道:
在 2020/8/3 上午5:46, Maciej W. Rozycki 写道:
On Fri, 31 Jul 2020, Serge Semin wrote:
Requested by downstream distros, a Kconfig option for default
IEEE754 conformance mode allows them to set their mode to
relaxed by default.
That's what should have been here
Hi Paul,
在 2020/7/28 下午11:40, Paul Cercueil 写道:
Hi Zhou,
Le sam. 25 juil. 2020 à 16:02, Zhou Yanjie
a écrit :
Hi Paul,
在 2020/7/23 下午4:47, Paul Cercueil 写道:
Hi Zhou,
Le jeu. 23 juil. 2020 à 15:19, 周琰杰 (Zhou Yanjie)
a écrit :
The commit 19c968222934 ("MIPS: DTS: CI20: make D
Hello Jiaxun,
Reviewed-by: 周琰杰 (Zhou Yanjie)
在 2020/8/1 下午2:11, Jiaxun Yang 写道:
Requested by downstream distros, a Kconfig option for default
IEEE 754 conformance mode allows them to set their mode to
relaxed by default.
Signed-off-by: Jiaxun Yang
Reviewed-by: WANG Xuerui
Reviewed-by
Hi Paul,
I'm not too sure if remove "cpu-feature-overrides.h" will cause some
problems for X2000, because according to my current test on X2000, I
found that it is somewhat different from the SoCs using XBurst1 CPU
core, with the kernel source code provided by Ingenic, for example, we
must co
Hi Paul,
在 2020/8/8 上午12:45, Paul Cercueil 写道:
Hi Zhou,
Le sam. 8 août 2020 à 0:23, Zhou Yanjie a
écrit :
Hi Paul,
I'm not too sure if remove "cpu-feature-overrides.h" will cause some
problems for X2000, because according to my current test on X2000, I
found that it is som
Hi Paul,
在 2020/8/4 上午1:01, Paul Cercueil 写道:
Support for Ingenic chips has been moved to the generic MIPS platform.
Update the paths accordingly.
The modification to "cu1830-neo_defconfig" seems to be missed here.
Thanks and best regards!
Signed-off-by: Paul Cercueil
---
MAINTAINERS |
在 2020/8/8 上午1:22, Zhou Yanjie 写道:
Hi Paul,
在 2020/8/4 上午1:01, Paul Cercueil 写道:
Support for Ingenic chips has been moved to the generic MIPS platform.
Update the paths accordingly.
The modification to "cu1830-neo_defconfig" seems to be missed here.
Sorry, this should be a re
Hi Paul,
I have some good news and some bad news.
Good news is:
I tested this series of patches on CU1000-Neo & CU1830-Neo, and it can
boot normally and log in to debian normally.
Bad news is:
1. Because we dropped arch/mips/jz4740/setup.c, so it did not return
MACH_INGENIC_ correctly
在 2020/8/12 上午8:15, Paul Cercueil 写道:
For each board the MACH_INGENIC_SOC option was selected instead of
MACH_INGENIC. Nothing else was changed in the menuconfig.
Signed-off-by: Paul Cercueil
---
Notes:
v2: Update cu1830-neo board config as well.
arch/mips/configs/ci20_defconfig
Add "jz4780_core1_disable()" for disable the second core of JZ4780,
prepare for later commits.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Paul Cercueil
---
Notes:
v1->v2:
Add Paul Cercueil's Reviewed-by.
v2->v3:
No change.
v3->v4:
Add MACPHY, CIM, AIC, DMIC, I2S clocks bindings for the X1000 SoC
and the X1830 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Paul Cercueil
Acked-by: Rob Herring
---
Notes:
v1->v2:
1.Add MACPHY and I2S for X1000, and add MACPHY for X1830.
2.Add Paul Cercuei
X1000 and X1830 have two MAC related clocks, one is MACPHY, which is
controlled by MACCDR register, the other is MAC, which is controlled
by the MAC bit in the CLKGR register (with CLK_AHB2 as the parent).
The original driver mistakenly mixed the two clocks together.
Signed-off-by: 周琰杰 (Zhou
.c files.
2.Reformat code, add missing blank lines, remove unnecessary
commas and tabs, and align code.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v1->v2:
Remove unnecessary -1 and commas.
v2->v3:
No change.
v3->v4:
1.The -1 used for placehold
Add CIM, AIC, DMIC, I2S clocks for the X1000 SoC and the
X1830 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v1->v2:
Add I2S clock for X1000.
v2->v3:
Correct the comment in x1000-cgu.c, change it from
"Custom (SoC-specific) OTG PHY"
should not be removed.
2.Move "JZ4780_CLK_CORE1" from the "Gate-only clocks"
class to the "Custom (SoC-specific)" class, because
it belongs to the custom clock.
周琰杰 (Zhou Yanjie) (5):
clk: JZ4780: Add function for disable the second core.
dt-bindings: cloc
Hi Paul,
On 2020/12/23 下午8:29, Paul Cercueil wrote:
Hi Zhou,
Le lun. 21 déc. 2020 à 23:52, 周琰杰 (Zhou Yanjie)
a écrit :
Add CIM, AIC, DMIC, I2S clocks for the X1000 SoC and the
X1830 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v1->v2:
Add I2S clock for X1
Hi Paul,
On 2020/12/23 下午8:39, Paul Cercueil wrote:
Hi Zhou,
Le lun. 21 déc. 2020 à 23:52, 周琰杰 (Zhou Yanjie)
a écrit :
1.When the clock does not have "CGU_CLK_MUX", the 2/3/4 bits in
parents do not need to be filled with -1. When the clock have
a "CGU_CLK_MUX" has o
: 周琰杰 (Zhou Yanjie)
Thanks and best regards!
diff --git a/drivers/phy/ingenic/phy-ingenic-usb.c
b/drivers/phy/ingenic/phy-ingenic-usb.c
index 4d1587d82286..ea127b177f46 100644
--- a/drivers/phy/ingenic/phy-ingenic-usb.c
+++ b/drivers/phy/ingenic/phy-ingenic-usb.c
@@ -82,18 +82,7 @@
#define
("PHY: Ingenic: Add USB PHY driver using generic PHY
framework.")
Signed-off-by: Alexander Lobakin
---
drivers/phy/ingenic/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Apologize for my carelessness, and
Tested-by: 周琰杰 (Zhou Yanjie)
Thanks and best regards!
On 2021/3/23 上午2:01, Paul Cercueil wrote:
Le mer. 17 mars 2021 à 17:57, 周琰杰 (Zhou Yanjie)
a écrit :
Add the pinctrl bindings for the JZ4730 SoC, the JZ4750 SoC,
the JZ4755 SoC, the JZ4775 SoC and the X2000 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v2:
New
On 2021/3/23 上午2:17, Paul Cercueil wrote:
Le mer. 17 mars 2021 à 17:58, 周琰杰 (Zhou Yanjie)
a écrit :
Add support for probing the pinctrl-ingenic driver on the
JZ4730 SoC from Ingenic.
This driver is derived from Paul Boddie. It is worth to
noting that the JZ4730 SoC is special in having
On 2021/3/23 上午2:20, Paul Cercueil wrote:
Le mer. 17 mars 2021 à 17:58, 周琰杰 (Zhou Yanjie)
a écrit :
Add support for probing the pinctrl-ingenic driver on the
JZ4750 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v3:
New patch.
drivers/pinctrl/pinctrl-ingenic.c
Hi Paul,
On 2021/3/23 上午1:53, Paul Cercueil wrote:
Hi Zhou,
Le mer. 17 mars 2021 à 17:57, 周琰杰 (Zhou Yanjie)
a écrit :
The MII group of JZ4770's MAC should have 7 pins, add missing
pins to the MII group.
Fixes: 5de1a73e78ed ("Pinctrl: Ingenic: Add missing parts for JZ4770
Hi,
On 2021/3/23 上午1:58, Paul Cercueil wrote:
Le mer. 17 mars 2021 à 17:57, 周琰杰 (Zhou Yanjie)
a écrit :
Add X1830 support in "ingenic_pinconf_get()", so that it can read the
configuration of X1830 SoC correctly.
Fixes: d7da2a1e4e08 ("pinctrl: Ingenic: Add pinctrl d
Hi,
On 2021/3/23 上午2:24, Paul Cercueil wrote:
Le mer. 17 mars 2021 à 17:58, 周琰杰 (Zhou Yanjie)
a écrit :
Add support for probing the pinctrl-ingenic driver on the
JZ4755 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v3:
New patch.
drivers/pinctrl/pinctrl
On 2021/3/23 上午2:25, Paul Cercueil wrote:
Le mer. 17 mars 2021 à 17:58, 周琰杰 (Zhou Yanjie)
a écrit :
Add support for probing the pinctrl-ingenic driver on the
JZ4775 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v3:
New patch.
drivers/pinctrl/pinctrl-ingenic.c
For SoCs after X1000, only send "X1000_I2C_DC_STOP" when last byte,
or it will cause error when I2C write operation.
周琰杰 (Zhou Yanjie) (1):
I2C: JZ4780: Fix bug for Ingenic X1000.
drivers/i2c/busses/i2c-jz4780.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
--
2.7.4
Only send "X1000_I2C_DC_STOP" when last byte, or it will cause
error when I2C write operation.
Fixes: 21575a7a8d4c ("I2C: JZ4780: Add support for the X1000.")
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
drivers/i2c/busses/i2c-jz4780.c | 7 +++
1 file changed, 3 insertions(+),
Hi Wolfram,
Sorry, please forgive my carefulness, I wrongly sent the version that
did not clean up, resulting in missing the reporter's information and
some errors in formats.
On 2021/3/19 上午1:06, Wolfram Sang wrote:
On Fri, Mar 19, 2021 at 12:25:43AM +0800, 周琰杰 (Zhou Yanjie) wrote:
Only send "X1000_I2C_DC_STOP" when last byte, or it will cause
error when I2C write operation.
Fixes: 21575a7a8d4c ("I2C: JZ4780: Add support for the X1000.")
Reported-by: 杨文龙 (Yang Wenlong)
Tested-by: 杨文龙 (Yang Wenlong)
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
For SoCs after X1000, only send "X1000_I2C_DC_STOP" when last byte,
or it will cause error when I2C write operation.
v1->v2:
1.Add missing Reported-by and Tested-by.
2.Remove change which not related to the bugfix.
周琰杰 (Zhou Yanjie) (1):
I2C: JZ4780: Fix bug for Ingenic X1000.
, CI20's OTG port has a great probability to
face overcurrent warning, which breaks the OTG functionality.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Signed-off-by: Dragan Čečavac
---
drivers/usb/dwc2/Kconfig | 6 ++
drivers/usb/dwc2/core.c | 9 +
2 files changed, 15 insertions(+)
diff --
Hi Paul,
On 2021/3/23 上午1:40, Paul Cercueil wrote:
Hi Zhou,
Le mer. 17 mars 2021 à 20:41, Zhou Yanjie
a écrit :
Hi Paul,
On 2021/3/7 下午10:17, Paul Cercueil wrote:
Add the CGU code and the compatible string to the TCU driver to support
the JZ4760 SoC.
Signed-off-by: Paul Cercueil
Hi Ilya,
On 2021/3/3 下午11:55, Ilya Lipnitskiy wrote:
On Wed, Mar 3, 2021 at 7:50 AM Eric W. Biederman wrote:
Ilya Lipnitskiy writes:
On Tue, Mar 2, 2021 at 11:37 AM Eric W. Biederman wrote:
Ilya Lipnitskiy writes:
On Mon, Mar 1, 2021 at 12:43 PM Eric W. Biederman wrote:
Ilya Lipnitsk
Hi Paul,
On 2021/3/28 上午2:30, Paul Cercueil wrote:
Hi Zhou,
Le jeu. 25 mars 2021 à 16:38, Zhou Yanjie
a écrit :
Hi,
On 2021/3/23 上午2:24, Paul Cercueil wrote:
Le mer. 17 mars 2021 à 17:58, 周琰杰 (Zhou Yanjie)
a écrit :
Add support for probing the pinctrl-ingenic driver on the
JZ4755
Hi Paul,
On 2021/3/28 上午3:58, Paul Cercueil wrote:
Hi Zhou,
Le jeu. 25 mars 2021 à 17:03, Zhou Yanjie
a écrit :
Hi Paul,
On 2021/3/23 上午2:39, Paul Cercueil wrote:
Le mer. 17 mars 2021 à 17:58, 周琰杰 (Zhou Yanjie)
a écrit :
Add support for probing the pinctrl-ingenic driver on the
Hi Ilya,
On 2021/3/29 上午10:48, Ilya Lipnitskiy wrote:
On Sat, Mar 20, 2021 at 8:59 AM Zhou Yanjie wrote:
Hi Ilya,
On 2021/3/3 下午11:55, Ilya Lipnitskiy wrote:
On Wed, Mar 3, 2021 at 7:50 AM Eric W. Biederman wrote:
Ilya Lipnitskiy writes:
On Tue, Mar 2, 2021 at 11:37 AM Eric W
/r/CALCv0x2YqOXEAy2Q=hafjhHCtTHVodChv1qpM=niaxopqeb...@mail.gmail.com
Signed-off-by: Ilya Lipnitskiy
Cc: Hugh Dickins
Cc: "Eric W. Biederman"
Cc: sta...@vger.kernel.org
---
mm/memory.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Tested-by: 周琰杰 (Zhou Yanjie) # on
CU1000
This reverts commit f685a533a7fab35c5d069dcd663f59c8e4171a75.
It cause kernel panic on Ingenic X1830, so let's revert it.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
arch/mips/mm/cache.c | 31 ++-
1 file changed, 14 insertions(+), 17 deletions(-)
diff --git a/arch/mi
The MII group of JZ4770's MAC should have 7 pins, add missing
pins to the MII group.
Fixes: 5de1a73e78ed ("Pinctrl: Ingenic: Add missing parts for JZ4770 and
JZ4780.")
Cc:
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Andy Shevchenko
Reviewed-by: Paul Cercueil
---
Notes:
Add X1830 support in "ingenic_pinconf_get()", so that it can read the
configuration of X1830 SoC correctly.
Fixes: d7da2a1e4e08 ("pinctrl: Ingenic: Add pinctrl driver for X1830.")
Cc:
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Andy Shevchenko
Reviewed-by: Paul Cercueil
Adjust the sequence of X1830's SSI related codes to make it consistent
with other Ingenic SoCs.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Andy Shevchenko
Reviewed-by: Paul Cercueil
---
Notes:
v2:
New patch.
v2->v3:
Add Paul Cercueil's Reviewed-by.
e two interfaces supported by X1830 are respectively referred to as
"TFT interface" and "SLCD interface", so the "lcd-rgb-xxx" is replaced
with "lcd-tft-xxx" to avoid confusion.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v4:
New patch.
v4-
Add support for probing the pinctrl-ingenic driver on the
JZ4750 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Andy Shevchenko
---
Notes:
v3:
New patch.
v3->v4:
1.Use "lcd-special" and "lcd-generic" instead "lcd-18bit-tft"
1.Move the "INGENIC_PIN_GROUP_FUNCS" to the macro definition section.
2.Add tabs before values to align the code in the macro definition section.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Andy Shevchenko
Reviewed-by: Paul Cercueil
---
Notes:
v2:
New patch.
v2-&g
Add the pinctrl bindings for the JZ4730 SoC, the JZ4750 SoC,
the JZ4755 SoC, the JZ4775 SoC and the X2000 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Rob Herring
---
Notes:
v2:
New patch.
v2->v3:
No change.
v3->v4:
1.Add a descript
ointless.
4.Improve the structure of some functions.
5.Adjust function names to avoid confusion.
6.Use "lcd-special" and "lcd-generic" instead "lcd-xxbit-tft".
7.Replace "lcd-rgb-xxx" with "lcd-tft-xxx" to avoid confusion.
v4->v5:
Add suppor
Add support for probing the pinctrl-ingenic driver on the
JZ4755 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Andy Shevchenko
---
Notes:
v3:
New patch.
v3->v4:
1.Split lcd pins into several groups.
2.Drop "lcd-no-pins" which is pointless
register pairs which have
2 bits for each GPIO pin.
Tested-by: H. Nikolaus Schaller # on Letux400
Co-developed-by: Paul Boddie
Signed-off-by: Paul Boddie
Signed-off-by: H. Nikolaus Schaller
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Andy Shevchenko
---
Notes:
v3:
New patch
Add support for probing the pinctrl-ingenic driver on the
X2000 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Andy Shevchenko
---
Notes:
v3:
New patch.
v3->v4:
1.Split lcd pins into several groups.
2.Drop "lcd-no-pins" which is poi
Add support for probing the pinctrl-ingenic driver on the
JZ4775 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Andy Shevchenko
---
Notes:
v3:
New patch.
v3->v4:
1.Split lcd pins into several groups.
2.Drop "lcd-no-pins" which is pointless
Hi Wolfram,
On 2021/3/31 下午3:18, Wolfram Sang wrote:
Hi,
Any write operation? I wonder then why nobody noticed before?
The standard I2C communication should look like this:
Read:
device_addr + w, reg_addr, device_addr + r, data;
Write:
device_addr + w, reg_addr, data;
But without this
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