From: Honghui Zhang
Move the struct defines of mtk iommu into a new header files for
common use.
Signed-off-by: Honghui Zhang
---
drivers/iommu/mtk_iommu.c | 48 +
drivers/iommu/mtk_iommu.h | 77
From: Honghui Zhang
Mediatek's m4u(Multimedia Memory Management Unit) and SMI(Smart
Multimedia Interface)have two generations HW. They basically sharing the
same hardware block diagram, but have some difference as below:
Generation one m4u only supports one
From: Honghui Zhang
Add the dtsi node of iommu and smi for mt2701.
Signed-off-by: Honghui Zhang
---
arch/arm/boot/dts/mt2701.dtsi | 51 +++
1 file changed, 51 insertions(+)
diff --git
From: Honghui Zhang
This patch defines the local arbitor port IDs for mediatek SoC MT2701 and
add descriptions of binding for mediatek generation one iommu and smi.
Signed-off-by: Honghui Zhang
Acked-by: Rob Herring
---
From: Honghui Zhang
Mediatek SoC's M4U has two generations of HW architcture. Generation one
uses flat, one layer pagetable, and was shipped with ARM architecture, it
only supports 4K size page mapping. MT2701 SoC uses this generation one
m4u HW. Generation two uses
From: Honghui Zhang
Mediatek SMI has two generations of HW architecture, mt8173 uses the
second generation of SMI HW while mt2701 uses the first generation
HW of SMI.
There's slight differences between the two generations, for generation 2,
the register which control
From: Honghui Zhang
The device_node will be released in of_iommu_configure, it may be double
released if call of_node_put in mtk_iommu_of_xlate.
Signed-off-by: Honghui Zhang
---
drivers/iommu/mtk_iommu.c | 1 -
1 file changed, 1
From: Honghui Zhang
Mediatek SoC's M4U has two generations of HW architcture. Generation one
uses flat, one layer pagetable, and was shipped with ARM architecture, it
only supports 4K size page mapping. MT2701 SoC uses this generation one
m4u HW. Generation two uses
From: Honghui Zhang
Mediatek's m4u(Multimedia Memory Management Unit) and SMI(Smart
Multimedia Interface)have two generations HW. They basically sharing the
same hardware block diagram, but have some difference as below:
Generation one m4u only supports one
From: Honghui Zhang
This patch defines the local arbitor port IDs for mediatek SoC MT2701 and
add descriptions of binding for mediatek generation one iommu and smi.
Signed-off-by: Honghui Zhang
Acked-by: Rob Herring
---
From: Honghui Zhang
Move the struct defines of mtk iommu into a new header files for
common use.
Signed-off-by: Honghui Zhang
---
drivers/iommu/mtk_iommu.c | 48 +
drivers/iommu/mtk_iommu.h | 77
From: Honghui Zhang
Add the dtsi node of iommu and smi for mt2701.
Signed-off-by: Honghui Zhang
---
arch/arm/boot/dts/mt2701.dtsi | 51 +++
1 file changed, 51 insertions(+)
diff --git
From: Honghui Zhang
Mediatek SMI has two generations of HW architecture, mt8173 uses the
second generation of SMI HW while mt2701 uses the first generation
HW of SMI.
There's slight differences between the two generations, for generation 2,
the register which control
From: Honghui Zhang
This patch defines the local arbitor port IDs for mediatek SoC MT2701 and
add descriptions of binding for mediatek generation one iommu and smi.
Signed-off-by: Honghui Zhang
---
From: Honghui Zhang
Mediatek SoC's M4U has two generations of HW architcture. Generation one
uses flat, one layer pagetable, and was shipped with ARM architecture, it
only supports 4K size page mapping. MT2701 SoC uses this generation one
m4u HW. Generation two uses
From: Honghui Zhang
Move the struct defines of mtk iommu into a new header files for
common use.
Signed-off-by: Honghui Zhang
---
drivers/iommu/mtk_iommu.c | 62 +---
drivers/iommu/mtk_iommu.h | 90
From: Honghui Zhang
Add the dtsi node of iommu and smi for mt2701.
Signed-off-by: Honghui Zhang
---
arch/arm/boot/dts/mt2701.dtsi | 51 +++
1 file changed, 51 insertions(+)
diff --git
From: Honghui Zhang
Mediatek SMI has two generations of HW architecture, mt8173 uses the
second generation of SMI HW while mt2701 uses the first generation
HW of SMI.
There's slight differences between the two generations, for generation 2,
the register which control
From: Honghui Zhang
Mediatek's m4u(Multimedia Memory Management Unit) and SMI(Smart
Multimedia Interface)have two generations HW. They basically sharing the
same hardware block diagram, but have some difference as below:
Generation one m4u only supports one
From: Honghui Zhang
Add the dtsi node of iommu and smi for mt2701.
Signed-off-by: Honghui Zhang
---
arch/arm/boot/dts/mt2701.dtsi | 51 +++
1 file changed, 51 insertions(+)
diff --git
From: Honghui Zhang
Mediatek's m4u(Multimedia Memory Management Unit) and SMI(Smart
Multimedia Interface)have two generations HW. They basically sharing the
same hardware block diagram, but have some difference as below:
Generation one m4u only support one layer,
From: Honghui Zhang
Mediatek SoC's M4U have two generations of HW architcture. Generation one
use flat, one layer pagetable, and was shipped with ARM architecture, it
only support 4K size page mapping. MT2701 SoC use this generation one
m4u HW. Generation two uses the
From: Honghui Zhang
This patch defines the local arbitor port IDs for mediatek SoC MT2701 and
add descriptions of binding for mediatek generation one iommu and smi.
Signed-off-by: Honghui Zhang
---
From: Honghui Zhang
Mediatek SMI have two generation HW architecture, mt8173 use the
secondary generation of SMI HW while mt2701 use the first generation
HW of SMI.
There's slight differences between the two generation, for generation 2,
the register which control
From: Honghui Zhang
Move the struct defines of mtk iommu into a new header files for
common use.
Signed-off-by: Honghui Zhang
---
drivers/iommu/mtk_iommu.c | 62 +---
drivers/iommu/mtk_iommu.h | 90
From: Honghui Zhang
larb2 have 23 ports, the LARB3_PORT_OFFSET should be LARB2_PORT_OFFSET
plus larb2's port number, it should be 44 instead of 43.
Signed-off-by: Honghui Zhang
---
include/dt-bindings/memory/mt2701-larb-port.h | 2 +-
1
From: Honghui Zhang
For mtk iommu, the domain_finalize was called in device attatch, the mtk
iommu iopgt ops was allocated and initialized in domain_finalize, the
iommu_group_create_direct_mappings would call the map interface to
implement the map. If it's earlier
From: Honghui Zhang
Mediatek's gen1 smi need the hardware larbid to identify the offset for
the register which controls whether enable iommu for this larb.
In the commit 3c8f4ad85c4b ("memory/mediatek: add support for mt2701"),
the larbid was used without properly
From: Honghui Zhang
This patch add larbid descritptions for mediatek's gen1 smi larb hardware.
Signed-off-by: Honghui Zhang
---
.../bindings/memory-controllers/mediatek,smi-larb.txt | 15 +++
1 file changed, 15
From: Honghui Zhang
In the commit 3c8f4ad85c4b ("memory/mediatek: add support for mt2701"),
the larb->larbid was added but not initialized.
Mediatek's gen1 smi need this hardware larbid information to get the
register offset which controls whether enable iommu for
From: Honghui Zhang
Add mediatek's hardware id information for smi larb.
Signed-off-by: Honghui Zhang
---
arch/arm/boot/dts/mt2701.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/mt2701.dtsi
From: Honghui Zhang
Mediatek's gen1 smi need the hardware larb-id to identify the offset for
the register which controls whether enable iommu for this larb.
In the commit 3c8f4ad85c4b ("memory/mediatek: add support for mt2701"),
the larbid was used without properly
From: Honghui Zhang
In the commit 3c8f4ad85c4b ("memory/mediatek: add support for mt2701"),
the larb->larbid was added but not initialized.
Mediatek's gen1 smi need this hardware larbid information to get the
register offset which controls whether enable iommu for
From: Honghui Zhang
Replace custom code with generic helper to retrieve driver data.
Signed-off-by: Honghui Zhang
---
drivers/memory/mtk-smi.c | 14 ++
1 file changed, 2 insertions(+), 12 deletions(-)
diff --git
From: Honghui Zhang
Add mediatek's hardware id information for smi larb.
Signed-off-by: Honghui Zhang
---
arch/arm/boot/dts/mt2701.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/mt2701.dtsi
From: Honghui Zhang
This patch add larbid descritptions for mediatek's gen1 smi larb hardware.
Acked-by: Rob Herring
Signed-off-by: Honghui Zhang
---
.../bindings/memory-controllers/mediatek,smi-larb.txt | 15
From: Ryder Lee
This is a transitional patch. We currently use platfarm_get_resource() for
retrieving the IOMEM resources, but there might be some chips don't have
subsys/shared registers part, which depends on platform design, and these
will be introduced in further
From: Ryder Lee
Wait Gen2 training by using readl_poll_timeout() calls, and simplify
the hardware assert logical by merge it into the new interface
mtk_pcie_startup_port.
Signed-off-by: Ryder Lee
Signed-off-by: Honghui Zhang
From: Ryder Lee
MT2712 and MT7622 using a new IP block of Gen2 controller which has two
root ports and shares the same probing flow with MT2701/MT7623.
Both MT2712 and MT7622 have the same per-port control registers, but
there are slight differences between them:
MT7622
From: Ryder Lee
Add controller support for mt2712/mt7622 and update related
properities.
Signed-off-by: Ryder Lee
Signed-off-by: Honghui Zhang
Acked-by: Rob Herring
---
From: Honghui Zhang
Introduce a structure "mtk_pcie_soc" to abstract the differences between
controller generations, and the .startup() hook is used to encapsulate
some SoC-dependent related setting. In doing so, the common code which
will be reused by future chips.
From: Ryder Lee
In order to accommodate other SoC generations, this patch updates filename
to make it more generic, regroups specific properties by SoCs, and removes
redundant descriptions.
Signed-off-by: Ryder Lee
Signed-off-by: Honghui Zhang
From: Honghui Zhang
Rename "port->index" to "port->slot" since the ports are hardwired at
PCI_SLOT. Also rename "mtk_pcie_parse_ports" to "mtk_pcie_parse_port"
since it parses one port each time.
No functional change in this patch.
Signed-off-by: Honghui Zhang
From: Honghui Zhang
MediaTek's PCIe host controller has two generation HWs, MT2712 and MT7622
using the new generation HW, which has two root ports. They share most
probing flow with MT2701/MT7623. But the read/write config space logical
is different. The per-port
From: Honghui Zhang
MT2712 and MT7622's PCIe host controller support 32bit address MSI, and it
connect to GIC with the same IRQ number of INTx IRQ, so it shares the same
IRQ with INTx IRQ.
This patch adds MSI support for MT2712 and MT7622.
Signed-off-by: Honghui
From: Honghui Zhang
MT2712 and MT7622's PCIe host controller support MSI, but only 32bit MSI
address are supportted. It connect to GIC with the same IRQ number of INTx
IRQ, so it shares the same IRQ with INTx IRQ.
This patch add MSI support for MT2712 and MT7622.
From: Honghui Zhang
MT2712 and MT7622's PCIe host controller support MSI, but only 32bit MSI
address are supportted. It connect to GIC with the same IRQ number of INTx
IRQ, so it shares the same IRQ with INTx IRQ.
This patchset add MSI support for MT2712 and MT7622.
From: Honghui Zhang
In commit ae02a6dda285 ("PCI: mediatek: Add controller support for MT2712
and MT7622"), the function 'mtk_pcie_init_irq_domain', the pattern used to
check and return error is:
if (!var) {
dev_err(...);
return PTR_ERR(var);
}
The
From: Honghui Zhang
Commit ae02a6dda285 ("PCI: mediatek: Add controller support for MT2712 and
MT7622") has put the mtk_pcie * into bus->sysdata, take advantage of that
to get the private data and simplify the code.
Signed-off-by: Honghui Zhang
From: Honghui Zhang
MediaTek's PCIe host controller has two generation HWs, the new
generation HW has two root ports, it shares most probing flow with the
legacy controller. But the read/write config space logical is different
from the lagacy controller.
This patchset
From: Ryder Lee
In order to accommodate other SoC generations, this patch updates filename
to make it more generic, regroups specific properties by SoCs, and removes
redundant descriptions.
Signed-off-by: Ryder Lee
---
From: Ryder Lee
Introduce a structure "mtk_pcie_soc" to abstract the differences between
controller generations, and the .startup() hook is used to encapsulate
some SoC-dependent related setting. In doing so, the common code which
will be reused by future chips.
In
From: Ryder Lee
Add support for new Gen2 controller which has two root ports and shares the
probing flow with legacy controller. Currently this IP block can be found
on MT7622/MT2712. More specifically, the newer (future) chips will be
developed based on this generation,
From: Ryder Lee
This is a transitional patch. We currently use platfarm_get_resource() for
retrieving the IOMEM resources, but there might be some chips don't have
subsys/shared registers part, which depends on platform design, and these
will be introduced in further
From: Ryder Lee
Add support for MediaTek new generation controller and update related
properities.
Signed-off-by: Ryder Lee
Signed-off-by: Honghui Zhang
---
.../devicetree/bindings/pci/mediatek-pcie.txt | 84
From: Honghui Zhang
Replace custom code with generic helper to retrieve driver data.
Signed-off-by: Honghui Zhang
---
drivers/memory/mtk-smi.c | 14 ++
1 file changed, 2 insertions(+), 12 deletions(-)
diff --git
From: Honghui Zhang
Replace custom code with generic helper to retrieve driver data.
Signed-off-by: Honghui Zhang
---
drivers/memory/mtk-smi.c | 14 ++
1 file changed, 2 insertions(+), 12 deletions(-)
diff --git
From: Honghui Zhang
Replace custom code with generic helper to retrieve driver data.
Signed-off-by: Honghui Zhang
---
drivers/memory/mtk-smi.c | 18 --
1 file changed, 4 insertions(+), 14 deletions(-)
diff --git
From: Ryder Lee
Introduce a structure "mtk_pcie_soc" to abstract the differences between
controller generations, and the .startup() hook is used to encapsulate
some SoC-dependent related setting. In doing so, the common code which
will be reused by future chips.
In
From: Ryder Lee
Add support for new Gen2 controller which has two root ports and shares
the probing flow with legacy controller. Currently this IP block can be
found on MT7622/MT2712.
Signed-off-by: Ryder Lee
Signed-off-by: Honghui Zhang
From: Ryder Lee
In order to accommodate other SoC generations, this patch updates filename
to make it more generic, regroups specific properties by SoCs, and removes
redundant descriptions.
Signed-off-by: Ryder Lee
---
From: Ryder Lee
Add support for MediaTek new generation controller and update related
properities.
Signed-off-by: Ryder Lee
Signed-off-by: Honghui Zhang
---
.../devicetree/bindings/pci/mediatek-pcie.txt | 168
From: Ryder Lee
This is a transitional patch. We currently use platfarm_get_resource() for
retrieving the IOMEM resources, but there might be some chips don't have
subsys/shared registers part, which depends on platform design, and these
will be introduced in further
From: Ryder Lee
Add support for MediaTek new generation controller and update related
properities.
Signed-off-by: Ryder Lee
Signed-off-by: Honghui Zhang
---
.../devicetree/bindings/pci/mediatek-pcie.txt | 168
From: Honghui Zhang
Add mediatek's hardware id information for smi larb.
Signed-off-by: Honghui Zhang
---
arch/arm/boot/dts/mt2701.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/mt2701.dtsi
From: Honghui Zhang
In the commit 3c8f4ad85c4b ("memory/mediatek: add support for mt2701"),
the larb->larbid was added but not initialized.
Mediatek's gen1 smi need this hardware larbid information to get the
register offset which controls whether enable iommu for
From: Honghui Zhang
This patch add larbid descritptions for mediatek's gen1 smi larb hardware.
Signed-off-by: Honghui Zhang
---
.../bindings/memory-controllers/mediatek,smi-larb.txt | 15 +++
1 file changed, 15
From: Honghui Zhang
Mediatek's gen1 smi need the hardware larbid to identify the offset for
the register which controls whether enable iommu for this larb.
In the commit 3c8f4ad85c4b ("memory/mediatek: add support for mt2701"),
the larbid was used without properly
From: Honghui Zhang
MediaTek's PCIe host controller has two generation HWs, the new
generation HW has two root ports, it shares most probing flow with the
legacy controller. But the read/write config space logical is different
from the lagacy controller.
This patchset
From: Ryder Lee
MediaTek's PCIe host controller has two generation HWs, the new
generation HW has two root ports, it shares most probing flow with the
legacy controller. But the read/write config space logical is different
from the legacy controller. The per-port register
From: Ryder Lee
Add support for MediaTek new generation controller and update related
properities.
Signed-off-by: Ryder Lee
Signed-off-by: Honghui Zhang
Acked-by: Rob Herring
---
From: Honghui Zhang
Introduce a structure "mtk_pcie_soc" to abstract the differences between
controller generations, and the .startup() hook is used to encapsulate
some SoC-dependent related setting. In doing so, the common code which
will be reused by future chips.
From: Ryder Lee
Wait Gen2 training by using readl_poll_timeout() calls, and simplify
the hardware assert logical by merge it into the new interface
mtk_pcie_startup_ports.
Signed-off-by: Ryder Lee
Signed-off-by: Honghui Zhang
From: Ryder Lee
In order to accommodate other SoC generations, this patch updates filename
to make it more generic, regroups specific properties by SoCs, and removes
redundant descriptions.
Signed-off-by: Ryder Lee
Signed-off-by: Honghui Zhang
From: Honghui Zhang
MediaTek's PCIe host controller has two generation HWs, the new
generation HW has two root ports, it shares most probing flow with the
legacy controller. But the read/write config space logical is different
from the legacy controller. The per-port
From: Ryder Lee
This is a transitional patch. We currently use platfarm_get_resource() for
retrieving the IOMEM resources, but there might be some chips don't have
subsys/shared registers part, which depends on platform design, and these
will be introduced in further
From: Honghui Zhang
Switch from using a custom NUM_INTX macro to the generic PCI_NUM_INTX
definition for the number of INTx interrupts.
Signed-off-by: Honghui Zhang
---
drivers/pci/host/pcie-mediatek.c | 5 ++---
1 file changed, 2
From: Honghui Zhang
There maybe a same irq reentry scenario after irq received in current
irq handle flow:
EP device PCIe host driverEP driver
1. issue an irq
2. received irq
3. clear irq
From: Honghui Zhang
Two fixups for mediatek's host bridge:
The first patch fixup the IRQ handle routine to avoid IRQ reentry which
may exist for both MT2712 and MT7622.
The second patch fixup class type for MT7622.
Change since v2:
- Move the initialize of the
From: Honghui Zhang
The MTCMOS of PCIe Host for MT2712 will be off when system suspend, and all
the internal control register will be reset after system resume. The PCIe
link should be re-established and the related control register values
should be re-set after system resume.
Signed-off-by:
From: Honghui Zhang
The MTCMOS of PCIe Host for MT2712 will be off when system suspend, and all
the internel control register will be reset after system resume. The PCIe
link should be re-established and the related control register values should
be re-set after system resume.
Signed-off-by:
From: Honghui Zhang
The MTCMOS of PCIe Host for MT2712 will be off when system suspend, and all
the internal control register will be reset after system resume. The PCIe
link should be re-established and the related control register values
should be re-set after system resume.
Signed-off-by:
From: Honghui Zhang
The Mediatek's host controller has two slots, each with it's own control
registers. The host driver need to identify which slot was connected
in order to access the device's configuration space. There's problem
for current host driver to find out which slot was connected to
From: Honghui Zhang
The MTCMOS of PCIe Host for MT2712 and MT7622 will be off when system
suspend, and all the internal control register will be reset after system
resume. The PCIe link should be re-established and the related control
register values should be re-set after system resume.
From: Honghui Zhang
The clocks was not enabled when enable MSI. This patch fix this
issue by calling mtk_pcie_enable_msi in mtk_pcie_startup_port_v2
since the clock was all enabled at that time.
The function of mtk_pcie_startup_port_v2's define location is
re-arranged to avoid
From: Honghui Zhang
Implement remove callback function for Mediatek PCIe driver to add
loadable kernel module support.
Signed-off-by: Honghui Zhang
Reviewed-by: Ryder Lee
---
drivers/pci/controller/Kconfig | 2 +-
drivers/pci/controller/pcie-mediatek.c | 60
From: Honghui Zhang
This patchset includes misc patchs:
The first patch fixup the mtk_pcie_find_port logical which will cause system
could not touch the EP's configuration space which was connected to PCIe slot 1.
The second patch fixup the enable msi logical, the operation to enable msi
From: Honghui Zhang
The clocks was not enabled when enable MSI. This patch fix this
issue by calling mtk_pcie_enable_msi in mtk_pcie_startup_port_v2
since the clock was all enabled at that time.
The function of mtk_pcie_startup_port_v2's define location is
re-arranged to avoid
From: Honghui Zhang
The Mediatek's host controller has two slots, each with it's own control
registers. The host driver need to identify which slot was connected
in order to access the device's configuration space. There's problem
for current host driver to find out which slot was connected to
From: Honghui Zhang
Implement remove callback function for Mediatek PCIe driver to add
loadable kernel module support.
Signed-off-by: Honghui Zhang
---
drivers/pci/controller/Kconfig | 2 +-
drivers/pci/controller/pcie-mediatek.c | 60 +++---
2 files
From: Honghui Zhang
This patchset includes misc patchs:
The first patch fixup the mtk_pcie_find_port logical which will cause system
could not touch the EP's configuration space which was connected to PCIe slot 1.
The second patch fixup the enable msi logical, the operation to enable msi
From: Honghui Zhang
The MTCMOS of PCIe Host for MT2712 and MT7622 will be off when system
suspend, and all the internal control register will be reset after system
resume. The PCIe link should be re-established and the related control
register values should be re-set after system resume.
From: Honghui Zhang
The MTCMOS of PCIe Host for MT2712 will be off when system suspend, and all
the internal control register will be reset after system resume. The PCIe
link should be re-established and the related control register values
should be re-set after system resume.
Signed-off-by:
From: Honghui Zhang
This patchset includes misc patchs:
The first patch fixup the mtk_pcie_find_port logical which will cause system
could not touch the EP's configuration space which was connected to PCIe slot 1.
The second patch fixup the enable msi logical, the operation to enable msi
From: Honghui Zhang
The clocks was not enabled when enable MSI. This patch fix this
issue by calling mtk_pcie_enable_msi in mtk_pcie_startup_port_v2
since the clock was all enabled at that time.
The function of mtk_pcie_startup_port_v2's define location is
re-arranged to avoid
From: Honghui Zhang
The MTCMOS of PCIe Host for MT2712 and MT7622 will be off when system
suspend, and all the internal control register will be reset after system
resume. The PCIe link should be re-established and the related control
register values should be re-set after system resume.
From: Honghui Zhang
Implement remove callback function for Mediatek PCIe driver to add
loadable kernel module support.
Signed-off-by: Honghui Zhang
Reviewed-by: Ryder Lee
---
drivers/pci/controller/Kconfig | 2 +-
drivers/pci/controller/pcie-mediatek.c | 63
From: Honghui Zhang
Mediatek's host controller have two slots, each have it's own control
registers. The host driver need to identify which slot was connected
in order to access the device's configuration space. There's problem
for current host driver to find out which slot was connected to for
From: Honghui Zhang
Using irq_chip solution to setup IRQs in order to consist
with IRQ framework.
Signed-off-by: Honghui Zhang
Acked-by: Ryder Lee
---
drivers/pci/host/pcie-mediatek.c | 206
From: Honghui Zhang
Two fixups for mediatek's host bridge:
The first patch fixup class type and vendor ID for MT7622.
The second patch fixup the IRQ handle routine by using irq_chip solution
to avoid IRQ reentry which may exist for both MT2712 and MT7622.
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