Hi Rob, Thanks for your advice, and I already sent the second patch.
Change note: 1: modify the subject for 0001* 2: modify the description for 0003* Best Regards, Yunfei Dong -----邮件原件----- 发件人: Rob Herring [mailto:r...@kernel.org] 发送时间: 2019年1月4日 7:17 收件人: Yunfei Dong (董云飞) 抄送: Tiffany Lin (林慧珊); Andrew-CT Chen (��智迪); Mauro Carvalho Chehab; Mark Rutland; Matthias Brugger; linux-me...@vger.kernel.org; devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-media...@lists.infradead.org; Qianqian Yan (阎倩倩) 主题: Re: [PATCH 1/3] media: dt-bindings: media: Fix MTK document for vcodec On Fri, Dec 28, 2018 at 02:33:03PM +0800, Yunfei Dong wrote: > Fix MTK binding document for MT8173 dtsi changed in order to use > standard CCF interface. > MT8173 SoC from Mediatek. A better subject would be "add 'assigned-clocks' to vcodec examples". > > Signed-off-by: Yunfei Dong <yunfei.d...@mediatek.com> > Signed-off-by: Qianqian Yan <qianqian....@mediatek.com> > --- > .../devicetree/bindings/media/mediatek-vcodec.txt | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git > a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt > b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt > index 2a615d84a682..b6b5dde6abd8 100644 > --- a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt > +++ b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt > @@ -66,6 +66,15 @@ vcodec_dec: vcodec@16000000 { > "vencpll", > "venc_lt_sel", > "vdec_bus_clk_src"; > + assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>, > + <&topckgen CLK_TOP_CCI400_SEL>, > + <&topckgen CLK_TOP_VDEC_SEL>, > + <&apmixedsys CLK_APMIXED_VCODECPLL>, > + <&apmixedsys CLK_APMIXED_VENCPLL>; > + assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>, > + <&topckgen CLK_TOP_UNIVPLL_D2>, > + <&topckgen CLK_TOP_VCODECPLL>; > + assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>; > }; > > vcodec_enc: vcodec@18002000 { > @@ -105,4 +114,8 @@ vcodec_dec: vcodec@16000000 { > "venc_sel", > "venc_lt_sel_src", > "venc_lt_sel"; > + assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>, > + <&topckgen CLK_TOP_VENC_LT_SEL>; > + assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>, > + <&topckgen CLK_TOP_UNIVPLL1_D2>; > }; > -- > 2.19.1 >
