-by: Sibi Sankar
Signed-off-by: Abel Vesa
---
drivers/remoteproc/qcom_q6v5_pas.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/remoteproc/qcom_q6v5_pas.c
b/drivers/remoteproc/qcom_q6v5_pas.c
index 117fdfdfbc26..581ae5e570e8 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
From: Sibi Sankar
Add support for PIL loading on ADSP and CDSP on X1E80100 SoCs.
Signed-off-by: Sibi Sankar
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Abel Vesa
---
drivers/remoteproc/qcom_q6v5_pas.c | 41 ++
1 file changed, 41 insertions(+)
diff --git
Document the aDSP and cDSP Peripheral Authentication Service on the
X1E80100 Platform.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Abel Vesa
---
Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Documentation
Signed-off-by: Abel Vesa
---
Changes in v2:
- Added Krzysztof's R-b tag to bindings patch
- Added Dmitry's R-b tag to the X1E80100 related patch
- Dropped the comment about the comment from adsp_load about lite
version
- Link to v1:
https://lore.kernel.org/r/20240129-x1e80100-remoteproc-v1-0
On 24-01-29 17:17:28, Dmitry Baryshkov wrote:
> On Mon, 29 Jan 2024 at 15:35, Abel Vesa wrote:
> >
> > From: Sibi Sankar
> >
> > The UEFI loads a lite variant of the ADSP firmware to support charging
> > use cases. The kernel needs to unload and reload it wi
-by: Sibi Sankar
Signed-off-by: Abel Vesa
---
drivers/remoteproc/qcom_q6v5_pas.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/remoteproc/qcom_q6v5_pas.c
b/drivers/remoteproc/qcom_q6v5_pas.c
index 083d71f80e5c..4f6940368eb4 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
From: Sibi Sankar
Add support for PIL loading on ADSP and CDSP on X1E80100 SoCs.
Signed-off-by: Sibi Sankar
Signed-off-by: Abel Vesa
---
drivers/remoteproc/qcom_q6v5_pas.c | 41 ++
1 file changed, 41 insertions(+)
diff --git a/drivers/remoteproc
Document the aDSP and cDSP Peripheral Authentication Service on the
X1E80100 Platform.
Signed-off-by: Abel Vesa
---
Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom
Signed-off-by: Abel Vesa
---
Abel Vesa (1):
dt-bindings: remoteproc: qcom,sm8550-pas: document the X1E80100 aDSP &
cDSP
Sibi Sankar (2):
remoteproc: qcom_q6v5_pas: Add support for X1E80100 ADSP/CDSP
remoteproc: qcom_q6v5_pas: Unload lite firmware on ADSP
.../bind
On 21-04-08 00:06:29, Stephen Boyd wrote:
> Quoting Abel Vesa (2021-04-04 13:40:24)
> > The following changes since commit a38fd8748464831584a19438cbb3082b5a2dab15:
> >
> > Linux 5.12-rc2 (2021-03-05 17:33:41 -0800)
> >
> > are available in the
The following changes since commit a38fd8748464831584a19438cbb3082b5a2dab15:
Linux 5.12-rc2 (2021-03-05 17:33:41 -0800)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux.git clk/imx
for you to fetch changes up to
On 21-04-02 19:48:41, Adrien Grassein wrote:
> Hi,
>
> Le ven. 2 avr. 2021 à 19:42, Abel Vesa a écrit :
> >
> > On 21-04-02 18:45:04, Adrien Grassein wrote:
> > > Hi,
> > >
> > > this patch et aims to add the support of the i.MX 8 Power Domain driv
On 21-04-02 18:45:04, Adrien Grassein wrote:
> Hi,
>
> this patch et aims to add the support of the i.MX 8 Power Domain driver.
> Some devices (like usbotg2) can't work without this patch as their
> attached power domain are down.
>
> The original drivr was taken from le imx kernel and aapted to
On 21-03-23 11:10:34, Jian Dong wrote:
> From: Jian Dong
>
> when register failed, clk will be freed, it will generate dangling pointer
> problem in later reference. it should return directly.
>
> Signed-off-by: Jian Dong
Applied, thanks.
> ---
> drivers/clk/imx/clk-lpcg-scu.c | 1 +
>
On 21-03-15 16:17:48, Richard Zhu wrote:
> - The sys2_pll_50m should be one of the clock sels of PCIE_AUX clock.
> Change the sys2_pll_500m to sys2_pll_50m.
> - Correct one mis-spell of the imx8mq_pcie1_ctrl_sels definition, from
> "sys2_pll_250m" to "sys2_pll_333m".
>
> Signed-off-by: Richard
On 21-03-15 16:17:47, Richard Zhu wrote:
> In the i.MX8MP PCIe design, the PCIe PHY REF clock comes from external
> OSC or internal system PLL. It is configured in the IOMUX_GPR14 register
> directly, and can't be contolled by CCM at all.
> Remove the PCIE PHY clock from clock driver to clean up
On 21-03-24 09:02:43, Stephen Rothwell wrote:
> Hi all,
>
> Please try to avoid merging branches based on v5.12-rc1-dontuse - ask
> the branch owner to rebase onto (at least) v5.12-rc2.
>
Oups, fixed now.
> --
> Cheers,
> Stephen Rothwell
)
> Suggested-by: Aisheng Dong
> Signed-off-by: Adam Ford
> Reviewed-by: Abel Vesa
> Tested-by: Ahmad Fatoum
>
> ---
> V4: Check if of_stdout is available before using it.
> Re-align #ifdef to remove repeated code.
> V3: Return a method more closely related to upst
On 21-03-20 18:00:25, Adam Ford wrote:
> On Sun, Mar 14, 2021 at 4:40 AM Ahmad Fatoum wrote:
> >
> > On 13.03.21 16:16, Ahmad Fatoum wrote:
> > >> +/* i.MX boards use device trees now. For build tests without
> > >> CONFIG_OF, do nothing */
> > >> +#ifdef CONFIG_OF
> > >> if
On 21-03-15 15:39:24, Richard Zhu wrote:
> In the i.MX8MP PCIe design, the PCIe PHY REF clock comes from external
> OSC or internal system PLL. It is configured in the IOMUX_GPR14 register
> directly, and can't be contolled by CCM at all.
> Remove the PCIE PHY clock from clock driver to clean up
On 21-03-03 10:31:19, Abel Vesa wrote:
> On 21-03-02 13:03:04, Adam Ford wrote:
> > On Mon, Feb 15, 2021 at 7:06 AM Abel Vesa wrote:
> > >
> > > On 21-02-13 08:44:28, Adam Ford wrote:
> > > > On Wed, Feb 3, 2021 at 3:22 PM Adam Ford wrote:
> > > &g
On 21-02-25 13:13:17, Martin Kepplinger wrote:
> On 23.02.21 18:20, Abel Vesa wrote:
> > On 21-02-22 17:03:13, Martin Kepplinger wrote:
> > > On 19.02.21 16:59, Abel Vesa wrote:
> > > > This has been on my queue for quite some time now. It is more
Instead of locking explicitly every time, call the clk_core_enable_lock
variant.
Signed-off-by: Abel Vesa
---
drivers/clk/clk.c | 12 ++--
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 5052541..fd37773 100644
--- a/drivers/clk
On 21-03-02 13:03:04, Adam Ford wrote:
> On Mon, Feb 15, 2021 at 7:06 AM Abel Vesa wrote:
> >
> > On 21-02-13 08:44:28, Adam Ford wrote:
> > > On Wed, Feb 3, 2021 at 3:22 PM Adam Ford wrote:
> > > >
> > > > On Thu, Jan 21, 2021 at 4:24 AM Abel Ve
On 20-11-03 13:18:12, Abel Vesa wrote:
> The BLK_CTL according to HW design is basically the wrapper of the entire
> function specific group of IPs and holds GPRs that usually cannot be placed
> into one specific IP from that group. Some of these GPRs are used to control
> some clocks
On 21-02-22 17:03:13, Martin Kepplinger wrote:
> On 19.02.21 16:59, Abel Vesa wrote:
> > This has been on my queue for quite some time now. It is more of a
> > proof-of-concept.
> >
> > This rework is done with the compatibility of future i.MX platforms in
> &g
On 21-02-19 18:00:11, Abel Vesa wrote:
> The fsl,icc-id property here is used to link the icc node
> registered by the imx8mq interconnect driver with the noc
> device. Remove the fsl,ddrc property since it will not be used
> anymore.
>
> Signed-off-by: Abel Vesa
> ---
&
The fsl,icc-id property here is used to link the icc node
registered by the imx8mq interconnect driver with the noc
device. Remove the fsl,ddrc property since it will not be used
anymore.
Signed-off-by: Abel Vesa
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 4 ++--
scripts/dtc/fdtoverlay
in reducing the clock speeds along the icc path
for each pl301 and NoC, but still meet the requirements for all the
other icc consumers.
Signed-off-by: Abel Vesa
---
drivers/mmc/host/sdhci-esdhc-imx.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/mmc/host
The icc node will be probed by the imx8mq interconnect driver.
Will look-up the NoC and all the pl301s (identified by fsl,icc-id property)
and will assign the corresponding icc node to each one of them.
Then, it will register the icc provider.
Signed-off-by: Abel Vesa
---
arch/arm64/boot/dts
in reducing the clock speeds along the icc path
for each pl301 and NoC, but still meet the requirements for all the
other icc consumers.
Signed-off-by: Abel Vesa
---
drivers/net/ethernet/freescale/fec.h | 3 +++
drivers/net/ethernet/freescale/fec_main.c | 19 +++
2 files changed
Add all the pl301s found on i.MX8MQ, according to the bus diagram.
Each pl301 has its own clock, icc id and opp table. They are probed
by the imx-bus driver.
Signed-off-by: Abel Vesa
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 180 ++
1 file changed, 180 insertions
-off-by: Abel Vesa
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 6a64b4bf31f5..43760316052f 100644
--- a/arch/arm64/boot/dts/freescale
Now that the imx generic interconnect doesn't use the
imx_icc_node_adj_desc, we remove it from all the i.MX8M
platform drivers.
Signed-off-by: Abel Vesa
---
drivers/interconnect/imx/imx.h| 19 -
drivers/interconnect/imx/imx8mm.c | 32 +---
drivers
The fsl,icc-id property here is used to link the icc node
registered by the imx8mq interconnect driver with the ddrc
device.
Signed-off-by: Abel Vesa
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
b
The i.MX8MQ driver will probe based on the compatible string
instead of using device data in imx-bus devfreq driver.
Signed-off-by: Abel Vesa
---
drivers/interconnect/imx/imx8mq.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/interconnect/imx/imx8mq.c
b/drivers
The aggregate function will return whatever is the highest
rate for that specific node. The imx_icc_get_bw sets the
initial avg and peak to 0 in order to avoid setting them to
INT_MAX by the interconnect core.
Signed-off-by: Abel Vesa
---
drivers/interconnect/imx/imx.c | 20
nodes in the dts we will have a
interconnect dedicated node. This node will be the actual device of the
icc provider.
Signed-off-by: Abel Vesa
---
drivers/interconnect/imx/imx.c | 72 +++---
1 file changed, 32 insertions(+), 40 deletions(-)
diff --git a/drivers
.
Signed-off-by: Abel Vesa
---
drivers/interconnect/imx/imx8mq.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/interconnect/imx/imx8mq.c
b/drivers/interconnect/imx/imx8mq.c
index b8c36d668946..010ad3d76286 100644
--- a/drivers/interconnect/imx/imx8mq.c
In order to allow the dram_apb to be switched to a different parent,
we need to remove the CLK_IS_CRITICAL flag. This leads to clock
being disabled on clk_disabled_unused call, so add the
CLK_IGNORE_UNUSED instead to avoid that.
Signed-off-by: Abel Vesa
---
drivers/clk/imx/clk-imx8mq.c | 2
Seems that, in order to be able to resume from suspend, the dram rate
needs to be the highest one available. Therefore, add the late system
suspend/resume PM ops which set the highest rate on suspend and the
latest one used before suspending on resume.
Signed-off-by: Abel Vesa
---
drivers
The link between an imx-bus device and its icc id will be done
through the fsl,icc-id property in each dts node. The imx
interconnect driver will pick up all the dts nodes that have that
property defined and will link them to the rightfull icc id.
Signed-off-by: Abel Vesa
---
drivers/devfreq
By switching to powersave governor, we allow the imx8m-ddrc to always
run at minimum rate needed by all the running masters.
Signed-off-by: Abel Vesa
---
drivers/devfreq/imx8m-ddrc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/devfreq/imx8m-ddrc.c b/drivers
i.MX8M platforms get their dram OPPs from the EL3.
We don't need to duplicate that in the kernel dram dts node.
We should just trust the OPPs provided by the EL3.
Signed-off-by: Abel Vesa
---
drivers/devfreq/imx8m-ddrc.c | 49 ++--
1 file changed, 2 insertions
By switching to powersave governor, we allow the imx-bus to always run
at minimum rate needed by all the running masters.
Signed-off-by: Abel Vesa
---
drivers/devfreq/imx-bus.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/devfreq/imx-bus.c b/drivers/devfreq/imx
.
Signed-off-by: Abel Vesa
---
include/dt-bindings/interconnect/imx8mq.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/include/dt-bindings/interconnect/imx8mq.h
b/include/dt-bindings/interconnect/imx8mq.h
index 1a4cae7f8be2..1953de8af5cb 100644
--- a/include/dt-bindings/interconnect
t icc path accordingly.
Abel Vesa (19):
clk: imx8mq: Replace critical with ignore_unused flag for dram_apb
clock
dt-bindings: interconnect: imx8mq: Add missing pl301 and SAI ids
devfreq: imx-bus: Switch governor to powersave
devfreq: imx-bus: Decouple imx-bus from icc made
devfreq:
On 21-02-13 08:44:28, Adam Ford wrote:
> On Wed, Feb 3, 2021 at 3:22 PM Adam Ford wrote:
> >
> > On Thu, Jan 21, 2021 at 4:24 AM Abel Vesa wrote:
> > >
> > > On 21-01-21 10:56:17, Sascha Hauer wrote:
> > > > On Wed, Jan 20, 2021 at 06:14:21PM +0200,
On 21-01-29 09:19:48, Sascha Hauer wrote:
> On Wed, Jan 27, 2021 at 01:16:31PM +0200, Abel Vesa wrote:
> > On 21-01-27 11:47:20, Sascha Hauer wrote:
> > > On Wed, Jan 27, 2021 at 12:12:20PM +0200, Abel Vesa wrote:
> > > > On 21-01-26 15:30:17, Sascha Hauer wrote:
On 21-01-27 11:47:20, Sascha Hauer wrote:
> On Wed, Jan 27, 2021 at 12:12:20PM +0200, Abel Vesa wrote:
> > On 21-01-26 15:30:17, Sascha Hauer wrote:
> > > On Tue, Jan 26, 2021 at 03:12:39PM +0200, Abel Vesa wrote:
> > > > On 21-01-26 12:51:05, Sascha Hauer wrote:
On 21-01-26 15:30:17, Sascha Hauer wrote:
> On Tue, Jan 26, 2021 at 03:12:39PM +0200, Abel Vesa wrote:
> > On 21-01-26 12:51:05, Sascha Hauer wrote:
> > > On Tue, Jan 26, 2021 at 01:21:36PM +0200, Abel Vesa wrote:
> > > > Some clocks are already enabled in HW even be
On 21-01-26 12:51:05, Sascha Hauer wrote:
> On Tue, Jan 26, 2021 at 01:21:36PM +0200, Abel Vesa wrote:
> > Some clocks are already enabled in HW even before the kernel
> > starts to boot. So, in order to make sure that these clocks do not
> > get disabled when clk_disabl
with CLK_IGNORE_UNUSED flag
and also needs to have the is_enabled ops implemented.
Signed-off-by: Abel Vesa
---
drivers/clk/clk.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 3d751ae5bc70..26d55851cfa5 100644
--- a/drivers
On 21-01-21 10:56:17, Sascha Hauer wrote:
> On Wed, Jan 20, 2021 at 06:14:21PM +0200, Abel Vesa wrote:
> > On 21-01-20 16:50:01, Sascha Hauer wrote:
> > > On Wed, Jan 20, 2021 at 05:28:13PM +0200, Abel Vesa wrote:
> > > > On 21-01-20 16:13:05, Sascha
On 21-01-20 16:50:01, Sascha Hauer wrote:
> On Wed, Jan 20, 2021 at 05:28:13PM +0200, Abel Vesa wrote:
> > On 21-01-20 16:13:05, Sascha Hauer wrote:
> > > Hi Abel,
> > >
> > > On Wed, Jan 20, 2021 at 04:44:54PM +0200, Abel Vesa wrote:
> >
On 21-01-20 16:13:05, Sascha Hauer wrote:
> Hi Abel,
>
> On Wed, Jan 20, 2021 at 04:44:54PM +0200, Abel Vesa wrote:
> > On 21-01-18 08:00:43, Adam Ford wrote:
> > > On Mon, Jan 18, 2021 at 6:52 AM Abel Vesa wrote:
...
> > >
> > > >
> > >
On 21-01-18 08:00:43, Adam Ford wrote:
> On Mon, Jan 18, 2021 at 6:52 AM Abel Vesa wrote:
> >
> > On 21-01-15 12:29:08, Adam Ford wrote:
> >
> > ...
> >
> > > diff --git a/drivers/clk/imx/clk-imx25.c b/drivers/clk/imx/clk-imx25.c
> > > index a6
On 21-01-15 12:29:08, Adam Ford wrote:
...
> diff --git a/drivers/clk/imx/clk-imx25.c b/drivers/clk/imx/clk-imx25.c
> index a66cabfbf94f..66192fe0a898 100644
> --- a/drivers/clk/imx/clk-imx25.c
> +++ b/drivers/clk/imx/clk-imx25.c
> @@ -73,16 +73,6 @@ enum mx25_clks {
>
> static struct clk
Add a section for NXP i.MX clock drivers and list myself
as the maintainer.
Signed-off-by: Abel Vesa
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 2894657..9eafd4d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12827,6 +12827,13 @@ F
On 20-12-31 17:33:40, Fabio Estevam wrote:
> Hi Martin,
>
> On Thu, Dec 31, 2020 at 11:22 AM Martin Kepplinger
> wrote:
> >
> > This reverts commit 936c383673b9e3007432f17140ac62de53d87db9.
> >
> > It breaks clock reparenting via devfreq on the imx8mq used in the
> > Librem 5 phone. When
Some composite clocks might be enabled/disabled from outside the
clock framework. So allow the composite clock register successfully
with only the .is_enabled op for gate ops.
Signed-off-by: Abel Vesa
---
drivers/clk/clk-composite.c | 19 ++-
1 file changed, 10 insertions(+), 9
Both dram_apb and dram_alt are controlled by EL3. Using the dram
variant registration of the composite-8m clock, the mux and the
divider will be read only. Do this for all i.MX8M platforms.
Signed-off-by: Abel Vesa
---
drivers/clk/imx/clk-imx8mm.c | 4 ++--
drivers/clk/imx/clk-imx8mn.c | 4
The clocks that can be changed from outside of the clock common framework
scope (for example, EL3) need to have only the .is_enabled gate op.
Signed-off-by: Abel Vesa
---
drivers/clk/clk-gate.c | 5 +
include/linux/clk-provider.h | 1 +
2 files changed, 6 insertions(+)
diff --git
The switch between parents for dram_apb and dram_alt is done in EL3,
so make all the ops read-only. That means none of the ops that write
any of the registers is used for such a clock.
Signed-off-by: Abel Vesa
---
drivers/clk/imx/clk-composite-8m.c | 12 +++-
drivers/clk/imx/clk.h
This can be used by the clocks that have their parents changed from EL3.
This way the clk_get_parent will read the value from register instead of
using the value stored in the core framework.
Signed-off-by: Abel Vesa
Suggested-by: Peng Fan
---
drivers/clk/clk.c| 31
the registers.
Changes since v1:
* allow generic composite clock registration with .is_enabled gate op
only
Abel Vesa (5):
clk: Add clk_gate_ro_ops for read-only gate clocks
clk: Add CLK_GET_PARENT_NOCACHE flag
clk: composite: Allow gate ops with only .is_enabled op
clk: imx: composite-8m
On 20-11-11 17:13:25, Dong Aisheng wrote:
> On Tue, Nov 3, 2020 at 7:22 PM Abel Vesa wrote:
> ...
> > +static int imx_blk_ctl_reset_set(struct reset_controller_dev *rcdev,
> > + unsigned long id, bool assert)
> > +{
> > + struc
In the reference manual the actual name is Audio BLK_CTL.
Lets make it more obvious here by renaming from audiomix to audio_blk_ctl.
Signed-off-by: Abel Vesa
Acked-by: Rob Herring
Reviewed-by: Dong Aisheng
---
include/dt-bindings/clock/imx8mp-clock.h | 120 +++
1
These will be used by the imx8mp for blk_ctl driver.
Signed-off-by: Abel Vesa
Acked-by: Rob Herring
Reviewed-by: Dong Aisheng
---
include/dt-bindings/reset/imx8mp-reset.h | 28
1 file changed, 28 insertions(+)
diff --git a/include/dt-bindings/reset/imx8mp-reset.h
These will be used imx8mp for blk_ctl driver.
Signed-off-by: Abel Vesa
Acked-by: Rob Herring
Reviewed-by: Dong Aisheng
---
include/dt-bindings/reset/imx8mp-reset.h | 12
1 file changed, 12 insertions(+)
diff --git a/include/dt-bindings/reset/imx8mp-reset.h
b/include/dt-bindings
These will be used by the imx8mp for blk_ctl driver.
Signed-off-by: Abel Vesa
Acked-by: Rob Herring
Reviewed-by: Dong Aisheng
---
include/dt-bindings/clock/imx8mp-clock.h | 40
1 file changed, 40 insertions(+)
diff --git a/include/dt-bindings/clock/imx8mp
Some of the features of the audio_ctl will be used by some
different drivers in a way those drivers will know best, so adding the
syscon compatible we allow those to do just that. Only the resets
and the clocks are registered bit the clk-blk-ctl driver.
Signed-off-by: Abel Vesa
Reviewed-by: Dong
to be able to use the imx clock API, this needs to be
in a clock driver. From there it can use the reset controller API and
leave the rest to the syscon.
Signed-off-by: Abel Vesa
---
drivers/clk/imx/Makefile | 2 +-
drivers/clk/imx/clk-blk-ctl.c | 302
According to the RM, the CCGR101 is shared for the following root clocks:
- AUDIO_AHB_CLK_ROOT
- AUDIO_AXI_CLK_ROOT
- SAI2_CLK_ROOT
- SAI3_CLK_ROOT
- SAI5_CLK_ROOT
- SAI6_CLK_ROOT
- SAI7_CLK_ROOT
- PDM_CLK_ROOT
Signed-off-by: Abel Vesa
Reviewed-by: Dong Aisheng
---
drivers/clk/imx/clk-imx8mp.c
Document the i.MX BLK_CTL with its devicetree properties.
Signed-off-by: Abel Vesa
Reviewed-by: Dong Aisheng
Reviewed-by: Rob Herring
---
.../devicetree/bindings/clock/fsl,imx-blk-ctl.yaml | 60 ++
1 file changed, 60 insertions(+)
create mode 100644 Documentation
All these IDs are for one single HW gate (CCGR101) that is shared
between these root clocks.
Signed-off-by: Abel Vesa
Acked-by: Rob Herring
Reviewed-by: Dong Aisheng
---
include/dt-bindings/clock/imx8mp-clock.h | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git
Some of the features of the media_ctl will be used by some
different drivers in a way those drivers will know best, so adding the
syscon compatible we allow those to do just that. Only the resets
and the clocks are registered bit the clk-blk-ctl driver.
Signed-off-by: Abel Vesa
Reviewed-by: Dong
the bus_blk_clk in the imx8mp blk_ctl driver (media_blk_ctl)
* added the R-b tag from Rob to the documentation patch
Abel Vesa (14):
dt-bindings: clocks: imx8mp: Rename audiomix ids clocks to
audio_blk_ctl
dt-bindings: reset: imx8mp: Add audio blk_ctl reset IDs
dt-bindings: clock: imx8mp
These will be used by the imx8mp for blk_ctl driver.
Signed-off-by: Abel Vesa
Acked-by: Rob Herring
Reviewed-by: Dong Aisheng
---
include/dt-bindings/clock/imx8mp-clock.h | 28
1 file changed, 28 insertions(+)
diff --git a/include/dt-bindings/clock/imx8mp-clock.h
These will be used by the imx8mp for blk_ctl driver.
Signed-off-by: Abel Vesa
Acked-by: Rob Herring
Reviewed-by: Dong Aisheng
---
include/dt-bindings/reset/imx8mp-reset.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/dt-bindings/reset/imx8mp-reset.h
b/include/dt-bindings
This driver is intended to work with the following BLK_CTL IPs found in
i.MX8MP:
- Audio
- Media
- HDMI
Signed-off-by: Abel Vesa
---
drivers/clk/imx/Makefile | 2 +-
drivers/clk/imx/clk-blk-ctl-imx8mp.c | 317 +++
2 files changed, 318 insertions
Some of the features of the hdmi_ctl will be used by some
different drivers in a way those drivers will know best, so adding the
syscon compatible we allow those to do just that. Only the resets
and the clocks are registered bit the clk-blk-ctl driver.
Signed-off-by: Abel Vesa
---
arch/arm64
On 20-10-31 00:21:01, Adam Ford wrote:
> On Mon, Oct 26, 2020 at 2:33 PM Abel Vesa wrote:
> >
> > This driver is intended to work with the following BLK_CTL IPs found in
> > i.MX8MP:
> > - Audio
> > - Media
> > - HDMI
> >
> > Signed-off-b
On 20-10-29 12:54:58, Lucas Stach wrote:
> Am Montag, den 26.10.2020, 11:23 -0500 schrieb Adam Ford:
> > On Mon, Oct 26, 2020 at 10:44 AM Lucas Stach wrote:
> > > Am Montag, den 26.10.2020, 10:12 -0500 schrieb Adam Ford:
> > > > On Mon, Oct 26, 2020 at 9:55 AM Abel V
On some i.MX8 platforms, there are HW gates that share the same bit.
So in order to make this clock type more usable, use a mask to specify
how many bits belong to those HW gates.
Signed-off-by: Abel Vesa
---
drivers/clk/imx/clk-gate2.c | 16 ++--
drivers/clk/imx/clk.h | 24
This was a hack which would allow multiple HW gates to be controlled
by a single bit. The only user of this is the imx_dev_clk_hw_gate_shared
which is not used anywhere as of now. Basically, complicates the logic
of the driver for no reason.
Signed-off-by: Abel Vesa
---
drivers/clk/imx/clk
Seems the logic here was wrong all along. For example, if
the cgr_val is 2 (0b10), the clk_gate2_reg_is_enabled would
report the clock as disabled. So check against cgr_val instead.
Signed-off-by: Abel Vesa
---
drivers/clk/imx/clk-gate2.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions
First version here: https://lkml.org/lkml/2020/10/26/988
Changes since v1:
* split the work in multiple iterative patches
Abel Vesa (5):
clk: imx: gate2: Remove the IMX_CLK_GATE2_SINGLE_BIT special case
clk: imx: gate2: Keep the register writing in on place
clk: imx: gate2: Check if clock
Move all the register writing to the newly added clk_gate2_do_shared_clks
and call that everywhere need needed. Cleans up the code a little bit.
Signed-off-by: Abel Vesa
---
drivers/clk/imx/clk-gate2.c | 33 -
1 file changed, 16 insertions(+), 17 deletions
Protect against enabling/disabling the gate while we're
checking if it is enabled.
Signed-off-by: Abel Vesa
---
drivers/clk/imx/clk-gate2.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c
index 7e4b5e8
On 20-10-28 11:15:52, Sascha Hauer wrote:
> On Wed, Oct 28, 2020 at 11:50:57AM +0200, Abel Vesa wrote:
> > On 20-10-28 09:24:12, Sascha Hauer wrote:
> > > Hi Abel,
> > >
> > > On Mon, Oct 26, 2020 at 08:50:48PM +0200, Abel Vesa wrote:
> > >
On 20-10-28 09:24:12, Sascha Hauer wrote:
> Hi Abel,
>
> On Mon, Oct 26, 2020 at 08:50:48PM +0200, Abel Vesa wrote:
> > The clock is considered to be enabled only if the controlling bits
> > match the cgr_val mask. Also make sure the is_enabled returns the
> > correct
On 20-10-27 11:57:56, t...@redhat.com wrote:
> From: Tom Rix
>
> A semicolon is not needed after a switch statement.
>
> Signed-off-by: Tom Rix
Reviewed-by: Abel Vesa
> ---
> drivers/clk/imx/clk-pll14xx.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
On 20-10-27 11:31:10, Abel Vesa wrote:
> On 20-10-26 16:37:51, Lucas Stach wrote:
> > Am Montag, den 26.10.2020, 16:55 +0200 schrieb Abel Vesa:
> > > On 20-10-25 11:05:32, Adam Ford wrote:
> > > > On Sun, Oct 25, 2020 at 7:19 AM Marek Vasut wrote:
> > > &
On 20-10-26 16:44:13, Lucas Stach wrote:
> Am Montag, den 26.10.2020, 10:12 -0500 schrieb Adam Ford:
> > On Mon, Oct 26, 2020 at 9:55 AM Abel Vesa wrote:
> > > On 20-10-25 11:05:32, Adam Ford wrote:
> > > > On Sun, Oct 25, 2020 at 7:19 AM Marek Vasut wrote:
>
On 20-10-26 16:37:51, Lucas Stach wrote:
> Am Montag, den 26.10.2020, 16:55 +0200 schrieb Abel Vesa:
> > On 20-10-25 11:05:32, Adam Ford wrote:
> > > On Sun, Oct 25, 2020 at 7:19 AM Marek Vasut wrote:
> > > > On 10/
Document the i.MX BLK_CTL with its devicetree properties.
Signed-off-by: Abel Vesa
Reviewed-by: Dong Aisheng
---
.../devicetree/bindings/clock/fsl,imx-blk-ctl.yaml | 60 ++
1 file changed, 60 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/fsl,imx
All these IDs are for one single HW gate (CCGR101) that is shared
between these root clocks.
Signed-off-by: Abel Vesa
Acked-by: Rob Herring
---
include/dt-bindings/clock/imx8mp-clock.h | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock
According to the RM, the CCGR101 is shared for the following root clocks:
- AUDIO_AHB_CLK_ROOT
- AUDIO_AXI_CLK_ROOT
- SAI2_CLK_ROOT
- SAI3_CLK_ROOT
- SAI5_CLK_ROOT
- SAI6_CLK_ROOT
- SAI7_CLK_ROOT
- PDM_CLK_ROOT
Signed-off-by: Abel Vesa
Reviewed-by: Dong Aisheng
---
drivers/clk/imx/clk-imx8mp.c
Some of the features of the audio_ctl will be used by some
different drivers in a way those drivers will know best, so adding the
syscon compatible we allow those to do just that. Only the resets
and the clocks are registered bit the clk-blk-ctl driver.
Signed-off-by: Abel Vesa
Reviewed-by: Dong
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