Hi, James,
> On 25/08/2020 03:31, Alison Wang wrote:
> >> On 09/07/2020 09:22, Alison Wang wrote:
> >>> Add error detection for A53 and A72 cores. Hardware error injection
> >>> is supported on A53. Software error injection is supported on both.
> >&g
Hi, James,
> On 09/07/2020 09:22, Alison Wang wrote:
> > Add error detection for A53 and A72 cores. Hardware error injection is
> > supported on A53. Software error injection is supported on both.
>
>
> As we can't safely write to these registers from linux, so I
Hi, Kurt,
> On Wed Jul 29 2020, Alison Wang wrote:
> > In the current arm64 defconfig, CONFIG_IRQ_TIME_ACCOUNTING is enabled
> > as default. According to my tests on NXP's LayerScape and i.MX
> > platforms, the system hangs when running the command "s
ssue
disappears. CONFIG_IRQ_TIME_ACCOUNTING causes serious performance impact
when running hrtimer stress test at the same time.
Signed-off-by: Alison Wang
---
arch/arm64/configs/defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/
the driver. Failure to enable access
disables hardware error injection. For error detection to work, another
SMC call enables access to L2ECTLR_EL1.
It is for NXP's Layerscape family LS1043A, LS1046A, LS2088A and LX2160A.
Signed-off-by: York Sun
Signed-off-by: Alison Wang
---
.../bindings
This patch adds pmu dt nodes for LS1028A.
Signed-off-by: Alison Wang
---
Changes in v2:
- Update compatible property.
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
b
Hi, Shawn,
> On Wed, Feb 27, 2019 at 09:57:52AM +0800, Alison Wang wrote:
> > This patch adds pmu dt nodes for LS1028A.
> >
> > Signed-off-by: Alison Wang
> > ---
> > arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi |5 +
> > 1 files changed, 5 ins
This patch adds Audio DT nodes for LS1028ARDB and LS1028AQDS boards.
Signed-off-by: Alison Wang
---
Changes in v3:
- Sort EDMA node in unit-address.
Changes in v2:
- Modify some nodes' names.
- Use GIC_SPI and IRQ_TYPE_LEVEL_HIGH.
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts |
> On Wed, Feb 20, 2019 at 04:44:57PM +0800, Alison Wang wrote:
> > This patch adds Audio DT nodes for LS1028ARDB and LS1028AQDS boards.
> >
> > Signed-off-by: Alison Wang
> > ---
> > Changes in v2:
> > - Modify some nodes' names.
> > - Use GI
This patch adds pmu dt nodes for LS1028A.
Signed-off-by: Alison Wang
---
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
This patch adds Audio DT nodes for LS1028ARDB and LS1028AQDS boards.
Signed-off-by: Alison Wang
---
Changes in v2:
- Modify some nodes' names.
- Use GIC_SPI and IRQ_TYPE_LEVEL_HIGH.
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 62
arch/arm64/boot/dts/free
Hi, Shawn,
> On Wed, Jan 23, 2019 at 01:21:35PM +0800, Alison Wang wrote:
> > This patch adds Audio DT nodes for LS1028ARDB and LS1028AQDS boards.
> >
> > Signed-off-by: Alison Wang
> > ---
> > arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 62
> +
This patch adds Audio DT nodes for LS1028ARDB and LS1028AQDS boards.
Signed-off-by: Alison Wang
---
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 62
arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 63 +
arch/arm64/boot/dts/freescale/fsl
value, the issues are gone.
Signed-off-by: Alison Wang
---
Change in v2:
- Add the description about this new property in the dt-bindings.
.../devicetree/bindings/sound/sgtl5000.txt |9 +
sound/soc/codecs/sgtl5000.c| 19 ++-
2 files c
value, the issues are gone.
Signed-off-by: Alison Wang
---
sound/soc/codecs/sgtl5000.c | 19 ++-
1 files changed, 18 insertions(+), 1 deletions(-)
diff --git a/sound/soc/codecs/sgtl5000.c b/sound/soc/codecs/sgtl5000.c
index add18d6..a6a4748 100644
--- a/sound/soc/codecs/sgtl50
s that it emulates a timer hardware via a hrtimer and then tells
> the cpu idle code not to go into deep power states on the cpu which owns
> that hrtimer. All other cpus can go as deep as they want and still get
> woken up.
>
> The only downside of adding this unconditionally is
before calling
drm_atomic_helper_resume().
The patch is verified on LS1021ATWR board.
Signed-off-by: Alison Wang
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
b/drivers/gpu/drm/fsl
ue.
This patch is verified on LS1021ATWR board.
Signed-off-by: Alison Wang
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
index 58e9e0601a61..875
> On Mon, 13 Feb 2017 07:39:41 +
> Alison Wang wrote:
>
> > Hi, Boris,
> >
> > Sorry, I forgot to change them. Should I resend them or you help
> to fix that when applying?
>
> I can fix that when applying, no need to resend.
> Note that you m
Hi, Boris,
Sorry, I forgot to change them. Should I resend them or you help to fix
that when applying?
Best Regards,
Alison Wang
>
> Hi Alison,
>
> The subject prefix is still wrong, should be 'memory: ifc: '.
>
> On Mon, 13 Feb 2017 14:46:55 +0800
>
As NAND support for Freescale/NXP IFC controller is available on
LS1021A, the dependency for LS1021A is added.
LS1021A is an earlier product and is not compatible with later
LayerScape architecture. So ARCH_LAYERSCAPE can't cover LS1021A.
Signed-off-by: Alison Wang
---
Changes in v3:
- U
Hi, Boris,
> On Thu, 5 Jan 2017 02:02:30 +
> Alison Wang wrote:
>
> > > On 01/04/2017 02:46 AM, Alison Wang wrote:
> > > >> On 01/03/2017 03:41 AM, Alison Wang wrote:
> > > >>> As NAND support for Freescale/NXP IFC controller is available
As Freescale/NXP IFC controller is available on LS1021A, the dependency
for LS1021A is added.
LS1021A is an earlier product and is not compatible with later
LayerScape architecture. So ARCH_LAYERSCAPE can't cover LS1021A.
Signed-off-by: Alison Wang
---
Changes in v3:
- Update the commit me
> On 01/04/2017 02:46 AM, Alison Wang wrote:
> >> On 01/03/2017 03:41 AM, Alison Wang wrote:
> >>> As NAND support for Freescale/NXP IFC controller is available on
> >>> LS1021A, the dependency for LS1021A is added.
> >>
> >> D
> On 01/03/2017 03:41 AM, Alison Wang wrote:
> > As NAND support for Freescale/NXP IFC controller is available on
> > LS1021A, the dependency for LS1021A is added.
>
> Does LS stand for LayerScape ? Yes it does. So why does ARCH_LAYERSCAPE
> not cover LS1021 ?
[Alison Wan
Ok, I see. Thanks.
Best Regards,
Alison Wang
> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@free-electrons.com]
> Sent: Tuesday, January 03, 2017 5:05 PM
> To: Alison Wang
> Cc: marek.va...@gmail.com; cyrille.pitc...@atmel.com; linux-
> ker.
As NAND support for Freescale/NXP IFC controller is available on
LS1021A, the dependency for LS1021A is added.
Signed-off-by: Alison Wang
---
Changes in v2:
- None
drivers/mtd/nand/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/Kconfig b/drivers
As Freescale/NXP IFC controller is available on LS1021A, the dependency
for LS1021A is added.
Signed-off-by: Alison Wang
---
Changes in v2:
- New patch
drivers/memory/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
ve the system]
> >
> > url: https://github.com/0day-ci/linux/commits/Alison-Wang/mtd-
> nand-Update-dependency-of-IFC-for-LS1021A/20161229-125233
> > base: git://git.infradead.org/linux-mtd.git master
> > config: arm-allmodconfig (attached as .config)
> > compiler
As NAND support for Freescale/NXP IFC controller is available on
LS1021A, the dependency for LS1021A is added.
Signed-off-by: Alison Wang
---
drivers/mtd/nand/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index
The ARMv8 architecture supports two execution state, AArch64 and
AArch32. To support KVM in AArch32 execution state for ARMv8, Cortex-A53
and Cortex-A72 need to be added for target-specific checks.
Signed-off-by: Alison Wang
---
arch/arm/include/asm/cputype.h | 2 ++
arch/arm/kvm/guest.c
The patch adds SMP support for running 32-bit Linux kernel for
Layerscape platforms. Spin-table method is used for SMP support.
Signed-off-by: Alison Wang
Signed-off-by: Chenhui Zhao
---
arch/arm/mach-imx/common.h | 1 +
arch/arm/mach-imx/mach-layerscape.c | 1 +
arch/arm/mach-imx
LayerScape platforms.
Verified on LayerScape LS1043ARDB, LS1012ARDB, LS1046ARDB boards.
Signed-off-by: Ebony Zhu
Signed-off-by: Alison Wang
---
arch/arm/Kconfig| 9 +
arch/arm/mach-imx/Kconfig | 14 ++
arch/arm/mach-imx/Makefile | 4
According to the current clock driver for Freescale QorIQ platform, new
clock binding will be used for LS1021A.
Signed-off-by: Alison Wang
---
arch/arm/boot/dts/ls1021a.dtsi | 97 +-
1 file changed, 40 insertions(+), 57 deletions(-)
diff --git a/arch/arm
According to the new mapping table, the partition for NOR flash
is added.
Signed-off-by: Alison Wang
---
arch/arm/boot/dts/ls1021a-qds.dts | 60 +++
arch/arm/boot/dts/ls1021a-twr.dts | 60 +++
2 files changed, 120
This patch enables some drivers for LS1021A, such as
GIANFAR, WATCHDOG, AUDIO, QSPI, I2C, ESDHC, EDMA, FTM.
QorIQ Clock Framework and Ramdisk support is also enabled.
Signed-off-by: Alison Wang
---
arch/arm/configs/multi_v7_defconfig | 14 ++
1 file changed, 14 insertions(+)
diff
GIANFAR,
I2C, WATCHDOG, AUDIO, EDMA and DSPI drivers, etc.
The other platforms need to be verified by the platform
maintainers too.
Signed-off-by: Alison Wang
---
arch/arm/configs/multi_v7_lpae_defconfig | 597 +++
1 file changed, 597 insertions(+)
create mode 100644
v7 LPAE multi-platform defconfig is based on v7 multi-platform
defconfig and adds LPAE support.
This defconfig is verified on LS1021A which enables GIANFAR,
I2C, WATCHDOG, AUDIO, EDMA and DSPI drivers, etc.
Signed-off-by: Alison Wang
---
arch/arm/configs/multi_v7_lpae_defconfig | 168
Signed-off-by: Alison Wang
---
Changes since v3:
- Modify the commit.
Changes since v2:
- Enable PSCI, as PSCI is enabled in u-boot.
Changes since v1:
- Enable GIANFAR, Sound and DSPI.
arch/arm/configs/ls1021a_defconfig | 160 +
1 file changed, 160 insertions
This patch adds Power Management support for SAI.
Activate regmap cache with REGCACHE_FLAT, and use
regmap cache code to save and restore registers in
suspend and resume. The Transmit Control Register
(TCSR) and Receive Control Register(RCSR) should
be volatile registers.
Signed-off-by: Alison
This patch adds dma-coherent property for eTSEC nodes, so
coherent DMA operations are supported.
Signed-off-by: Alison Wang
Signed-off-by: Shawn Guo
---
arch/arm/boot/dts/ls1021a.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts
.
Signed-off-by: Haikun Wang
Signed-off-by: Alison Wang
---
Changes since v2:
- Enable PSCI, as PSCI is enabled in u-boot.
Changes since v1:
- Enable GIANFAR, Sound and DSPI.
arch/arm/configs/ls1021a_defconfig | 161 +
1 file changed, 161 insertions
This patch adds platform notifier for dma-coherent requirement.
Structure arm_coherent_dma_ops is used instead of arm_dma_ops.
Signed-off-by: Alison Wang
---
arch/arm/mach-imx/mach-ls1021a.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/mach-imx
.
Signed-off-by: Haikun Wang
Signed-off-by: Alison Wang
---
Changes since v1:
- Enable GIANFAR, Sound and DSPI.
arch/arm/configs/ls1021a_defconfig | 160 +
1 file changed, 160 insertions(+)
create mode 100644 arch/arm/configs/ls1021a_defconfig
diff --git a
Hrtimer based broadcast is used on ARM platform. It can be
registered as the tick broadcast device in the absence of
a real external clock device.
Signed-off-by: Alison Wang
---
arch/arm/kernel/time.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/kernel/time.c b/arch/arm
This patch adds dts nodes for audio on LS1021A.
Signed-off-by: Alison Wang
Signed-off-by: Shawn Guo
---
Changes since v1:
- Remove "clocks" container, and use a unit node name.
arch/arm/boot/dts/ls1021a-qds.dts | 69 +++
arch/arm/boot/dts/ls102
Add ftm0 node, cause of ftm0 can be set as a alarm before system
going to deep sleep.
Signed-off-by: Wang Dongsheng
Signed-off-by: Alison Wang
---
Changes since v1:
- Add my SoB.
- Use "ARM:" as subject prefix.
arch/arm/boot/dts/ls1021a-qds.dts | 4
arch/arm/boot/dts/ls1021a.d
Hrtimer based broadcast mode is used instead of
periodic tick broadcast to provide high resolution
clock in SMP.
Signed-off-by: Alison Wang
---
arch/arm/mach-imx/mach-ls1021a.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/mach-imx/mach-ls1021a.c b/arch/arm/mach-imx
From: Wang Dongsheng
Add ftm0 node, cause of ftm0 can be set as a alarm before system
going to deep sleep.
Signed-off-by: Wang Dongsheng
---
arch/arm/boot/dts/ls1021a-qds.dts | 4
arch/arm/boot/dts/ls1021a.dtsi| 8
2 files changed, 12 insertions(+)
diff --git a/arch/arm/boot
From: Jia Hongtao
This patch adds LTC2945 node for LS1021A TWR board.
Signed-off-by: Jia Hongtao
---
arch/arm/boot/dts/ls1021a-twr.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts
b/arch/arm/boot/dts/ls1021a-twr.dts
index a0d9ad6..938b16a 100644
This patch adds dts nodes for audio on LS1021A.
Signed-off-by: Alison Wang
---
arch/arm/boot/dts/ls1021a-qds.dts | 71 +++
arch/arm/boot/dts/ls1021a-twr.dts | 63 ++
arch/arm/boot/dts/ls1021a.dtsi| 14
3 files
This patch adds generic dts nodes for eTSEC0, eTSEC1 and eTSEC2.
Signed-off-by: Claudiu Manoil
Signed-off-by: Alison Wang
---
arch/arm/boot/dts/ls1021a-qds.dts | 20 ++
arch/arm/boot/dts/ls1021a-twr.dts | 20 ++
arch/arm/boot/dts/ls1021a.dtsi| 82
CONFIG_GIANFAR is not depended on FSL_SOC, it
can be built on non-PPC platforms.
Signed-off-by: Alison Wang
---
drivers/net/ethernet/freescale/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/freescale/Kconfig
b/drivers/net/ethernet/freescale
This patch adds Power Management support for SAI.
Activate regmap cache with REGCACHE_RBTREE, and use
regmap cache code to save and restore registers in
suspend and resume. The Transmit Control Register
(TCSR) and Receive Control Register(RCSR) should
be volatile registers.
Signed-off-by: Alison
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