Re: [PATCH] PCI: controller: dwc: Make PCI_IMX6 depend on PCIEPORTBUS

2018-12-07 Thread Andrey Smirnov
On Fri, Dec 7, 2018 at 5:11 AM Niklas Cassel wrote: > > On Thu, Dec 06, 2018 at 08:55:13PM -0800, Andrey Smirnov wrote: > > On Thu, Dec 6, 2018 at 2:28 AM Lucas Stach wrote: > > > > > > Am Mittwoch, den 05.12.2018, 23:45 -0800 schrieb Andrey Smir

Re: [PATCH] PCI: controller: dwc: Make PCI_IMX6 depend on PCIEPORTBUS

2018-12-06 Thread Andrey Smirnov
On Thu, Dec 6, 2018 at 2:28 AM Lucas Stach wrote: > > Am Mittwoch, den 05.12.2018, 23:45 -0800 schrieb Andrey Smirnov: > > Building a kernel with CONFIG_PCI_IMX6=y, but CONFIG_PCIEPORTBUS=n > > produces a system where built-in PCIE bridge (16c3:abcd) isn't bound >

Re: [PATCH v2 0/3] PCIE support for i.MX8MQ

2018-12-06 Thread Andrey Smirnov
On Thu, Dec 6, 2018 at 4:15 AM Lorenzo Pieralisi wrote: > > On Wed, Dec 05, 2018 at 11:35:42PM -0800, Andrey Smirnov wrote: > > Everyone: > > > > This series contains changes I made in order to enable support of PCIE > > IP block on i.MX8MQ SoCs (full t

[PATCH] PCI: controller: dwc: Make PCI_IMX6 depend on PCIEPORTBUS

2018-12-05 Thread Andrey Smirnov
-by: Andrey Smirnov --- Assuming this is a reasonable dependency, shold this be done to more than just i.MX6 driver? drivers/pci/controller/dwc/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 2b139acccf32

[PATCH v2 1/3] PCI: imx: No-op imx6_setup_phy_mpll() on i.MX7D

2018-12-05 Thread Andrey Smirnov
" Cc: Richard Zhu Cc: linux-...@nxp.com Cc: linux-arm-ker...@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-...@vger.kernel.org Tested-by: Trent Piepho Signed-off-by: Andrey Smirnov --- drivers/pci/controller/dwc/pci-imx6.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/d

[PATCH v2 3/3] PCI: imx: Add support for i.MX8MQ

2018-12-05 Thread Andrey Smirnov
Cc: linux-...@vger.kernel.org Cc: Mark Rutland Cc: Rob Herring Cc: devicet...@vger.kernel.org Signed-off-by: Andrey Smirnov --- .../bindings/pci/fsl,imx6q-pcie.txt | 6 +- drivers/pci/controller/dwc/Kconfig| 2 +- drivers/pci/controller/dwc/pci-imx6.c

[PATCH v2 2/3] PCI: imx: No-op imx6_pcie_reset_phy() on i.MX7D

2018-12-05 Thread Andrey Smirnov
" Cc: Richard Zhu Cc: linux-...@nxp.com Cc: linux-arm-ker...@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-...@vger.kernel.org Tested-by: Trent Piepho Signed-off-by: Andrey Smirnov --- drivers/pci/controller/dwc/pci-imx6.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/d

[PATCH v2 0/3] PCIE support for i.MX8MQ

2018-12-05 Thread Andrey Smirnov
er-id" property to distinguish between two intances of PCIE IP block - All code pertaining to L1SS was dropped to simplify the patch - Documented additions to DT bindings Feedback is welcome! Thanks, Andrey Smirnov [v1] https://lore.kernel.org/linux-arm-kernel/20181117181225.10737-1-a

[PATCH 3/5] irqchip/irq-imx-gpcv2: Make use of BIT() macro

2018-12-05 Thread Andrey Smirnov
c: linux-arm-ker...@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov --- drivers/irqchip/irq-imx-gpcv2.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-imx-gpcv2.c b/drivers/irqchip/irq-imx-gpcv2.c index b262ba8b2652..077

[PATCH 2/5] irqchip/irq-imx-gpcv2: Share reg offset calculation code

2018-12-05 Thread Andrey Smirnov
nxp.com Cc: linux-arm-ker...@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov --- drivers/irqchip/irq-imx-gpcv2.c | 18 ++ 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/irq-imx-gpcv2.c b/drivers/irqchip/irq-imx-gpc

[PATCH 5/5] irqchip/irq-imx-gpcv2: Add support for i.MX8MQ

2018-12-05 Thread Andrey Smirnov
kernel.org Signed-off-by: Andrey Smirnov --- drivers/irqchip/irq-imx-gpcv2.c | 31 +-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-imx-gpcv2.c b/drivers/irqchip/irq-imx-gpcv2.c index c2b2b3128ddd..17a2dad2d4c2 100644 --- a/drivers/irqch

[PATCH 4/5] irqchip/irq-imx-gpcv2: Make error messages more consistent

2018-12-05 Thread Andrey Smirnov
om Cc: linux-arm-ker...@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov --- drivers/irqchip/irq-imx-gpcv2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-imx-gpcv2.c b/drivers/irqchip/irq-imx-gpcv2.c index 077d56b3183a..c2b2b3128ddd

[PATCH 0/5] i.MX8MQ support for GPCv2 irqchip driver

2018-12-05 Thread Andrey Smirnov
] https://lore.kernel.org/linux-arm-kernel/20181116154927.16152-3-l.st...@pengutronix.de/ Andrey Smirnov (5): irqchip/irq-imx-gpcv2: Remove unused code irqchip/irq-imx-gpcv2: Share reg offset calculation code irqchip/irq-imx-gpcv2: Make use of BIT() macro irqchip/irq-imx-gpcv2: Make error

[PATCH 1/5] irqchip/irq-imx-gpcv2: Remove unused code

2018-12-05 Thread Andrey Smirnov
ead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov --- drivers/irqchip/irq-imx-gpcv2.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/irqchip/irq-imx-gpcv2.c b/drivers/irqchip/irq-imx-gpcv2.c index 4760307ab43f..cbed00319315 100644 --- a/drivers/irqchip/irq-imx-gpc

[PATCH v2 3/3] dt-bindings: reset: imx7: Document usage on i.MX8MQ SoCs

2018-11-27 Thread Andrey Smirnov
Cc: linux-arm-ker...@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov --- Documentation/devicetree/bindings/reset/fsl,imx7-src.txt | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/reset/fsl,imx7-

[PATCH v2 2/3] reset: imx7: Add support for i.MX8MQ IP block variant

2018-11-27 Thread Andrey Smirnov
..@nxp.com Cc: linux-arm-ker...@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov --- drivers/reset/Kconfig| 2 +- drivers/reset/reset-imx7.c | 106 +++ include/dt-bindings/reset/imx8mq-reset.h | 64 +++

[PATCH v2 1/3] reset: imx7: Add plubming to support multiple IP variants

2018-11-27 Thread Andrey Smirnov
ob Herring Cc: devicet...@vger.kernel.org Cc: linux-...@nxp.com Cc: linux-arm-ker...@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov --- drivers/reset/reset-imx7.c | 62 +++--- 1 file changed, 45 insertions(+), 17 deletions(-)

[PATCH v2 0/3] Reset controller support for i.MX8MQ

2018-11-27 Thread Andrey Smirnov
, Andrey Smirnov Changes since [v1] - Series re-written to use a per-variant LUT instead of using a single table - Changed driver to use "imx8mq" insead of "imx8m" to match other drivers and CONFIG_ARCH_IMX8MQ - Updated list of exported i.MX8MQ resets, add missing and

Re: [PATCH v2 3/3] PCI: imx6: limit DBI register length

2018-11-27 Thread Andrey Smirnov
On Tue, Nov 27, 2018 at 5:12 PM Fabio Estevam wrote: > > Hi Andrey, > > On Tue, Nov 27, 2018 at 10:57 PM Andrey Smirnov > wrote: > > > Could this be a regression? Prior to 415b6185c541 ("PCI: imx6: Fix > > config read timeout handling") all of the imprecis

Re: [PATCH v2 3/3] PCI: imx6: limit DBI register length

2018-11-27 Thread Andrey Smirnov
be a simple fix would be to install such a handler when running on i.MX6Q? Thanks, Andrey Smirnov > > Signed-off-by: Stefan Agner > --- > drivers/pci/controller/dwc/pci-imx6.c | 5 - > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/contr

Re: [PATCH 3/3] PCI: imx: Add support for i.MX8MQ

2018-11-27 Thread Andrey Smirnov
On Tue, Nov 27, 2018 at 2:46 AM Leonard Crestez wrote: > > On 11/27/18 12:06 PM, Lucas Stach wrote: > > Hi Andrey, > > > > Am Montag, den 26.11.2018, 10:24 -0800 schrieb Andrey Smirnov: > >> On Tue, Nov 20, 2018 at 2:49 AM Leonard Crestez > >> wrot

Re: [PATCH 3/3] PCI: imx: Add support for i.MX8MQ

2018-11-27 Thread Andrey Smirnov
On Tue, Nov 27, 2018 at 2:16 AM Leonard Crestez wrote: > > On 11/26/18 8:24 PM, Andrey Smirnov wrote: > > On Tue, Nov 20, 2018 at 2:49 AM Leonard Crestez > > wrote: > >> On Sat, 2018-11-17 at 10:12 -0800, Andrey Smirnov wrote: > > >>> +

Re: [PATCH 0/3] GPCv2 support for i.MX8MQ

2018-11-26 Thread Andrey Smirnov
On Mon, Nov 19, 2018 at 6:10 AM Lucas Stach wrote: > > Hi Andrey, > > Am Samstag, den 17.11.2018, 10:12 -0800 schrieb Andrey Smirnov: > > Everyone: > > > > This series contains changes I made to add support for i.MX8MQ to > > GPCv2 driver in order to enable

Re: [PATCH 2/3] PCI: imx: No-op imx6_pcie_reset_phy() on i.MX7D

2018-11-26 Thread Andrey Smirnov
On Mon, Nov 19, 2018 at 5:22 PM Trent Piepho wrote: > > On Sat, 2018-11-17 at 10:12 -0800, Andrey Smirnov wrote: > > PCIE PHY IP block on i.MX7D differs from the one used on i.MX6 family, > > so none of the code in current implementation of imx6_pcie_reset_phy() > > i

Re: [PATCH 3/3] PCI: imx: Add support for i.MX8MQ

2018-11-26 Thread Andrey Smirnov
On Tue, Nov 20, 2018 at 2:49 AM Leonard Crestez wrote: > > On Sat, 2018-11-17 at 10:12 -0800, Andrey Smirnov wrote: > > @@ -921,7 +1004,28 @@ static int imx6_pcie_probe(struct platform_device > > *pdev) > > - case IMX7D: > > + case IMX8MQ: > > +

Re: [PATCH 3/3] PCI: imx: Add support for i.MX8MQ

2018-11-26 Thread Andrey Smirnov
On Sun, Nov 18, 2018 at 11:07 PM Richard Zhu wrote: > > Hi Andrey: > Thanks for your patch-set. > I have comment about the L1SS implementation below. > It's better to figure out one method to fix it. > > BR > Richard > > > -Original Message- > > F

Re: [PATCH 1/1] reset: imx7: Add support for i.MX8MQ

2018-11-26 Thread Andrey Smirnov
ets. > > On Sat, 2018-11-17 at 10:11 -0800, Andrey Smirnov wrote: > > SRC IP block used in i.MX8MQ is a superset of what is found in i.MX7D, > > Is this true, though? > > i.MX7 has SRC_ERCR at offset 0x14 and HSICPHY_RCR at offset 0x1c. > According to documentation, i

[PATCH 2/3] soc: imx: gpcv2: Make regmap access table variant specific.

2018-11-17 Thread Andrey Smirnov
linux-arm-ker...@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov --- drivers/soc/imx/gpcv2.c | 43 + 1 file changed, 22 insertions(+), 21 deletions(-) diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index 08

[PATCH 0/3] GPCv2 support for i.MX8MQ

2018-11-17 Thread Andrey Smirnov
dependencies). However is should be in OK enough shape to get some early feedback on, which is the intent of this submission. All other feedback is appreciated as well! Thank you, Andrey Smirnov [github-v0] https://github.com/ndreys/linux/commits/imx8mq-pcie-v0 Andrey Smirnov (3): soc: imx: gpcv2

[PATCH 3/3] soc: imx: gpcv2: Add support for i.MX8MQ

2018-11-17 Thread Andrey Smirnov
Cc: linux-arm-ker...@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov --- drivers/soc/imx/Kconfig | 4 +- drivers/soc/imx/gpcv2.c | 195 2 files changed, 197 insertions(+), 2 deletions(-) diff --git a/drivers/soc/imx

[PATCH 1/3] PCI: imx: No-op imx6_setup_phy_mpll() on i.MX7D

2018-11-17 Thread Andrey Smirnov
" Cc: Richard Zhu Cc: linux-...@nxp.com Cc: linux-arm-ker...@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-...@vger.kernel.org Signed-off-by: Andrey Smirnov --- drivers/pci/controller/dwc/pci-imx6.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/controller/dwc/

[PATCH 0/3] PCIE support for i.MX8MQ

2018-11-17 Thread Andrey Smirnov
acceptable) solution for the problem. All other feedback is appreciated as well! Thank you, Andrey Smirnov [github-v0] https://github.com/ndreys/linux/commits/imx8mq-pcie-v0 Andrey Smirnov (3): PCI: imx: No-op imx6_setup_phy_mpll() on i.MX7D PCI: imx: No-op imx6_pcie_reset_phy() on i.MX7D P

[PATCH 3/3] PCI: imx: Add support for i.MX8MQ

2018-11-17 Thread Andrey Smirnov
Cc: bhelg...@google.com Cc: Fabio Estevam Cc: cphe...@gmail.com Cc: l.st...@pengutronix.de Cc: Leonard Crestez Cc: "A.s. Dong" Cc: Richard Zhu Cc: linux-...@nxp.com Cc: linux-arm-ker...@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-...@vger.kernel.org Signed-off-

[PATCH 2/3] PCI: imx: No-op imx6_pcie_reset_phy() on i.MX7D

2018-11-17 Thread Andrey Smirnov
" Cc: Richard Zhu Cc: linux-...@nxp.com Cc: linux-arm-ker...@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-...@vger.kernel.org Signed-off-by: Andrey Smirnov --- drivers/pci/controller/dwc/pci-imx6.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/controller/dwc/

[PATCH 1/3] soc: imx: gpcv2: Remove static qualifier from domain_data

2018-11-17 Thread Andrey Smirnov
Cc: Shawn Guo Cc: Fabio Estevam Cc: cphe...@gmail.com Cc: l.st...@pengutronix.de Cc: Leonard Crestez Cc: "A.s. Dong" Cc: Richard Zhu Cc: linux-...@nxp.com Cc: linux-arm-ker...@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov --- drivers/soc/imx/g

[PATCH 1/1] reset: imx7: Add support for i.MX8MQ

2018-11-17 Thread Andrey Smirnov
Cc: linux-...@nxp.com Cc: linux-arm-ker...@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov --- drivers/reset/Kconfig | 2 +- drivers/reset/reset-imx7.c | 66 - include/dt-bindings/reset/imx7-reset.h | 15 +-

[PATCH 0/1] Reset controller support for i.MX8MQ

2018-11-17 Thread Andrey Smirnov
as well! Thank you, Andrey Smirnov [github-v0] https://github.com/ndreys/linux/commits/imx8mq-pcie-v0 Andrey Smirnov (1): reset: imx7: Add support for i.MX8MQ drivers/reset/Kconfig | 2 +- drivers/reset/reset-imx7.c | 66 - include/dt

Re: [PATCH v2] PCI: imx: Add imx6sx suspend/resume support

2018-11-14 Thread Andrey Smirnov
; > + return; Purely optionally, if you feel like avoiding goto you can change this to: default: if (!imx6_pcie->turnoff_reset) { dev_err(dev, "PME_Turn_Off not implemented\n"); return; } reset_control_assert(imx6_pcie->turnoff_res

[PATCH] tools: Add 'firmware' category and add ihex2fw tool

2018-10-17 Thread Andrey Smirnov
h-Hartman Cc: Kyle McMartin Cc: Andrew Morton Cc: Masahiro Yamada Cc: David Woodhouse Cc: Greg Kroah-Hartman Cc: linux-kernel Signed-off-by: Andrey Smirnov --- tools/Makefile | 7 +- tools/firmware/Makefile | 13 ++ tools/firmware/ihex2fw.c | 281 +

Re: Fate of ihex2fw tool

2018-10-17 Thread Andrey Smirnov
On Wed, Oct 17, 2018 at 12:43 AM Greg Kroah-Hartman wrote: > > On Tue, Oct 16, 2018 at 10:36:15PM -0700, Andrey Smirnov wrote: > > Everyone: > > > > Since commit 5620a0d1aacd554ebebcff373e31107bb1ef7769 ("firmware: > > delete in-kernel firmware"): >

Fate of ihex2fw tool

2018-10-16 Thread Andrey Smirnov
e tree it can be found nowadays? Or is there another established tool that can do .ihex -> .fw conversion that is expected to be used instead of ihex2bin? Thanks, Andrey Smirnov

Re: [PATCH v7 4/5] clk: imx: add imx composite clock

2018-09-20 Thread Andrey Smirnov
_RATE_NO_REPARENT | > CLK_OPS_PARENT_ENABLE) > + > +#define imx_clk_composite_critical(name, parent_names, reg) \ > + imx_clk_composite_flags(name, parent_names, ARRAY_SIZE(parent_names), > reg, \ > + CLK_IS_CRITICAL | CLK_SET_RATE_NO_REPARENT | > CLK_OPS_PARENT_ENABLE) Another minor suggestion is to define a intermediary macro and define both imx_clk_composite_critical() and imx_clk_composite() in terms of it. Say: #define __imx_clk_composite(name, parent_names, reg, flags) \ imx_clk_composite_flags(name, parent_names, ARRAY_SIZE(parent_names), reg, \ flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) #define imx_clk_composite(name, parent_names, reg) __imx_clk_composite_flags(name, parent_names, reg, 0) #define imx_clk_composite_critical(name, parent_names, reg) __imx_clk_composite_flags(name, parent_names, reg, CLK_IS_CRITICAL) this way it might be a bit easier to spot that the only difference between the two is CLK_IS_CRITICAL. Thanks, Andrey Smirnov

Re: [PATCH v7 3/5] clk: imx: add SCCG PLL type

2018-09-20 Thread Andrey Smirnov
int retry = 7; > + > + /* Wait for PLL to lock */ > + do { > + if (readl_relaxed(pll->base) & PLL_LOCK_MASK) > + break; > + udelay(10); > + retry--; > + } while (retry); > + Can readx_poll_timeout_atomic() be used here instead? Thanks, Andrey Smirnov

Re: [PATCH v7 2/5] clk: imx: add fractional PLL output clock

2018-09-20 Thread Andrey Smirnov
, divff, divfi, divq; > + u64 temp64; > + > + val = readl_relaxed(pll->base + PLL_CFG0); > + divq = ((val & PLL_OUTPUT_DIV_MASK) + 1) * 2; > + val = readl_relaxed(pll->base + PLL_CFG1); > + divff = (val >> 7) & PLL_FRAC_DIV_MASK; Just as a suggestion you can do: #define PLL_FRAC_DIV GENMASK(30, 7) divff = FIELD_GET(PLL_FRAC_DIV, val) it's a bit nicer (IMHO, of course) because it allows you to avoid having to encode shit and mask separately and mask definition can be easily verified against the datasheet. Thanks, Andrey Smirnov

Re: [PATCH v6 3/5] clk: imx: add SCCG PLL type

2018-09-04 Thread Andrey Smirnov
On Tue, Sep 4, 2018 at 6:13 AM Abel Vesa wrote: > > On Tue, Aug 28, 2018 at 12:11:13PM -0700, Andrey Smirnov wrote: > > On Tue, Aug 28, 2018 at 3:58 AM Abel Vesa wrote: > > > > > > On Fri, Aug 24, 2018 at 09:40:11AM +0200, Sascha Hauer wrote: > > >

Re: [PATCH v6 3/5] clk: imx: add SCCG PLL type

2018-08-28 Thread Andrey Smirnov
On Tue, Aug 28, 2018 at 3:58 AM Abel Vesa wrote: > > On Fri, Aug 24, 2018 at 09:40:11AM +0200, Sascha Hauer wrote: > > +Cc Andrey Smirnov who made me aware of this issue. > > > > On Wed, Aug 22, 2018 at 04:48:21PM +0300, Abel Vesa wrote: > > > From: Lucas Stach

Re: [PATCH v6 3/5] clk: imx: add SCCG PLL type

2018-08-28 Thread Andrey Smirnov
.unprepare = clk_pll1_unprepare, > + .recalc_rate= clk_pll2_recalc_rate, > + .round_rate = clk_pll2_round_rate, > + .set_rate = clk_pll2_set_rate, > +}; > + > +struct clk *imx_clk_sccg_pll(const char *name, > + const char *parent_name, > + void __iomem *base, > + enum imx_sccg_pll_type pll_type) > +{ > + struct clk_sccg_pll *pll; > + struct clk *clk; > + struct clk_init_data init; > + > + pll = kzalloc(sizeof(*pll), GFP_KERNEL); > + if (!pll) > + return ERR_PTR(-ENOMEM); > + > + pll->base = base; > + init.name = name; > + switch (pll_type) { > + case SCCG_PLL1: > + init.ops = _sccg_pll1_ops; > + break; > + case SCCG_PLL2: > + init.ops = _sccg_pll2_ops; > + break; > + } Please add error checking in the switch above since it's pretty clear that a wrong kind of argument can be passed as a pll_type without it being noticeable. Thanks, Andrey Smirnov

Re: [PATCH v6 5/5] clk: imx: add clock driver for i.MX8MQ CCM

2018-08-28 Thread Andrey Smirnov
66m", > "sys2_pll_250m", "sys1_pll_800m", > + "sys2_pll_1000m", > "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", }; > + > +static const char *imx8mq_csi2_phy_sels[] = {"osc_25m", "sys2_pll_125m", > "sys2_pll_100m", "sys1_pll_800m", > +"sys2_pll_1000m", "clk_ext2", > "audio_pll2_out", "video_pll1_out", }; > + > +static const char *imx8mq_csi2_esc_sels[] = {"osc_25m", "sys2_pll_100m", > "sys1_pll_80m", "sys1_pll_800m", > +"sys2_pll_1000m", > "sys3_pll2_out", "clk_ext3", "audio_pll2_out", }; > + > +static const char *imx8mq_pcie2_ctrl_sels[] = {"osc_25m", "sys2_pll_250m", > "sys2_pll_200m", "sys1_pll_266m", > + "sys1_pll_800m", > "sys2_pll_500m", "sys2_pll_333m", "sys3_pll2_out", }; > + > +static const char *imx8mq_pcie2_phy_sels[] = {"osc_25m", "sys2_pll_100m", > "sys2_pll_500m", "clk_ext1", > + "clk_ext2", "clk_ext3", > "clk_ext4", "sys1_pll_400m", }; > + > +static const char *imx8mq_pcie2_aux_sels[] = {"osc_25m", "sys2_pll_200m", > "sys2_pll_50m", "sys3_pll2_out", > + "sys2_pll_100m", > "sys1_pll_80m", "sys1_pll_160m", "sys1_pll_200m", }; > + > +static const char *imx8mq_ecspi3_sels[] = {"osc_25m", "sys2_pll_200m", > "sys1_pll_40m", "sys1_pll_160m", > + "sys1_pll_800m", "sys3_pll2_out", > "sys2_pll_250m", "audio_pll2_out", }; > +static const char *imx8mq_dram_core_sels[] = {"dram_pll_out", > "dram_alt_root", }; > + > +static const char *imx8mq_clko2_sels[] = {"osc_25m", "sys2_pll_200m", > "sys1_pll_400m", "sys2_pll_166m", "audio_pll1_out", > +"video_pll1_out", "ckil", }; > + > +static int const clks_init_on[] __initconst = { > + IMX8MQ_CLK_DRAM_CORE, IMX8MQ_CLK_AHB_CG, > + IMX8MQ_CLK_NOC, IMX8MQ_CLK_NOC_APB, > + IMX8MQ_CLK_USB_BUS, IMX8MQ_CLK_NAND_USDHC_BUS, > + IMX8MQ_CLK_MAIN_AXI, IMX8MQ_CLK_A53_CG, > + IMX8MQ_CLK_AUDIO_AHB_DIV, IMX8MQ_CLK_TMU_ROOT, > + IMX8MQ_CLK_DRAM_APB, > +}; > + > +static struct clk_onecell_data clk_data; > + > +static void __init imx8mq_clocks_init(struct device_node *ccm_node) > +{ > + struct device_node *np; > + void __iomem *base; > + int i; > + > + clks[IMX8MQ_CLK_DUMMY] = imx_clk_fixed("dummy", 0); > + clks[IMX8MQ_CLK_32K] = of_clk_get_by_name(ccm_node, "ckil"); > + clks[IMX8MQ_CLK_25M] = of_clk_get_by_name(ccm_node, "osc_25m"); > + clks[IMX8MQ_CLK_27M] = of_clk_get_by_name(ccm_node, "osc_27m"); > + clks[IMX8MQ_CLK_EXT1] = of_clk_get_by_name(ccm_node, "clk_ext1"); > + clks[IMX8MQ_CLK_EXT2] = of_clk_get_by_name(ccm_node, "clk_ext2"); > + clks[IMX8MQ_CLK_EXT3] = of_clk_get_by_name(ccm_node, "clk_ext3"); > + clks[IMX8MQ_CLK_EXT4] = of_clk_get_by_name(ccm_node, "clk_ext4"); > + > + np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-anatop"); > + base = of_iomap(np, 0); > + WARN_ON(!base); > + > + clks[IMX8MQ_ARM_PLL_REF_SEL] = imx_clk_mux("arm_pll_ref_sel", base + > 0x28, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); > + clks[IMX8MQ_GPU_PLL_REF_SEL] = imx_clk_mux("gpu_pll_ref_sel", base + > 0x18, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); > + clks[IMX8MQ_VPU_PLL_REF_SEL] = imx_clk_mux("vpu_pll_ref_sel", base + > 0x20, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); > + clks[IMX8MQ_AUDIO_PLL1_REF_SEL] = imx_clk_mux("audio_pll1_ref_sel", > base + 0x0, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); > + clks[IMX8MQ_AUDIO_PLL2_REF_SEL] = imx_clk_mux("audio_pll2_ref_sel", > base + 0x8, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); > + clks[IMX8MQ_VIDEO_PLL1_REF_SEL] = imx_clk_mux("video_pll1_ref_sel", > base + 0x10, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); > + clks[IMX8MQ_SYS1_PLL1_REF_SEL] = imx_clk_mux("sys1_pll1_ref_sel", > base + 0x30, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); > + clks[IMX8MQ_SYS2_PLL1_REF_SEL] = imx_clk_mux("sys2_pll1_ref_sel", > base + 0x3c, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); > + clks[IMX8MQ_SYS3_PLL1_REF_SEL] = imx_clk_mux("sys3_pll1_ref_sel", > base + 0x48, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); > + clks[IMX8MQ_DRAM_PLL1_REF_SEL] = imx_clk_mux("dram_pll1_ref_sel", > base + 0x60, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); > + clks[IMX8MQ_VIDEO2_PLL1_REF_SEL] = imx_clk_mux("video2_pll1_ref_sel", > base + 0x54, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); > + > + clks[IMX8MQ_ARM_PLL_REF_DIV]= imx_clk_divider("arm_pll_ref_div", > "arm_pll_ref_sel", base + 0x28, 5, 6); > + clks[IMX8MQ_GPU_PLL_REF_DIV]= imx_clk_divider("gpu_pll_ref_div", > "gpu_pll_ref_sel", base + 0x18, 5, 6); > + clks[IMX8MQ_VPU_PLL_REF_DIV]= imx_clk_divider("vpu_pll_ref_div", > "vpu_pll_ref_sel", base + 0x20, 5, 6); > + clks[IMX8MQ_AUDIO_PLL1_REF_DIV] = > imx_clk_divider("audio_pll1_ref_div", "audio_pll1_ref_sel", base + 0x0, 5, 6); > + clks[IMX8MQ_AUDIO_PLL2_REF_DIV] = > imx_clk_divider("audio_pll2_ref_div", "audio_pll2_ref_sel", base + 0x8, 5, 6); > + clks[IMX8MQ_VIDEO_PLL1_REF_DIV] = > imx_clk_divider("video_pll1_ref_div", "video_pll1_ref_sel", base + 0x10, 5, > 6); > + clks[IMX8MQ_SYS1_PLL1_REF_DIV] = > imx_clk_divider("sys1_pll1_ref_div", "sys1_pll1_ref_sel", base + 0x38, 25, 3); > + clks[IMX8MQ_SYS2_PLL1_REF_DIV] = > imx_clk_divider("sys2_pll1_ref_div", "sys2_pll1_ref_sel", base + 0x44, 25, 3); > + clks[IMX8MQ_SYS3_PLL1_REF_DIV] = > imx_clk_divider("sys3_pll1_ref_div", "sys3_pll1_ref_sel", base + 0x50, 25, 3); > + clks[IMX8MQ_DRAM_PLL1_REF_DIV] = > imx_clk_divider("dram_pll1_ref_div", "dram_pll1_ref_sel", base + 0x68, 25, 3); > + clks[IMX8MQ_VIDEO2_PLL1_REF_DIV] = > imx_clk_divider("video2_pll1_ref_div", "video2_pll1_ref_sel", base + 0x5c, > 25, 3); > + > + clks[IMX8MQ_ARM_PLL] = imx_clk_frac_pll("arm_pll", "arm_pll_ref_div", > base + 0x28); > + clks[IMX8MQ_GPU_PLL] = imx_clk_frac_pll("gpu_pll", "gpu_pll_ref_div", > base + 0x18); > + clks[IMX8MQ_VPU_PLL] = imx_clk_frac_pll("vpu_pll", "vpu_pll_ref_div", > base + 0x20); > + clks[IMX8MQ_AUDIO_PLL1] = imx_clk_frac_pll("audio_pll1", > "audio_pll1_ref_div", base + 0x0); > + clks[IMX8MQ_AUDIO_PLL2] = imx_clk_frac_pll("audio_pll2", > "audio_pll2_ref_div", base + 0x8); > + clks[IMX8MQ_VIDEO_PLL1] = imx_clk_frac_pll("video_pll1", > "video_pll1_ref_div", base + 0x10); > + clks[IMX8MQ_SYS1_PLL1] = imx_clk_sccg_pll("sys1_pll1", > "sys1_pll1_ref_div", base + 0x30, SCCG_PLL1); > + clks[IMX8MQ_SYS2_PLL1] = imx_clk_sccg_pll("sys2_pll1", > "sys2_pll1_ref_div", base + 0x3c, SCCG_PLL1); > + clks[IMX8MQ_SYS3_PLL1] = imx_clk_sccg_pll("sys3_pll1", > "sys3_pll1_ref_div", base + 0x48, SCCG_PLL1); > + clks[IMX8MQ_DRAM_PLL1] = imx_clk_sccg_pll("dram_pll1", > "dram_pll1_ref_div", base + 0x60, SCCG_PLL1); > + clks[IMX8MQ_VIDEO2_PLL1] = imx_clk_sccg_pll("video2_pll1", > "video2_pll1_ref_div", base + 0x5c, 3); This is a bug which will result in a crash once IMX8MQ_VIDEO2_PLL1 is exercised (I know that from having to debug this issue when using this code in Barebox). Last argument should be SCCG_PLL1. Thanks, Andrey Smirnov

Re: [PATCH 2/2] soc: imx: gpcv2: make pgc driver more generic for other i.MX platforms

2018-08-28 Thread Andrey Smirnov
On Tue, Aug 28, 2018 at 12:28 AM Anson Huang wrote: > > > > Anson Huang > Best Regards! > > > > -Original Message----- > > From: Andrey Smirnov > > Sent: Tuesday, August 28, 2018 6:51 AM > > To: Anson Huang > > Cc: Shawn Guo ; Sascha Hauer

Re: [PATCH 2/2] soc: imx: gpcv2: make pgc driver more generic for other i.MX platforms

2018-08-28 Thread Andrey Smirnov
On Mon, Aug 27, 2018 at 7:32 PM Anson Huang wrote: > > Hi, Andrey > > Anson Huang > Best Regards! > > > > -Original Message----- > > From: Andrey Smirnov > > Sent: Tuesday, August 28, 2018 7:04 AM > > To: Anson Huang > > Cc: Shawn Guo ;

Re: [PATCH 2/2] soc: imx: gpcv2: make pgc driver more generic for other i.MX platforms

2018-08-27 Thread Andrey Smirnov
On Mon, Aug 27, 2018 at 3:51 PM Andrey Smirnov wrote: > > On Sun, Aug 5, 2018 at 11:45 PM Anson Huang wrote: > > > > i.MX8MQ and i.MX8MM share same gpc module with i.MX7D, they > > can reuse gpcv2 pgc driver for power domain control, this > > patch renames all funct

Re: [PATCH 1/2] soc: imx: gpc: use A_CORE instread of A7 for more i.MX platforms

2018-08-27 Thread Andrey Smirnov
On Sun, Aug 26, 2018 at 7:14 PM Shawn Guo wrote: > > Andrey, > > Are you fine with these two patches? > I made a small comment on 2/2, but otherwise both patches seem reasonable (Acks provided in separate reply). Let me know if you need anything else from me. Thanks, Andrey Smirnov

Re: [PATCH 1/2] soc: imx: gpc: use A_CORE instread of A7 for more i.MX platforms

2018-08-27 Thread Andrey Smirnov
Looks reasonable to me: Acked-by: Andrey Smirnov > --- > drivers/soc/imx/gpcv2.c | 20 ++-- > 1 file changed, 10 insertions(+), 10 deletions(-) > > diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c > index 6ef18cf..0e31465 100644 > --- a/driv

Re: [PATCH 2/2] soc: imx: gpcv2: make pgc driver more generic for other i.MX platforms

2018-08-27 Thread Andrey Smirnov
evice *pdev) > return ret; > } > > + if (of_machine_is_compatible("fsl,imx7d")) { > + pgc_max_index = ARRAY_SIZE(imx7_pgc_domains); > + imx_pgc_domains = imx7_pgc_domains; > + } Is there any reason to do this explicit call to of_machine_is_compatible() as opposed to passing necessary data via .data in imx_gpcv2_dt_ids[]? The latter seems like a more straightforward way of passing variant specific driver info > + > + if (!imx_pgc_domains) { > + dev_err(>dev, "no device match found\n"); > + return -ENODEV; > + } And doing so would also allow you to drop the check above. Other that this seems like a reasonable change: Acked-by: Andrey Smirnov Thanks, Andrey Smirnov

[PATCH v2 1/2] hid: microsoft: Convert private data to be a proper struct

2018-08-15 Thread Andrey Smirnov
Signed-off-by: Juha Kuikka Signed-off-by: Andrey Smirnov --- drivers/hid/hid-microsoft.c | 25 - 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/hid/hid-microsoft.c b/drivers/hid/hid-microsoft.c index 96e7d3231d2f..f8868d96c0c7 100644 --- a/drivers

[PATCH v2 2/2] hid: microsoft: Add rumble support for Xbox One S controller

2018-08-15 Thread Andrey Smirnov
@vger.kernel.org Cc: Pierre-Loup A. Griffais Signed-off-by: Juha Kuikka Signed-off-by: Andrey Smirnov --- drivers/hid/hid-ids.h | 1 + drivers/hid/hid-microsoft.c | 117 2 files changed, 118 insertions(+) diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h

[PATCH v2 0/2] Rumble support for Xbox One S controller

2018-08-15 Thread Andrey Smirnov
to be packed, magic 4 replaced with MAGNITUDE_NUM, output_report_dmabuf converted to be void * to avoid the need to typecast it. Thanks, Andrey Smirnov [v1] lkml.kernel.org/r/20180810001714.14659-1-andrew.smir...@gmail.com Andrey Smirnov (2): hid: microsoft: Convert private data

Re: [PATCH] hid: microsoft: Add rumble support for Xbox One S controller

2018-08-13 Thread Andrey Smirnov
On Fri, Aug 10, 2018 at 4:38 AM Bastien Nocera wrote: > > On Thu, 2018-08-09 at 17:17 -0700, Andrey Smirnov wrote: > > Add HID quirk driver for Xbox One S controller over bluetooth. > > > > This driver only adds support for rumble. Standard controller > > functiona

Re: [PATCH] hid: microsoft: Add rumble support for Xbox One S controller

2018-08-13 Thread Andrey Smirnov
On Fri, Aug 10, 2018 at 2:37 AM Benjamin Tissoires wrote: > > Hi Andrew, > > On Fri, Aug 10, 2018 at 2:17 AM Andrey Smirnov > wrote: > > > > Add HID quirk driver for Xbox One S controller over bluetooth. > > > > This driver only adds support for rumble

[PATCH] hid: microsoft: Add rumble support for Xbox One S controller

2018-08-09 Thread Andrey Smirnov
@vger.kernel.org Cc: Pierre-Loup A. Griffais Signed-off-by: Juha Kuikka Signed-off-by: Andrey Smirnov --- drivers/hid/Kconfig | 8 ++ drivers/hid/hid-ids.h | 1 + drivers/hid/hid-microsoft.c | 142 ++-- drivers/hid/hid-quirks.c| 1 + 4 files changed

Re: [PATCH v2 1/3] Revert "ARM: dts: imx7d: Invert legacy PCI irq mapping"

2018-07-23 Thread Andrey Smirnov
On Mon, Jul 23, 2018 at 5:41 AM Leonard Crestez wrote: > > On Fri, 2018-07-20 at 08:33 -0700, Andrey Smirnov wrote: > > On Fri, Jul 20, 2018 at 5:48 AM Leonard Crestez > > wrote: > > > > > > This reverts commit 1c86c9dd82f859b474474a7fee0d5195da2c9c

Re: [PATCH v2 1/3] Revert "ARM: dts: imx7d: Invert legacy PCI irq mapping"

2018-07-20 Thread Andrey Smirnov
people from trying to "fix" this in the future. Also, this change is going to break QEMU's mapping found here: https://git.qemu.org/?p=qemu.git;a=blob;f=hw/arm/fsl-imx7.c;h=d5e26855a552e2d52b91f0435a607fae2f88456b;hb=HEAD#l464 any change you are planning to make the change there as well? Thanks, Andrey Smirnov

[PATCH] ARM: dts: vf610-zii-ssmb-spu3: Fix W=1 level warnings

2018-07-19 Thread Andrey Smirnov
Fix a couple of things that were causing warning when building DTB with W=1. Cc: Shawn Guo Cc: Fabio Estevam Cc: cphe...@gmail.com Cc: linux-arm-ker...@lists.infradead.org Cc: devicet...@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov --- arch/arm/boot/dts/vf610

[PATCH v2] ARM: dts: vf610: Add ZII CFU1 board

2018-07-19 Thread Andrey Smirnov
-off-by: Andrey Smirnov --- Changes since [v1]: - Fixed DT warning when compiling with W=1 - Collected Reviewed-by from Fabio [v1] lkml.kernel.org/r/20180719005941.10458-1-andrew.smir...@gmail.com arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/vf610-zii-cfu1.dts | 305

Re: [PATCH] ARM: dts: vf610: Add ZII CFU1 board

2018-07-19 Thread Andrey Smirnov
On Thu, Jul 19, 2018 at 5:45 AM Fabio Estevam wrote: > > Hi Andrey, > > On Wed, Jul 18, 2018 at 9:59 PM, Andrey Smirnov > wrote: > > > +/ { > > + model = "ZII VF610 CFU1 Board"; > > + compatible = "zii,vf610cfu1"

[PATCH] ARM: dts: vf610: Add ZII CFU1 board

2018-07-18 Thread Andrey Smirnov
Add support for the Zodiac Inflight Innovations CFU1 board (VF610-based). Cc: Shawn Guo Cc: Fabio Estevam Cc: cphe...@gmail.com Cc: linux-arm-ker...@lists.infradead.org Cc: devicet...@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrew Lunn Signed-off-by: Andrey Smirnov

Re: [PATCH] ARM: dts: vf610: Add ZII SSMB SPU3 board

2018-07-18 Thread Andrey Smirnov
On Wed, Jul 18, 2018 at 3:50 PM Fabio Estevam wrote: > > Hi Andrey, > > On Tue, Jul 17, 2018 at 1:06 AM, Andrey Smirnov > wrote: > > > +/dts-v1/; > > +#include "vf610.dtsi" > > + > > +/ { > > + model = "ZII VF610 SSMB SPU3

[PATCH v2] spi: spi-fsl-dspi: Fill actual_length when doing DMA transfer

2018-07-16 Thread Andrey Smirnov
'actual_length. Cc: Mark Brown Cc: Sanchayan Maity Cc: Stefan Agner Cc: cphe...@gmail.com Cc: linux-...@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov --- Changes since [v1] - Patch rebase on for-next branch of SPI sybsytem's git tree [v1] lkml.kernel.org/r

Re: [PATCH] spi: spi-fsl-dspi: Fill actual_length when doing DMA transfer

2018-07-16 Thread Andrey Smirnov
On Mon, Jul 16, 2018 at 4:26 AM Mark Brown wrote: > > On Sun, Jul 15, 2018 at 11:25:08PM -0700, Andrey Smirnov wrote: > > Users of SPI device drivers may rely on 'actual_length', so it is > > important that information is correctly reported. One example would be > >

[PATCH] ARM: dts: vf610: Add ZII SSMB SPU3 board

2018-07-16 Thread Andrey Smirnov
Add support for Zodiac Inflight Innovations SSMB SPU3 board (VF610-based). Cc: Shawn Guo Cc: Fabio Estevam Cc: cphe...@gmail.com Cc: linux-arm-ker...@lists.infradead.org Cc: devicet...@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrew Lunn Signed-off-by: Andrey Smirnov

[PATCH] spi: spi-fsl-dspi: Fill actual_length when doing DMA transfer

2018-07-16 Thread Andrey Smirnov
'. Cc: Mark Brown Cc: Sanchayan Maity Cc: Stefan Agner Cc: cphe...@gmail.com Cc: linux-...@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov --- drivers/spi/spi-fsl-dspi.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-fsl

[PATCH v2 0/2] Follow up fixes for SCU3 ESB

2018-07-13 Thread Andrey Smirnov
Shawn: Here's a couple of fixes for things I missed in the [original-submission]. Sorry about the inconvenience. Changes since [v1]: - Reword commit message for patch 2/2 Thanks, Andrey Smirnov [v1] lkml.kernel.org/r/20180712023337.30112-1-andrew.smir...@gmail.com [original-submission

[PATCH v2 2/2] ARM: dts: imx51-zii-scu3-esb: Fix RAVE SP watchdog compatible string

2018-07-13 Thread Andrey Smirnov
...@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Andrew Lunn Signed-off-by: Andrey Smirnov --- arch/arm/boot/dts/imx51-zii-scu3-esb.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts index

[PATCH v2 1/2] ARM: dts: imx51-zii-scu3-esb: Add switch IRQ line pinumx config

2018-07-13 Thread Andrey Smirnov
: Rob Herring Cc: Mark Rutland Cc: linux-arm-ker...@lists.infradead.org Cc: devicet...@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Andrew Lunn Reviewed-by: Andrew Lunn Signed-off-by: Andrey Smirnov --- arch/arm/boot/dts/imx51-zii-scu3-esb.dts | 8 1 file changed, 8 insertions

Re: [PATCH 1/2] ARM: dts: imx51-zii-scu3-esb: Add switch IRQ line pinumx config

2018-07-12 Thread Andrey Smirnov
On Thu, Jul 12, 2018 at 6:37 AM Fabio Estevam wrote: > > Hi Andrey, > > On Wed, Jul 11, 2018 at 11:33 PM, Andrey Smirnov > wrote: > > > + pinctrl_switch: switchgrp { > > + fsl,pins = < > > + MX51_PAD_AUD3_BB_CK_

[PATCH 1/2] ARM: dts: imx51-zii-scu3-esb: Add switch IRQ line pinumx config

2018-07-11 Thread Andrey Smirnov
-kernel@vger.kernel.org Cc: Andrew Lunn Signed-off-by: Andrey Smirnov --- arch/arm/boot/dts/imx51-zii-scu3-esb.dts | 8 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts index 2941a92d40f1..0bb42c00d72b 100644

[PATCH 2/2] ARM: dts: imx51-zii-scu3-esb: Fix RAVE SP watchdog compatible string

2018-07-11 Thread Andrey Smirnov
...@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Andrew Lunn Signed-off-by: Andrey Smirnov --- arch/arm/boot/dts/imx51-zii-scu3-esb.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts index

[PATCH 0/2] Follow up fixes for SCU3 ESB

2018-07-11 Thread Andrey Smirnov
Shawn: Here's a couple of fixes for things I missed in the [original-submission]. Sorry about the inconvenience. Thanks, Andrey Smirnov [original-submission] lkml.kernel.org/r/20180711050704.11492-1-andrew.smir...@gmail.com Andrey Smirnov (2): ARM: dts: imx51-zii-scu3-esb: Add switch IRQ

Re: [PATCH] ARM: dts: imx: Add ZII SCU3 ESB

2018-07-11 Thread Andrey Smirnov
On Wed, Jul 11, 2018 at 7:57 AM Andrew Lunn wrote: > > On Tue, Jul 10, 2018 at 10:07:04PM -0700, Andrey Smirnov wrote: > > + switch@0 { > > + compatible = "marvell,mv88e6085"; > > + reg = <0>; >

[PATCH] ARM: dts: imx: Add ZII SCU3 ESB

2018-07-10 Thread Andrey Smirnov
Cc: linux-kernel@vger.kernel.org Reviewed-by: Fabio Estevam Signed-off-by: Andrey Gusakov Signed-off-by: Andrey Smirnov --- Shawn: Similarly to [mezz] this is a spin-off of SCU3 (AFAIU, original submission incorrectly called it SCU2 ESB) ESB board support originally found in [v0]. Original

[PATCH] ARM: dts: imx: Add ZII SCU2 Mezz board

2018-07-06 Thread Andrey Smirnov
-kernel@vger.kernel.org Reviewed-by: Fabio Estevam Signed-off-by: Andrey Gusakov Signed-off-by: Andrey Smirnov --- Shawn: This is a spin-off of SCU2 Mezz board support originally found in [v0] as per out off-list (Fabio, Chris, Nikita, myself) to add support for ZII hardware fist and worry about

[PATCH 3/6] mfd: rave-sp: Initialize flow control and parity of the port

2018-07-06 Thread Andrey Smirnov
code to explicitly configure both. Cc: linux-kernel@vger.kernel.org Cc: cphe...@gmail.com Cc: Lucas Stach Cc: Nikita Yushchenko Cc: Lee Jones Signed-off-by: Andrey Smirnov --- drivers/mfd/rave-sp.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/mfd/rave-sp.c b/drivers/mfd

[PATCH 2/6] mfd: rave-sp: Fix incorrectly specified checksum type

2018-07-06 Thread Andrey Smirnov
RAVE SP firmware covered by "legacy" variant uses 16-bit CCITT checksum algorithm. Change the code to correctly reflect that. Cc: linux-kernel@vger.kernel.org Cc: cphe...@gmail.com Cc: Lucas Stach Cc: Nikita Yushchenko Cc: Lee Jones Signed-off-by: Andrey Smirnov --- drivers/mfd/rav

[PATCH 6/6] mfd: rave-sp: Emulate CMD_GET_STATUS on device that don't support it

2018-07-06 Thread Andrey Smirnov
@gmail.com Cc: Lucas Stach Cc: Nikita Yushchenko Cc: Lee Jones Signed-off-by: Andrey Smirnov --- drivers/mfd/rave-sp.c | 96 --- 1 file changed, 63 insertions(+), 33 deletions(-) diff --git a/drivers/mfd/rave-sp.c b/drivers/mfd/rave-sp.c index ee

[PATCH 0/6] RAVE SP MFD driver fixes/improvements

2018-07-06 Thread Andrey Smirnov
(not supported by upstream yet). Hopefully all of the changes are straightforward. Let me know if anything needs changing. Thanks, Andrey Smirnov Andrey Smirnov (6): mfd: rave-sp: Remove unused defines mfd: rave-sp: Fix incorrectly specified checksum type mfd: rave-sp: Initialize flow control

[PATCH 5/6] mfd: rave-sp: Add legacy watchdog ping command translation

2018-07-06 Thread Andrey Smirnov
This is needed to make rave-sp-wdt driver to properly ping the watchdog on "legacy" firmware. Cc: linux-kernel@vger.kernel.org Cc: cphe...@gmail.com Cc: Lucas Stach Cc: Nikita Yushchenko Cc: Lee Jones Signed-off-by: Andrey Smirnov --- drivers/mfd/rave-sp.c | 2 ++ 1 file

[PATCH 1/6] mfd: rave-sp: Remove unused defines

2018-07-06 Thread Andrey Smirnov
Remove unusded defines that are a leftover from earlier iterations of the driver. Cc: linux-kernel@vger.kernel.org Cc: cphe...@gmail.com Cc: Lucas Stach Cc: Nikita Yushchenko Cc: Lee Jones Signed-off-by: Andrey Smirnov --- drivers/mfd/rave-sp.c | 10 -- 1 file changed, 10 deletions

[PATCH 4/6] mfd: rave-sp: Add legacy EEPROM access command translation

2018-07-06 Thread Andrey Smirnov
This is needed to make rave-sp-eeprom driver work on "legacy" firmware. Cc: linux-kernel@vger.kernel.org Cc: cphe...@gmail.com Cc: Lucas Stach Cc: Nikita Yushchenko Cc: Lee Jones Signed-off-by: Andrey Smirnov --- drivers/mfd/rave-sp.c | 2 ++ include/linux/mfd/rave-sp.h | 1

Re: [PATCH 1/2] ARM: dts: imx51-babbage: Fix reg for usbh1phy

2018-06-28 Thread Andrey Smirnov
On Thu, Jun 28, 2018 at 6:35 AM Fabio Estevam wrote: > > Hi Andrey, > > On Thu, Jun 28, 2018 at 1:37 AM, Andrey Smirnov > wrote: > > There's already a USB PHY with reg of zero on that bus - usbphy0, used > > by usbotg (included from imx51.dtsi). Move usbh1phy to @1

Re: [PATCH 2/4] ARM: dts: imx6qdl-zii-rdu2: Populate RAVE SP EEPROM nodes

2018-06-27 Thread Andrey Smirnov
On Wed, Jun 27, 2018 at 9:24 PM Andrey Smirnov wrote: > > ZII's RDU1s come with two EEPROMs attached to RAVE SP. Add Ugh, the description should read RDU2, not RDU1. Will fix in v2, tomorrow. Sorry about that. Thanks, Andrey Smirnov > corresponding nodes to make them availible. >

[PATCH 2/2] ARM: dts: imx51-babbage: Make use of pinctrl_usbh1reg

2018-06-27 Thread Andrey Smirnov
Pinctrl_usbh1reg defines pinmux setting for reset GPIO used by usbh1phy, but is not referenced by that node. Fix that. Cc: Fabio Estevam Cc: Shawn Guo Cc: linux-arm-ker...@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov --- arch/arm/boot/dts/imx51

[PATCH 1/2] ARM: dts: imx51-babbage: Fix reg for usbh1phy

2018-06-27 Thread Andrey Smirnov
There's already a USB PHY with reg of zero on that bus - usbphy0, used by usbotg (included from imx51.dtsi). Move usbh1phy to @1 avoid address collision. Cc: Fabio Estevam Cc: Shawn Guo Cc: linux-arm-ker...@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov

[PATCH 3/4] ARM: dts: imx6qdl-zii-rdu2: Populate RAVE SP backlight node

2018-06-27 Thread Andrey Smirnov
...@lists.infradead.org Cc: devicet...@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov --- arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi index

[PATCH 1/4] ARM: dts: imx51-zii-rdu1: Populate RAVE SP EEPROM nodes

2018-06-27 Thread Andrey Smirnov
...@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov --- arch/arm/boot/dts/imx51-zii-rdu1.dts | 29 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts index ad2445dfa91d

[PATCH 4/4] ARM: dts: imx6qdl-zii-rdu2: Populate RAVE SP power button node

2018-06-27 Thread Andrey Smirnov
...@lists.infradead.org Cc: devicet...@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov --- arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi index

[PATCH 2/4] ARM: dts: imx6qdl-zii-rdu2: Populate RAVE SP EEPROM nodes

2018-06-27 Thread Andrey Smirnov
...@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov --- arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi | 18 ++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi index 19a075aee19e

[PATCH 0/4] RDU1/2 latest supported RAVE SP nodes

2018-06-27 Thread Andrey Smirnov
-sp-eeprom.txt Documentation/devicetree/bindings/input/zii,rave-sp-pwrbutton.txt Documentation/devicetree/bindings/leds/backlight/zii,rave-sp-backlight.txt Feedback is welcome! Thanks, Andrey Smirnov Andrey Smirnov (4): ARM: dts: imx51-zii-rdu1: Populate RAVE SP EEPROM nodes ARM: dts

Re: [1/3] ARM: dts: imx51-zii-common: create common include dtsi

2018-06-27 Thread Andrey Smirnov
rge > common logical blocks. Perhaos RDU1 and babbage have more in common - so > what, create a dtsi for them? Nope, that slippery slope doesn't exist at all. We have a clear boundary/decision criteria of common vendor. As I said, let's leave this decision up to the maintainers and avoid continuing having this argument where neither party convinces another. Thanks, Andrey Smirnov

Re: [1/3] ARM: dts: imx51-zii-common: create common include dtsi

2018-06-27 Thread Andrey Smirnov
label = "system:green:status"; > > - linux,default-trigger = "default-on"; > > - }; > > > + sysled3: led3@3 { > > + reg = <3>; > > + label = "system:red:power"; > > + linux,default-trigger = "default-on"; > > + }; > > > + { > > + label = "system:green:status"; > > What for this label games? Same as above. Avoiding unnecessary repetitions. Thanks, Andrey Smirnov

Re: [PATCH] nvmem: rave-sp-eeprom: Remove VLA usage

2018-06-21 Thread Andrey Smirnov
> [1] > https://lkml.kernel.org/r/CA+55aFzCG-zNmZwX4A2FQpadafLfEzK6CC=qpxydaacu1rq...@mail.gmail.com > > Signed-off-by: Kees Cook I completely forgot that I was using VLAs in this driver. Thanks for fixing that! Reviewed-by: Andrey Smirnov Tested-by: Andrey Smirnov > --- > drivers/nvmem

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