uot;
3. MN PMU doesnot support counter overflow IRQ in HiP05/06/07, So
use hrtimer to poll and avoid counter overflow.
Signed-off-by: Shaokun Zhang
Signed-off-by: Dikshit N
Signed-off-by: Anurup M
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_
Add nodes for djtag, L3 cache and MN to support uncore events.
Signed-off-by: Anurup M
---
arch/arm64/boot/dts/hisilicon/hip07.dtsi | 87
1 file changed, 87 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
b/arch/arm64/boot/dts/hisilicon
Add support for Hisilicon SoC hardware event counters
for HiP05/06/07 chip versions.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
MAINTAINERS | 10 ++
1 file changed, 10 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 6d7b7a7..4a95977 100644
--- a/MAINTAINERS
cache hardware events. Each L3 cache banks will
be registered as separate PMU with perf.
5. L3C events will be listed at /sys/devices/hisi_l3cX_Y/events/
6. L3C PMU in HiP05/06/07 does not support counter overflow IRQ. So hrtimer
is used to poll and avoid overflow.
Signed-off-by: Anurup M
Signed
-by: John Garry
Signed-off-by: Anurup M
---
drivers/perf/Makefile | 1 +
drivers/perf/hisilicon/Makefile | 1 +
drivers/perf/hisilicon/djtag.c | 684
drivers/perf/hisilicon/djtag.h | 47 +++
4 files changed, 733 insertions(+)
create mode
Documentation for perf usage and Hisilicon SoC PMU uncore events.
The Hisilicon SOC has event counters for hardware modules like
L3 cache, Miscellaneous node etc. These events are all uncore.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
Documentation/perf/hisi-pmu.txt | 75
Update Kconfig for HiP05/06/07 PMU support.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index 9365190..248d730 100644
--- a
From: Tan Xiaojun
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun
Signed-off-by: Anurup M
Acked-by: Rob Herring
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 51 ++
1 file changed, 51 insertions(+)
create mode 100644
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 29 +++
.../devicetree
hw version.
- use devm_kzalloc.
- Remove DDRC changes in this series. As the DDRC PMU doesnot
depend on djtag it will be send separately.
v1
--
-Initial version with support for L3C, MN and DDRC event counters
-Djtag driver is used to access registers of L3 cache and MN.
Anurup M (6):
arm64
On Friday 31 March 2017 07:53 PM, Mark Rutland wrote:
On Fri, Mar 31, 2017 at 07:43:20PM +0530, Anurup M wrote:
On Thursday 30 March 2017 04:16 PM, Mark Rutland wrote:
+ /*
+* We must NOT create groups containing mixed PMUs, although
+* software events are acceptable
On Thursday 30 March 2017 04:16 PM, Mark Rutland wrote:
+ /*
> >>>+ * We must NOT create groups containing mixed PMUs, although
> >>>+ * software events are acceptable
> >>>+ */
> >>>+ if (event->group_leader->pmu != event->pmu &&
> >>>+ !is_software_event(
On Tuesday 21 March 2017 10:22 PM, Mark Rutland wrote:
+static int hisi_hw_perf_event_init(struct perf_event *event)
>+{
>+ struct hw_perf_event *hwc = &event->hw;
>+ struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
>+ struct device *dev = hisi_pmu->dev;
+
>+ /*
>+* We must NOT
On Friday 24 March 2017 05:06 PM, Mark Rutland wrote:
+#define SC_DJTAG_TIMEOUT_US(100 * USEC_PER_MSEC) /* 100ms */
> >How was this value chosen?
> >
> >How likely is a timeout?
>
>As explained in PATCH 7,
>
>The djtag -EBUSY in hardware is a very rare scenario, and by design
>of hardware
On Friday 24 March 2017 05:13 PM, Mark Rutland wrote:
How do we ensure that we don't take the interrupt in the middle of a
> >sequence of accesses to the HW?
>
>The L3 cache and MN PMU does not use the overflow IRQ and it does
>not occur here
>as the interrupt Mask register is by default maske
On Friday 24 March 2017 05:27 PM, Mark Rutland wrote:
+/* hip05/06 chips L3C bank identifier */
>+static u32 l3c_bankid_map_v1[MAX_BANKS] = {
>+0x02, 0x04, 0x01, 0x08,
>+};
>+
>+/* hip07 chip L3C bank identifier */
>+static u32 l3c_bankid_map_v2[MAX_BANKS] = {
>+0x01, 0x02, 0x03, 0x04,
Thanks for the review.
On Tuesday 21 March 2017 09:21 PM, Mark Rutland wrote:
On Fri, Mar 10, 2017 at 01:28:22AM -0500, Anurup M wrote:
From: Tan Xiaojun
The Hisilicon Djtag is an independent component which connects
with some other components in the SoC by Debug Bus. This driver
can be
On Tuesday 21 March 2017 10:58 PM, Mark Rutland wrote:
On Tue, Mar 21, 2017 at 02:07:42PM +, Mark Rutland wrote:
On Fri, Mar 10, 2017 at 01:27:27AM -0500, Anurup M wrote:
+HiSilicon SoC chip is encapsulated by multiple CPU and IO dies. The CPU die
+is called as Super CPU cluster (SCCL
Thanks for the review.
On Tuesday 21 March 2017 10:22 PM, Mark Rutland wrote:
On Fri, Mar 10, 2017 at 01:28:31AM -0500, Anurup M wrote:
+ * This code is based on the uncore PMU's like arm-cci and
+ * arm-ccn.
Nit: s/PMU's/PMUs/
Ok.
[...]
+struct hisi_l3c_hwcfg {
+ u32
On Tuesday 21 March 2017 10:47 PM, Mark Rutland wrote:
On Fri, Mar 10, 2017 at 01:29:01AM -0500, Anurup M wrote:
When no IRQ is supported in hardware, use hrtimer to poll and
update event counter and avoid overflow condition for MN PMU.
An interval of 8 seconds is used for the hrtimer
On Tuesday 21 March 2017 10:46 PM, Mark Rutland wrote:
On Fri, Mar 10, 2017 at 01:28:45AM -0500, Anurup M wrote:
Add hrtimer support which use poll method to avoid counter overflow
when overflow IRQ is not supported in hardware.
The L3 cache PMU use N-N SPI interrupt which has no support in
Thanks for the review.
On Tuesday 21 March 2017 07:42 PM, Mark Rutland wrote:
Hi,
On Fri, Mar 10, 2017 at 01:27:39AM -0500, Anurup M wrote:
+HiP0x chips are encapsulated by multiple CPU and IO die's. The CPU die is
Nit: that apostrophe shouldn't be there.
Ok. shall recheck
Please have a look at this patch series. Looking forward for any
feedback and comments.
Thanks,
Anurup
On Friday 10 March 2017 11:55 AM, Anurup M wrote:
Provide Support for Hisilicon SoC(HiP05/06/07) Hardware event counters.
The Hisilicon SoC HiP0x series has many uncore or non-CPU
d_req/"
Signed-off-by: Shaokun Zhang
Signed-off-by: Anurup M
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_mn.c | 489
2 files changed, 490 insertions(+), 1 deletion(-)
create mode 100644 drivers/perf/hisilicon/hisi_uncore_
Add nodes for djtag, L3 cache and MN to support uncore events.
Signed-off-by: Anurup M
---
arch/arm64/boot/dts/hisilicon/hip07.dtsi | 79
1 file changed, 79 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
b/arch/arm64/boot/dts/hisilicon
interval of 10 seconds is used for the hrtimer.
Signed-off-by: Dikshit N
Signed-off-by: Anurup M
---
drivers/perf/hisilicon/hisi_uncore_l3c.c | 47 ++
drivers/perf/hisilicon/hisi_uncore_pmu.c | 82
drivers/perf/hisilicon/hisi_uncore_pmu.h | 17
When no IRQ is supported in hardware, use hrtimer to poll and
update event counter and avoid overflow condition for MN PMU.
An interval of 8 seconds is used for the hrtimer.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: Dikshit N
---
drivers/perf/hisilicon
-by: John Garry
Signed-off-by: Anurup M
---
drivers/perf/Makefile | 1 +
drivers/perf/hisilicon/Makefile | 1 +
drivers/perf/hisilicon/djtag.c | 773
drivers/perf/hisilicon/djtag.h | 42 +++
4 files changed, 817 insertions(+)
create mode
cache hardware events. Each L3 cache banks will
be registered as separate PMU with perf.
5. L3C events will be listed at /sys/devices/hisi_l3cX_Y/events/
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers
Update Kconfig for HiP05/06/07 PMU support.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index 1e95d6a..f0aa818 100644
--- a
Documentation for perf usage and Hisilicon SoC PMU uncore events.
The Hisilicon SOC has event counters for hardware modules like
L3 cache, Miscellaneous node etc. These events are all uncore.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
Documentation/perf/hisi-pmu.txt | 76
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Acked-by: Rob Herring
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 25
From: Tan Xiaojun
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun
Signed-off-by: Anurup M
Acked-by: Rob Herring
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 51 ++
1 file changed, 51 insertions(+)
create mode 100644
Add support for Hisilicon SoC hardware event counters
for HiP05/06/07 chip versions.
Signed-off-by: Anurup M
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 6d7b7a7..c2f9806 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5958,6
counters
-Djtag driver is used to access registers of L3 cache and MN.
Anurup M (8):
arm64: MAINTAINERS: hisi: Add hisilicon SoC PMU support
dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU
Documentation: perf: hisi: Documentation for HiP05/06/07 PMU event
counting
On Friday 03 March 2017 12:20 PM, Rob Herring wrote:
On Thu, Mar 02, 2017 at 05:48:36AM -0500, Anurup M wrote:
From: Tan Xiaojun
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun
Signed-off-by: Anurup M
---
.../devicetree/bindings/arm/hisilicon
Documentation for perf usage and Hisilicon SoC PMU uncore events.
The Hisilicon SOC has event counters for hardware modules like
L3 cache, Miscellaneous node etc. These events are all uncore.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
Documentation/perf/hisi-pmu.txt | 76
When no IRQ is supported in hardware, use hrtimer to poll and
update event counter and avoid overflow condition for MN PMU.
An interval of 8 seconds is used for the hrtimer.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: Dikshit N
---
drivers/perf/hisilicon
d_req/"
Signed-off-by: Shaokun Zhang
Signed-off-by: Anurup M
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_mn.c | 489
2 files changed, 490 insertions(+), 1 deletion(-)
create mode 100644 drivers/perf/hisilicon/hisi_uncore_
Add nodes for djtag, L3 cache and MN to support uncore events.
Signed-off-by: Anurup M
---
arch/arm64/boot/dts/hisilicon/hip07.dtsi | 79
1 file changed, 79 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
b/arch/arm64/boot/dts/hisilicon
Add support for Hisilicon SoC hardware event counters
for HiP05/06/07 chip versions.
Signed-off-by: Anurup M
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d662a83..9bb2ddb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5875,6
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 25 +++
.../devicetree
used to access registers of L3 cache and MN.
Anurup M (8):
arm64: MAINTAINERS: hisi: Add hisilicon SoC PMU support
dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU
Documentation: perf: hisi: Documentation for HiP05/06/07 PMU event
counting.
drivers: perf: hisi
interval of 10 seconds is used for the hrtimer.
Signed-off-by: Dikshit N
Signed-off-by: Anurup M
---
drivers/perf/hisilicon/hisi_uncore_l3c.c | 47 ++
drivers/perf/hisilicon/hisi_uncore_pmu.c | 82
drivers/perf/hisilicon/hisi_uncore_pmu.h | 17
cache hardware events. Each L3 cache banks will
be registered as separate PMU with perf.
5. L3C events will be listed at /sys/devices/hisi_l3cX_Y/events/
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers
-by: John Garry
Signed-off-by: Anurup M
---
drivers/perf/Makefile | 1 +
drivers/perf/hisilicon/Makefile | 1 +
drivers/perf/hisilicon/djtag.c | 771
drivers/perf/hisilicon/djtag.h | 40 +++
4 files changed, 813 insertions(+)
create mode
Update Kconfig for HiP05/06/07 PMU support.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index 4d5c5f9..5b988f5 100644
--- a
From: Tan Xiaojun
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun
Signed-off-by: Anurup M
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 51 ++
1 file changed, 51 insertions(+)
create mode 100644 Documentation
On Friday 24 February 2017 08:34 AM, Anurup M wrote:
+static int hisi_mn_init_irqs_fdt(struct device *dev,
+struct hisi_pmu *mn_pmu)
+{
+struct hisi_mn_data *mn_data = mn_pmu->hwmod_data;
+struct hisi_djtag_client *client = mn_data->client;
+int irq = -1, nu
On Tuesday 21 February 2017 05:39 PM, Will Deacon wrote:
On Mon, Feb 20, 2017 at 11:09:43AM +, Mark Rutland wrote:
On Sun, Feb 19, 2017 at 01:51:03PM -0500, Anurup M wrote:
The L3 cache PMU use N-N SPI interrupt which has no support
in kernel mainline.
Could you elaborate on what you
Sorry for delay in reply.
On Tuesday 21 February 2017 05:33 PM, Mark Rutland wrote:
On Tue, Feb 21, 2017 at 05:19:58PM +0530, Anurup M wrote:
On Monday 20 February 2017 04:59 PM, Mark Rutland wrote:
On Sun, Feb 19, 2017 at 01:51:22PM -0500, Anurup M wrote:
+ /* Clear
On Monday 20 February 2017 04:59 PM, Mark Rutland wrote:
Hi,
On Sun, Feb 19, 2017 at 01:51:22PM -0500, Anurup M wrote:
+static irqreturn_t hisi_pmu_mn_isr(int irq, void *dev_id)
+{
+ struct hisi_pmu *mn_pmu = dev_id;
+ struct hisi_mn_data *mn_data = mn_pmu->hwmod_d
Adding Marc.
On Monday 20 February 2017 04:39 PM, Mark Rutland wrote:
On Sun, Feb 19, 2017 at 01:51:03PM -0500, Anurup M wrote:
The L3 cache PMU use N-N SPI interrupt which has no support
in kernel mainline.
Could you elaborate on what you mean by this?
I don't understand what is meant
1. Add nodes for hip07 L3 cache to support uncore events.
2. Add nodes for hip07 support uncore events.
Signed-off-by: Shaokun Zhang
Signed-off-by: Anurup M
---
arch/arm64/boot/dts/hisilicon/hip07.dtsi | 94 ++--
1 file changed, 64 insertions(+), 30 deletions
MN1 support IRQ for counter overflow handling.
MN1 use the index 26 of the Fabric Totem IRQ.
The interrupt parent will be Hisilicon Mbigen-v2.
The interrupt type is LPI.
Signed-off-by: Shaokun Zhang
Signed-off-by: Anurup M
---
drivers/perf/hisilicon/hisi_uncore_mn.c | 121
-by: John Garry
Signed-off-by: Anurup M
---
drivers/perf/Makefile | 1 +
drivers/perf/hisilicon/Makefile | 1 +
drivers/perf/hisilicon/djtag.c | 773
drivers/perf/hisilicon/djtag.h | 40 +++
4 files changed, 815 insertions(+)
create mode
N
Signed-off-by: Anurup M
---
drivers/perf/hisilicon/hisi_uncore_l3c.c | 44 +++
drivers/perf/hisilicon/hisi_uncore_pmu.c | 95
drivers/perf/hisilicon/hisi_uncore_pmu.h | 17 ++
3 files changed, 156 insertions(+)
diff --git a/drivers/perf
Update Kconfig for HiP05/06/07 PMU support.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index 4d5c5f9..5b988f5 100644
--- a
d_req/"
Signed-off-by: Shaokun Zhang
Signed-off-by: Anurup M
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_mn.c | 490
2 files changed, 491 insertions(+), 1 deletion(-)
create mode 100644 drivers/perf/hisilicon/hisi_uncore_
cache hardware events. Each L3 cache banks will
be registered as separate PMU with perf.
5. L3C events will be listed at /sys/devices/hisi_l3cX_Y/events/
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 25 +
.../devicetree
Add support for Hisilicon SoC hardware event counters
for HiP05/06/07 chip versions.
Signed-off-by: Anurup M
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d662a83..9bb2ddb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5875,6
From: Tan Xiaojun
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun
Signed-off-by: Anurup M
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 51 ++
1 file changed, 51 insertions(+)
create mode 100644 Documentation
depend on djtag
hw version.
- use devm_kzalloc.
- Remove DDRC changes in this series. As the DDRC PMU doesnot
depend on djtag it will be send separately.
v1
--
-Initial version with support for L3C, MN and DDRC event counters
-Djtag driver is used to access registers of L3 cache and MN.
Anurup
On Tuesday 10 January 2017 11:13 PM, Mark Rutland wrote:
Hi,
On Mon, Jan 02, 2017 at 01:47:52AM -0500, Anurup M wrote:
ToDo:
1) The counter overflow handling is currently unsupported in this
patch series.
From a quick scan of the patches, I see mention of an interrupt in a
comment the
On Tuesday 10 January 2017 11:25 PM, Mark Rutland wrote:
On Mon, Jan 02, 2017 at 01:49:37AM -0500, Anurup M wrote:
+The Hisilicon SoC HiP05/06/07 chips consist of various independent system
+device PMU's such as L3 cache(L3C) and Miscellaneous Nodes(MN).
+These PMU devices are independen
On Wednesday 04 January 2017 04:29 AM, Rob Herring wrote:
On Mon, Jan 02, 2017 at 01:49:21AM -0500, Anurup M wrote:
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.
Signed-off-by
On Wednesday 04 January 2017 04:26 AM, Rob Herring wrote:
On Mon, Jan 02, 2017 at 01:49:03AM -0500, Anurup M wrote:
From: Tan Xiaojun
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun
Signed-off-by: Anurup M
---
.../devicetree/bindings/arm
1. Add nodes for hip06 L3 cache to support uncore events.
2. Add nodes for hip06 MN to support uncore events.
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
Signed-off-by: Anurup M
---
arch/arm64/boot/dts/hisilicon/hip06.dtsi | 72
1 file changed, 72
CPU
for counting.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
drivers/perf/hisilicon/hisi_uncore_l3c.c | 53
drivers/perf/hisilicon/hisi_uncore_pmu.c | 39 +++
drivers/perf/hisilicon/hisi_uncore_pmu.h | 21 +
3 fil
counting.
5. Add support to count L3 cache hardware events.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_l3c.c | 556 +++
drivers/perf/hisilicon/hisi_uncore_pmu.c | 326
d_req/"
Signed-off-by: Shaokun Zhang
Signed-off-by: Anurup M
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_mn.c | 501
2 files changed, 502 insertions(+), 1 deletion(-)
create mode 100644 drivers/perf/hisilicon/hisi_uncore_
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 25 ++
.../devicetree
Update Kconfig for HiP05/06/07 PMU support.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index 4d5c5f9..2a5435b 100644
--- a
-by: John Garry
Signed-off-by: Anurup M
---
drivers/perf/Makefile | 1 +
drivers/perf/hisilicon/Makefile | 1 +
drivers/perf/hisilicon/djtag.c | 731
drivers/perf/hisilicon/djtag.h | 39 +++
4 files changed, 772 insertions(+)
create mode
Documentation for perf usage and Hisilicon SoC PMU uncore events.
The Hisilicon SOC has event counters for hardware modules like
L3 cache, Miscellaneous node etc. These events are all uncore.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
Documentation/perf/hisi-pmu.txt | 75
From: Tan Xiaojun
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun
Signed-off-by: Anurup M
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 41 ++
1 file changed, 41 insertions(+)
create mode 100644 Documentation
Add support for Hisilicon SoC hardware event counters
for HIP05/06/07 chip versions.
Signed-off-by: Anurup M
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b224caa..fca339e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5725,6
series. As the DDRC PMU doesnot
depend on djtag it will be send separately.
v1
--
-Initial version with support for L3C, MN and DDRC event counters
-Djtag driver is used to access registers of L3 cache and MN.
Anurup M (7):
arm64: MAINTAINERS: hisi: Add hisilicon SoC PMU support
dt-bindings
On Monday 19 December 2016 10:07 PM, Rob Herring wrote:
On Wed, Dec 07, 2016 at 11:55:59AM -0500, Anurup M wrote:
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.
Signed-off-by: Anurup
On Monday 19 December 2016 10:01 PM, Rob Herring wrote:
On Wed, Dec 07, 2016 at 11:55:19AM -0500, Anurup M wrote:
From: Tan Xiaojun
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun
Signed-off-by: Anurup M
---
.../devicetree/bindings/arm
CPU
for counting.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
drivers/perf/hisilicon/hisi_uncore_l3c.c | 57
drivers/perf/hisilicon/hisi_uncore_pmu.c | 40 ++
drivers/perf/hisilicon/hisi_uncore_pmu.h | 21
3 files ch
1. Add nodes for hip06 L3 cache to support uncore events.
2. Add nodes for hip06 MN to support uncore events.
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
Signed-off-by: Anurup M
---
arch/arm64/boot/dts/hisilicon/hip06.dtsi | 78
1 file changed, 78
d_req/"
Signed-off-by: Shaokun Zhang
Signed-off-by: Anurup M
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_mn.c | 516
2 files changed, 517 insertions(+), 1 deletion(-)
create mode 100644 drivers/perf/hisilicon/hisi_uncore_
-by: John Garry
Signed-off-by: Anurup M
---
drivers/perf/Makefile | 1 +
drivers/perf/hisilicon/Makefile | 1 +
drivers/perf/hisilicon/djtag.c | 729
drivers/perf/hisilicon/djtag.h | 39 +++
4 files changed, 770 insertions(+)
create mode
counting.
5. Add support to count L3 cache hardware events.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_l3c.c | 572 +++
drivers/perf
Add support for Hisilicon SoC hardware event counters
for HIP05/06/07 chip versions.
Signed-off-by: Anurup M
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b224caa..ce86c07 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5725,6
Update Kconfig for Hip05/06/07 PMU support.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
Signed-off-by: John Garry
---
drivers/perf/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index 4d5c5f9..2befa55 100644
--- a
Documentation for perf usage and Hisilicon SoC PMU uncore events.
The Hisilicon SOC has event counters for hardware modules like
L3 cache, Miscellaneous node etc. These events are all uncore.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
Documentation/perf/hisi-pmu.txt | 75
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 25 ++
.../devicetree
djtag
hw version.
- use devm_kzalloc.
- Remove DDRC changes in this series. As the DDRC PMU doesnot
depend on djtag it will be send separately.
v1
--
-Initial version with support for L3C, MN and DDRC event counters
-Djtag driver is used to access registers of L3 cache and MN.
Anurup M (7
From: Tan Xiaojun
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun
Signed-off-by: Anurup M
---
.../devicetree/bindings/arm/hisilicon/djtag.txt| 41 ++
1 file changed, 41 insertions(+)
create mode 100644 Documentation
.
Anurup M (7):
arm64: MAINTAINERS: hisi: Add hisilicon SoC PMU support
dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU
Documentation: perf: hisi: Documentation for HIP05/06/07 PMU event
counting.
perf: hisi: Update Kconfig for Hisilicon PMU support
perf: hisi: Add
On Wednesday 09 November 2016 02:36 PM, John Garry wrote:
I'd suggest requiring #address-cells=<1> and #size-cells=<0> in the
master
node, and listing the children by reg property. If the address is not
easily expressed as a single integer, use a larger #address-cells
value.
We already have
On Thursday 10 November 2016 03:10 AM, Arnd Bergmann wrote:
On Wednesday, November 9, 2016 9:58:38 AM CET Anurup M wrote:
I also see that the compatible strings have the version included in
them, and you can probably drop them by requiring them only in the
fallback:
compatible
On Tuesday 08 November 2016 08:40 PM, Arnd Bergmann wrote:
On Tuesday, November 8, 2016 1:49:43 PM CET John Garry wrote:
Hi Arnd,
Thanks for the reference.
I think the i2c interface doesn't fully satisfy our requirements as we
need more than just a slave bus address when accessing the slave
On Tuesday 08 November 2016 08:38 PM, Arnd Bergmann wrote:
On Tuesday, November 8, 2016 7:16:30 PM CET Anurup M wrote:
If these are backwards compatible, just mark them as compatible in DT,
e.g. hip06 can use
compatible = "hisilicon,hip06-cpu-djtag-v1", "hisilicon,hip
On Tuesday 08 November 2016 05:15 PM, Arnd Bergmann wrote:
On Tuesday, November 8, 2016 11:23:35 AM CET John Garry wrote:
On 07/11/2016 20:08, Arnd Bergmann wrote:
On Monday, November 7, 2016 2:15:10 PM CET John Garry wrote:
Hi Arnd,
The new bus type tries to model the djtag in a similar wa
On Tuesday 08 November 2016 05:13 PM, Arnd Bergmann wrote:
On Tuesday, November 8, 2016 1:08:31 PM CET Anurup M wrote:
On Tuesday 08 November 2016 12:32 PM, Tan Xiaojun wrote:
On 2016/11/7 21:26, Arnd Bergmann wrote:
On Wednesday, November 2, 2016 11:42:46 AM CET Anurup M wrote:
From
On Tuesday 08 November 2016 12:32 PM, Tan Xiaojun wrote:
On 2016/11/7 21:26, Arnd Bergmann wrote:
On Wednesday, November 2, 2016 11:42:46 AM CET Anurup M wrote:
From: Tan Xiaojun
The Hisilicon Djtag is an independent component which connects
with some other components in the
1 - 100 of 117 matches
Mail list logo
