Commit-ID: 955d1427a91b18f53e082bd7c19c40ce13b0a0f4
Gitweb: http://git.kernel.org/tip/955d1427a91b18f53e082bd7c19c40ce13b0a0f4
Author: Aravind Gopalakrishnan <aravind.gopalakrish...@amd.com>
AuthorDate: Fri, 8 Jul 2016 11:09:38 +0200
Committer: Ingo Molnar <mi...@kernel.org>
Commit-ID: 955d1427a91b18f53e082bd7c19c40ce13b0a0f4
Gitweb: http://git.kernel.org/tip/955d1427a91b18f53e082bd7c19c40ce13b0a0f4
Author: Aravind Gopalakrishnan
AuthorDate: Fri, 8 Jul 2016 11:09:38 +0200
Committer: Ingo Molnar
CommitDate: Fri, 8 Jul 2016 11:29:25 +0200
x86/mce/AMD
Commit-ID: 6bda529ec42e1cd4dde1c3d0a1a18000ffd3d419
Gitweb: http://git.kernel.org/tip/6bda529ec42e1cd4dde1c3d0a1a18000ffd3d419
Author: Aravind Gopalakrishnan <aravind.gopalakrish...@amd.com>
AuthorDate: Sat, 30 Apr 2016 14:33:52 +0200
Committer: Ingo Molnar <mi...@kernel.org>
Commit-ID: bb91f8c0176b072aeb6b84cfd7e04084025121e0
Gitweb: http://git.kernel.org/tip/bb91f8c0176b072aeb6b84cfd7e04084025121e0
Author: Aravind Gopalakrishnan <aravind.gopalakrish...@amd.com>
AuthorDate: Sat, 30 Apr 2016 14:33:53 +0200
Committer: Ingo Molnar <mi...@kernel.org>
Commit-ID: 10001d91aa0efc793952051f9070a569cc388ebc
Gitweb: http://git.kernel.org/tip/10001d91aa0efc793952051f9070a569cc388ebc
Author: Aravind Gopalakrishnan <aravind.gopalakrish...@amd.com>
AuthorDate: Sat, 30 Apr 2016 14:33:51 +0200
Committer: Ingo Molnar <mi...@kernel.org>
Commit-ID: 6bda529ec42e1cd4dde1c3d0a1a18000ffd3d419
Gitweb: http://git.kernel.org/tip/6bda529ec42e1cd4dde1c3d0a1a18000ffd3d419
Author: Aravind Gopalakrishnan
AuthorDate: Sat, 30 Apr 2016 14:33:52 +0200
Committer: Ingo Molnar
CommitDate: Tue, 3 May 2016 08:24:15 +0200
x86/mce: Grade
Commit-ID: bb91f8c0176b072aeb6b84cfd7e04084025121e0
Gitweb: http://git.kernel.org/tip/bb91f8c0176b072aeb6b84cfd7e04084025121e0
Author: Aravind Gopalakrishnan
AuthorDate: Sat, 30 Apr 2016 14:33:53 +0200
Committer: Ingo Molnar
CommitDate: Tue, 3 May 2016 08:24:16 +0200
x86/mce: Carve
Commit-ID: 10001d91aa0efc793952051f9070a569cc388ebc
Gitweb: http://git.kernel.org/tip/10001d91aa0efc793952051f9070a569cc388ebc
Author: Aravind Gopalakrishnan
AuthorDate: Sat, 30 Apr 2016 14:33:51 +0200
Committer: Ingo Molnar
CommitDate: Tue, 3 May 2016 08:24:15 +0200
x86/mce: Log MCEs
Commit-ID: ea2ca36b658cfc6081ee454e97593c81f646806e
Gitweb: http://git.kernel.org/tip/ea2ca36b658cfc6081ee454e97593c81f646806e
Author: Aravind Gopalakrishnan <aravind.gopalakrish...@amd.com>
AuthorDate: Mon, 7 Mar 2016 14:02:21 +0100
Committer: Ingo Molnar <mi...@kernel.org>
Commit-ID: 8dd1e17a55b0bb1206c71c7a4344c5e3037cdf65
Gitweb: http://git.kernel.org/tip/8dd1e17a55b0bb1206c71c7a4344c5e3037cdf65
Author: Aravind Gopalakrishnan <aravind.gopalakrish...@amd.com>
AuthorDate: Mon, 7 Mar 2016 14:02:19 +0100
Committer: Ingo Molnar <mi...@kernel.org>
Commit-ID: 2cd3b5f9033f0b051842a279dac5a54271cbd3c8
Gitweb: http://git.kernel.org/tip/2cd3b5f9033f0b051842a279dac5a54271cbd3c8
Author: Aravind Gopalakrishnan <aravind.gopalakrish...@amd.com>
AuthorDate: Mon, 7 Mar 2016 14:02:20 +0100
Committer: Ingo Molnar <mi...@kernel.org>
Commit-ID: ea2ca36b658cfc6081ee454e97593c81f646806e
Gitweb: http://git.kernel.org/tip/ea2ca36b658cfc6081ee454e97593c81f646806e
Author: Aravind Gopalakrishnan
AuthorDate: Mon, 7 Mar 2016 14:02:21 +0100
Committer: Ingo Molnar
CommitDate: Tue, 8 Mar 2016 11:48:15 +0100
x86/mce/AMD
Commit-ID: 8dd1e17a55b0bb1206c71c7a4344c5e3037cdf65
Gitweb: http://git.kernel.org/tip/8dd1e17a55b0bb1206c71c7a4344c5e3037cdf65
Author: Aravind Gopalakrishnan
AuthorDate: Mon, 7 Mar 2016 14:02:19 +0100
Committer: Ingo Molnar
CommitDate: Tue, 8 Mar 2016 11:48:14 +0100
x86/mce/AMD: Fix
Commit-ID: 2cd3b5f9033f0b051842a279dac5a54271cbd3c8
Gitweb: http://git.kernel.org/tip/2cd3b5f9033f0b051842a279dac5a54271cbd3c8
Author: Aravind Gopalakrishnan
AuthorDate: Mon, 7 Mar 2016 14:02:20 +0100
Committer: Ingo Molnar
CommitDate: Tue, 8 Mar 2016 11:48:15 +0100
x86/mce: Clarify
Commit-ID: be0aec23bf4624fd55650629fe8df20483487049
Gitweb: http://git.kernel.org/tip/be0aec23bf4624fd55650629fe8df20483487049
Author: Aravind Gopalakrishnan <aravind.gopalakrish...@amd.com>
AuthorDate: Mon, 7 Mar 2016 14:02:18 +0100
Committer: Ingo Molnar <mi...@kernel.org>
Commit-ID: be0aec23bf4624fd55650629fe8df20483487049
Gitweb: http://git.kernel.org/tip/be0aec23bf4624fd55650629fe8df20483487049
Author: Aravind Gopalakrishnan
AuthorDate: Mon, 7 Mar 2016 14:02:18 +0100
Committer: Ingo Molnar
CommitDate: Tue, 8 Mar 2016 11:48:14 +0100
x86/mce/AMD, EDAC
Commit-ID: adc53f2e0ae2fcff10a4b981df14729ffb1482fc
Gitweb: http://git.kernel.org/tip/adc53f2e0ae2fcff10a4b981df14729ffb1482fc
Author: Aravind Gopalakrishnan <aravind.gopalakrish...@amd.com>
AuthorDate: Mon, 7 Mar 2016 14:02:17 +0100
Committer: Ingo Molnar <mi...@kernel.org>
Commit-ID: adc53f2e0ae2fcff10a4b981df14729ffb1482fc
Gitweb: http://git.kernel.org/tip/adc53f2e0ae2fcff10a4b981df14729ffb1482fc
Author: Aravind Gopalakrishnan
AuthorDate: Mon, 7 Mar 2016 14:02:17 +0100
Committer: Ingo Molnar
CommitDate: Tue, 8 Mar 2016 11:48:14 +0100
x86/mce: Move
On 3/3/16 12:45 PM, Borislav Petkov wrote:
Applied, minor stuff corrected and pushed out to
http://git.kernel.org/cgit/linux/kernel/git/bp/bp.git/log/?h=tip-ras
so that the 0day bot can chew on them a little.
Thanks!
-Aravind.
On 3/3/16 12:45 PM, Borislav Petkov wrote:
Applied, minor stuff corrected and pushed out to
http://git.kernel.org/cgit/linux/kernel/git/bp/bp.git/log/?h=tip-ras
so that the 0day bot can chew on them a little.
Thanks!
-Aravind.
Since this is contained to only MCE code, move
the MSR definiton there instead of adding to msr-index
Per discussion here:
http://marc.info/?l=linux-kernel=145633699026474=2
Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrish...@amd.com>
---
arch/x86/include/asm/mce.h
Since this is contained to only MCE code, move
the MSR definiton there instead of adding to msr-index
Per discussion here:
http://marc.info/?l=linux-kernel=145633699026474=2
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/mce.h | 4
arch/x86/include/asm/msr-index.h
In an attempt to aid in understanding of what the threshold_block
structure holds, provide comments to describe the members here.
Also, trim comments around threshold_restart_bank()
and update copyright info.
No functional change is introduced.
Signed-off-by: Aravind Gopalakrishnan
In an attempt to aid in understanding of what the threshold_block
structure holds, provide comments to describe the members here.
Also, trim comments around threshold_restart_bank()
and update copyright info.
No functional change is introduced.
Signed-off-by: Aravind Gopalakrishnan
---
arch
to existing logic for older processors.
Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrish...@amd.com>
---
arch/x86/include/asm/mce.h | 4 ++
arch/x86/kernel/cpu/mcheck/mce_amd.c | 90
2 files changed, 65 insertions(+), 29 deletions(-)
diff
to existing logic for older processors.
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/mce.h | 4 ++
arch/x86/kernel/cpu/mcheck/mce_amd.c | 90
2 files changed, 65 insertions(+), 29 deletions(-)
diff --git a/arch/x86/include/asm/mce.h b
register
to indicate Task context is corrupt.
Add logic here to decode errors from all known IP
blocks for Fam17h Model 00-0fh and to print TCC errors.
Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrish...@amd.com>
---
arch/x86/include/asm/mce.h | 59 +++
arch/x86/
register
to indicate Task context is corrupt.
Add logic here to decode errors from all known IP
blocks for Fam17h Model 00-0fh and to print TCC errors.
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/mce.h | 59 +++
arch/x86/kernel/cpu/mcheck/mce_amd.c | 30
suggestions)
- Incorporated all changes as suggested by Boris from here-
- http://marc.info/?l=linux-kernel=145691594921586=2
- http://marc.info/?l=linux-kernel=145691606221610=2
- http://marc.info/?l=linux-kernel=145691610421627=2
- No functional change is introduced
Aravind
Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrish...@amd.com>
---
arch/x86/include/asm/mce.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 0681d0a..b016219 100644
--- a/arch/x86/include/asm/mce.h
+++ b/ar
suggestions)
- Incorporated all changes as suggested by Boris from here-
- http://marc.info/?l=linux-kernel=145691594921586=2
- http://marc.info/?l=linux-kernel=145691606221610=2
- http://marc.info/?l=linux-kernel=145691610421627=2
- No functional change is introduced
Aravind
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/mce.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 0681d0a..b016219 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -40,7
On 3/2/2016 10:38 AM, Borislav Petkov wrote:
But you can take the three here, merge them again into a single patch
and do the changes ontot.
I made them into three to show you more easily what should be changed.
Ok, I'll just spin a V3 of the entire patchset with all your suggested
On 3/2/2016 10:38 AM, Borislav Petkov wrote:
But you can take the three here, merge them again into a single patch
and do the changes ontot.
I made them into three to show you more easily what should be changed.
Ok, I'll just spin a V3 of the entire patchset with all your suggested
On 3/2/2016 10:21 AM, Borislav Petkov wrote:
On Wed, Mar 02, 2016 at 09:52:23AM -0600, Aravind Gopalakrishnan wrote:
So, I think we should continue this approach and have something like this-
static const char * const amd_core_mcablock_names[] = {
[SMCA_LS] = "load_
On 3/2/2016 10:21 AM, Borislav Petkov wrote:
On Wed, Mar 02, 2016 at 09:52:23AM -0600, Aravind Gopalakrishnan wrote:
So, I think we should continue this approach and have something like this-
static const char * const amd_core_mcablock_names[] = {
[SMCA_LS] = "load_
semble the rest of this file,
while at it and do some minor stylistic changes.
Signed-off-by: Borislav Petkov <b...@suse.de>
Looks good. Thanks.
Reviewed-by: Aravind Gopalakrishnan<aravind.gopalakrish...@amd.com>
-
default:
printk(KERN_WARNING "Huh? What fam
of this file,
while at it and do some minor stylistic changes.
Signed-off-by: Borislav Petkov
Looks good. Thanks.
Reviewed-by: Aravind Gopalakrishnan
-
default:
printk(KERN_WARNING "Huh? What family is it: 0x%x?!\n", c->x86);
-
On 3/2/2016 4:50 AM, Borislav Petkov wrote:
Ok, applied with a bunch of changes ontop.
Thanks!
The second patch is relying on the assumption that a
hwid of 0 is invalid. Is that so?
Yes, HWID of 0 is invalid.
Thanks,
-Aravind.
On 3/2/2016 4:50 AM, Borislav Petkov wrote:
Ok, applied with a bunch of changes ontop.
Thanks!
The second patch is relying on the assumption that a
hwid of 0 is invalid. Is that so?
Yes, HWID of 0 is invalid.
Thanks,
-Aravind.
On 3/2/2016 4:53 AM, Borislav Petkov wrote:
Merge all IP blocks into a single enum. This allows for easier block
name use later. Drop superfluous "_BLOCK" from the enum names.
Signed-off-by: Borislav Petkov <b...@suse.de>
Cc: Aravind Gopalakrishnan <aravind.gopalakrish.
On 3/2/2016 4:53 AM, Borislav Petkov wrote:
Merge all IP blocks into a single enum. This allows for easier block
name use later. Drop superfluous "_BLOCK" from the enum names.
Signed-off-by: Borislav Petkov
Cc: Aravind Gopalakrishnan
enum amd_ip_types {
- SMCA_F17H_CORE
Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrish...@amd.com>
---
arch/x86/include/asm/mce.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 69f8bda..3b45e36 100644
--- a/arch/x86/include/asm/mce.h
+++ b/ar
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/mce.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 69f8bda..3b45e36 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -40,7
register
to indicate Task context is corrupt.
Add logic here to decode errors from all known IP
blocks for Fam17h Model 00-0fh and to print TCC errors.
Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrish...@amd.com>
---
arch/x86/include/asm/mce.h | 53 ++
arch/x86/
to existing logic for older processors.
Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrish...@amd.com>
---
arch/x86/include/asm/mce.h | 4 ++
arch/x86/kernel/cpu/mcheck/mce_amd.c | 90
2 files changed, 65 insertions(+), 29 deletions(-)
diff
register
to indicate Task context is corrupt.
Add logic here to decode errors from all known IP
blocks for Fam17h Model 00-0fh and to print TCC errors.
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/mce.h | 53 ++
arch/x86/kernel/cpu/mcheck/mce_amd.c | 11
to existing logic for older processors.
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/mce.h | 4 ++
arch/x86/kernel/cpu/mcheck/mce_amd.c | 90
2 files changed, 65 insertions(+), 29 deletions(-)
diff --git a/arch/x86/include/asm/mce.h b
In an attempt to aid in understand of what threshold_block
structure holds, assing comments to describe the members here.
Also, trimming comments around threshold_restart_bank()
and updating copyright info.
No functional change is introduced.
Signed-off-by: Aravind Gopalakrishnan
In an attempt to aid in understand of what threshold_block
structure holds, assing comments to describe the members here.
Also, trimming comments around threshold_restart_bank()
and updating copyright info.
No functional change is introduced.
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86
the code
Aravind Gopalakrishnan (5):
x86/mce: Move MCx_CONFIG MSR definition
EDAC, MCE, AMD: Enable error decoding of Scalable MCA errors
x86/mce/AMD: Fix logic to obtain block address
x86/mce: Clarify comments regarding deferred error
x86/mce/AMD: Add comments for easier understanding
arch
the code
Aravind Gopalakrishnan (5):
x86/mce: Move MCx_CONFIG MSR definition
EDAC, MCE, AMD: Enable error decoding of Scalable MCA errors
x86/mce/AMD: Fix logic to obtain block address
x86/mce: Clarify comments regarding deferred error
x86/mce/AMD: Add comments for easier understanding
arch
Since this is contained to only MCE code, move
the MSR definiton there instead of adding to msr-index
Per discussion here:
http://marc.info/?l=linux-kernel=145633699026474=2
Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrish...@amd.com>
---
arch/x86/include/asm/mce.h
Since this is contained to only MCE code, move
the MSR definiton there instead of adding to msr-index
Per discussion here:
http://marc.info/?l=linux-kernel=145633699026474=2
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/mce.h | 4
arch/x86/include/asm/msr-index.h
On 2/26/2016 11:44 AM, Borislav Petkov wrote:
threshold_restart_bank() reprograms the MISC MSR after sanity-checking
the fields supplied for that MSR. store_threshold_limit() sets the error
count, store_interrupt_enable() enables/disables the interrupt and both
call threshold_restart_bank() to
On 2/26/2016 11:44 AM, Borislav Petkov wrote:
threshold_restart_bank() reprograms the MISC MSR after sanity-checking
the fields supplied for that MSR. store_threshold_limit() sets the error
count, store_interrupt_enable() enables/disables the interrupt and both
call threshold_restart_bank() to
On 2/23/2016 6:35 AM, Borislav Petkov wrote:
On Tue, Feb 16, 2016 at 03:45:11PM -0600, Aravind Gopalakrishnan wrote:
/*
+ * Set the error_count and interrupt_enable sysfs attributes here.
+ * This function gets called during the init phase and when someone
+ * makes changes to either
On 2/23/2016 6:35 AM, Borislav Petkov wrote:
On Tue, Feb 16, 2016 at 03:45:11PM -0600, Aravind Gopalakrishnan wrote:
/*
+ * Set the error_count and interrupt_enable sysfs attributes here.
+ * This function gets called during the init phase and when someone
+ * makes changes to either
On 2/24/2016 5:37 AM, Borislav Petkov wrote:
On Tue, Feb 23, 2016 at 05:02:40PM -0600, Aravind Gopalakrishnan wrote:
On 2/23/16 6:11 AM, Borislav Petkov wrote:
On Tue, Feb 16, 2016 at 03:45:10PM -0600, Aravind Gopalakrishnan wrote:
/* AMD-specific bits */
-#define MCI_STATUS_DEFERRED
On 2/24/2016 5:37 AM, Borislav Petkov wrote:
On Tue, Feb 23, 2016 at 05:02:40PM -0600, Aravind Gopalakrishnan wrote:
On 2/23/16 6:11 AM, Borislav Petkov wrote:
On Tue, Feb 16, 2016 at 03:45:10PM -0600, Aravind Gopalakrishnan wrote:
/* AMD-specific bits */
-#define MCI_STATUS_DEFERRED
On 2/24/2016 5:33 AM, Borislav Petkov wrote:
On Tue, Feb 23, 2016 at 04:56:38PM -0600, Aravind Gopalakrishnan wrote:
I think MSR_AMD64_SMCA_MC0_MISC0 would be required in mce.c as well.
So might be better to retain it here.
Actually, I'm thinking, these all are - even if used in multiple files
On 2/24/2016 5:33 AM, Borislav Petkov wrote:
On Tue, Feb 23, 2016 at 04:56:38PM -0600, Aravind Gopalakrishnan wrote:
I think MSR_AMD64_SMCA_MC0_MISC0 would be required in mce.c as well.
So might be better to retain it here.
Actually, I'm thinking, these all are - even if used in multiple files
On 2/24/2016 5:28 AM, Borislav Petkov wrote:
On Tue, Feb 23, 2016 at 04:50:37PM -0600, Aravind Gopalakrishnan wrote:
Sorry about that. Looks like this pair is not defined in spelling.txt. So,
might be worth adding there as well?
Oh geez, we have a spelling.txt! I think we can declare
On 2/24/2016 5:28 AM, Borislav Petkov wrote:
On Tue, Feb 23, 2016 at 04:50:37PM -0600, Aravind Gopalakrishnan wrote:
Sorry about that. Looks like this pair is not defined in spelling.txt. So,
might be worth adding there as well?
Oh geez, we have a spelling.txt! I think we can declare
On 2/23/16 6:37 AM, Borislav Petkov wrote:
On Tue, Feb 16, 2016 at 03:45:08PM -0600, Aravind Gopalakrishnan wrote:
/* AMD-specific bits */
#define MCI_STATUS_DEFERRED (1ULL<<44) /* declare an uncorrected error */
#define MCI_STATUS_POISON (1ULL<<43) /* access po
On 2/23/16 6:37 AM, Borislav Petkov wrote:
On Tue, Feb 16, 2016 at 03:45:08PM -0600, Aravind Gopalakrishnan wrote:
/* AMD-specific bits */
#define MCI_STATUS_DEFERRED (1ULL<<44) /* declare an uncorrected error */
#define MCI_STATUS_POISON (1ULL<<43) /* access po
On 2/23/16 6:11 AM, Borislav Petkov wrote:
On Tue, Feb 16, 2016 at 03:45:10PM -0600, Aravind Gopalakrishnan wrote:
/* AMD-specific bits */
-#define MCI_STATUS_DEFERRED(1ULL<<44) /* declare an uncorrected error */
+#define MCI_STATUS_DEFERRED(1ULL<<44) /* declare a de
On 2/23/16 6:11 AM, Borislav Petkov wrote:
On Tue, Feb 16, 2016 at 03:45:10PM -0600, Aravind Gopalakrishnan wrote:
/* AMD-specific bits */
-#define MCI_STATUS_DEFERRED(1ULL<<44) /* declare an uncorrected error */
+#define MCI_STATUS_DEFERRED(1ULL<<44) /* declare a de
On 2/23/16 6:39 AM, Borislav Petkov wrote:
On Tue, Feb 16, 2016 at 03:45:09PM -0600, Aravind Gopalakrishnan wrote:
/* 'SMCA': AMD64 Scalable MCA */
+#define MSR_AMD64_SMCA_MC0_MISC0 0xc0002003
#define MSR_AMD64_SMCA_MC0_CONFIG 0xc0002004
#define MSR_AMD64_SMCA_MC0_IPID
On 2/23/16 6:39 AM, Borislav Petkov wrote:
On Tue, Feb 16, 2016 at 03:45:09PM -0600, Aravind Gopalakrishnan wrote:
/* 'SMCA': AMD64 Scalable MCA */
+#define MSR_AMD64_SMCA_MC0_MISC0 0xc0002003
#define MSR_AMD64_SMCA_MC0_CONFIG 0xc0002004
#define MSR_AMD64_SMCA_MC0_IPID
On 2/16/2016 3:45 PM, Aravind Gopalakrishnan wrote:
In upcoming processors, the BLKPTR field is no longer used
to indicate the MSR number of the additional register.
Insted, it simply indicates the prescence of additional MSRs.
Fixing the logic here to gather MSR address from
On 2/16/2016 3:45 PM, Aravind Gopalakrishnan wrote:
In upcoming processors, the BLKPTR field is no longer used
to indicate the MSR number of the additional register.
Insted, it simply indicates the prescence of additional MSRs.
Fixing the logic here to gather MSR address from
to existing logic for older processors.
Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrish...@amd.com>
---
arch/x86/include/asm/msr-index.h | 4 ++
arch/x86/kernel/cpu/mcheck/mce_amd.c | 94 +---
2 files changed, 69 insertions(+), 29 deletions(-)
diff
to existing logic for older processors.
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/msr-index.h | 4 ++
arch/x86/kernel/cpu/mcheck/mce_amd.c | 94 +---
2 files changed, 69 insertions(+), 29 deletions(-)
diff --git a/arch/x86/include/asm/msr-index.h
In an attempt to help folks not very familiar with the code to
understand what the code is doing, adding a bit of helper
comments around some more important functions in the driver
to describe them.
No functional change is introduced.
Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakr
In an attempt to help folks not very familiar with the code to
understand what the code is doing, adding a bit of helper
comments around some more important functions in the driver
to describe them.
No functional change is introduced.
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/kernel
register
to indicate Task context is corrupt.
Add logic here to decode errors from all known IP
blocks for Fam17h Model 00-0fh and to print TCC errors.
Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrish...@amd.com>
---
arch/x86/include/asm/mce.h | 50 ++
arch/x86/i
register
to indicate Task context is corrupt.
Add logic here to decode errors from all known IP
blocks for Fam17h Model 00-0fh and to print TCC errors.
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/mce.h | 50 ++
arch/x86/include/asm/msr-index.h | 2 +
arch
functionality
Tested the patches for regressions on Fam15h, Fam10h systems
and found none.
Aravind Gopalakrishnan (4):
EDAC, MCE, AMD: Enable error decoding of Scalable MCA errors
x86/mce/AMD: Fix logic to obtain block address
x86/mce: Clarify comments regarding deferred error
x86/mce/AMD
functionality
Tested the patches for regressions on Fam15h, Fam10h systems
and found none.
Aravind Gopalakrishnan (4):
EDAC, MCE, AMD: Enable error decoding of Scalable MCA errors
x86/mce/AMD: Fix logic to obtain block address
x86/mce: Clarify comments regarding deferred error
x86/mce/AMD
Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrish...@amd.com>
---
arch/x86/include/asm/mce.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 2ec67ac..476da8b 100644
--- a/arch/x86/include/asm/mce.h
+++ b/ar
Signed-off-by: Aravind Gopalakrishnan
---
arch/x86/include/asm/mce.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 2ec67ac..476da8b 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -40,7
Commit-ID: e6c8f1873be8a14c7e44202df1f7e6ea61bf3352
Gitweb: http://git.kernel.org/tip/e6c8f1873be8a14c7e44202df1f7e6ea61bf3352
Author: Aravind Gopalakrishnan
AuthorDate: Mon, 25 Jan 2016 20:41:53 +0100
Committer: Ingo Molnar
CommitDate: Mon, 1 Feb 2016 10:53:59 +0100
x86/mce/AMD: Set
Commit-ID: f57a1f3c14b9182f1fea667f5a38a1094699db7c
Gitweb: http://git.kernel.org/tip/f57a1f3c14b9182f1fea667f5a38a1094699db7c
Author: Aravind Gopalakrishnan
AuthorDate: Mon, 25 Jan 2016 20:41:51 +0100
Committer: Ingo Molnar
CommitDate: Mon, 1 Feb 2016 10:53:57 +0100
x86/mce/AMD: Fix
Commit-ID: 60f116fca162d9488f783f5014779463243ab7a2
Gitweb: http://git.kernel.org/tip/60f116fca162d9488f783f5014779463243ab7a2
Author: Aravind Gopalakrishnan
AuthorDate: Mon, 25 Jan 2016 20:41:50 +0100
Committer: Ingo Molnar
CommitDate: Mon, 1 Feb 2016 10:53:57 +0100
x86/mce/AMD
Commit-ID: 284b965c146f482b4a411133f62288d52b7e3a72
Gitweb: http://git.kernel.org/tip/284b965c146f482b4a411133f62288d52b7e3a72
Author: Aravind Gopalakrishnan
AuthorDate: Mon, 25 Jan 2016 20:41:49 +0100
Committer: Ingo Molnar
CommitDate: Mon, 1 Feb 2016 10:53:56 +0100
x86/mce/AMD: Do
Commit-ID: bfbe0eeb769e2aff2cb1fc6845c4e4b7eac40bb3
Gitweb: http://git.kernel.org/tip/bfbe0eeb769e2aff2cb1fc6845c4e4b7eac40bb3
Author: Aravind Gopalakrishnan
AuthorDate: Mon, 25 Jan 2016 20:41:48 +0100
Committer: Ingo Molnar
CommitDate: Mon, 1 Feb 2016 10:53:55 +0100
x86/mce: Fix
Commit-ID: bfbe0eeb769e2aff2cb1fc6845c4e4b7eac40bb3
Gitweb: http://git.kernel.org/tip/bfbe0eeb769e2aff2cb1fc6845c4e4b7eac40bb3
Author: Aravind Gopalakrishnan <aravind.gopalakrish...@amd.com>
AuthorDate: Mon, 25 Jan 2016 20:41:48 +0100
Committer: Ingo Molnar <mi...@kernel.org>
Commit-ID: 60f116fca162d9488f783f5014779463243ab7a2
Gitweb: http://git.kernel.org/tip/60f116fca162d9488f783f5014779463243ab7a2
Author: Aravind Gopalakrishnan <aravind.gopalakrish...@amd.com>
AuthorDate: Mon, 25 Jan 2016 20:41:50 +0100
Committer: Ingo Molnar <mi...@kernel.org>
Commit-ID: 284b965c146f482b4a411133f62288d52b7e3a72
Gitweb: http://git.kernel.org/tip/284b965c146f482b4a411133f62288d52b7e3a72
Author: Aravind Gopalakrishnan <aravind.gopalakrish...@amd.com>
AuthorDate: Mon, 25 Jan 2016 20:41:49 +0100
Committer: Ingo Molnar <mi...@kernel.org>
Commit-ID: f57a1f3c14b9182f1fea667f5a38a1094699db7c
Gitweb: http://git.kernel.org/tip/f57a1f3c14b9182f1fea667f5a38a1094699db7c
Author: Aravind Gopalakrishnan <aravind.gopalakrish...@amd.com>
AuthorDate: Mon, 25 Jan 2016 20:41:51 +0100
Committer: Ingo Molnar <mi...@kernel.org>
Commit-ID: e6c8f1873be8a14c7e44202df1f7e6ea61bf3352
Gitweb: http://git.kernel.org/tip/e6c8f1873be8a14c7e44202df1f7e6ea61bf3352
Author: Aravind Gopalakrishnan <aravind.gopalakrish...@amd.com>
AuthorDate: Mon, 25 Jan 2016 20:41:53 +0100
Committer: Ingo Molnar <mi...@kernel.org>
On 1/21/2016 6:32 AM, Borislav Petkov wrote:
On Wed, Jan 20, 2016 at 12:54:51PM +0300, Dan Carpenter wrote:
+ u64 dct_sel_base_off= (u64)(pvt->dct_sel_hi & 0xFC00) << 16;
@Aravind: do you have a box with
setpci -s 18.2 0x114.l
bits [31:16] not 0?
Nope. I don't see it set
On 1/21/2016 6:32 AM, Borislav Petkov wrote:
On Wed, Jan 20, 2016 at 12:54:51PM +0300, Dan Carpenter wrote:
+ u64 dct_sel_base_off= (u64)(pvt->dct_sel_hi & 0xFC00) << 16;
@Aravind: do you have a box with
setpci -s 18.2 0x114.l
bits [31:16] not 0?
Nope. I don't see it set
Commit-ID: 3849e91f571dcb48cf2c8143480c59137d44d6bc
Gitweb: http://git.kernel.org/tip/3849e91f571dcb48cf2c8143480c59137d44d6bc
Author: Aravind Gopalakrishnan
AuthorDate: Wed, 4 Nov 2015 12:49:42 +0100
Committer: Thomas Gleixner
CommitDate: Sat, 7 Nov 2015 10:37:51 +0100
x86/AMD: Fix
Commit-ID: 3849e91f571dcb48cf2c8143480c59137d44d6bc
Gitweb: http://git.kernel.org/tip/3849e91f571dcb48cf2c8143480c59137d44d6bc
Author: Aravind Gopalakrishnan <aravind.gopalakrish...@amd.com>
AuthorDate: Wed, 4 Nov 2015 12:49:42 +0100
Committer: Thomas Gleixner <t...@linu
Commit-ID: e5e84a26ef2909964d964224b805236293fb4c63
Gitweb: http://git.kernel.org/tip/e5e84a26ef2909964d964224b805236293fb4c63
Author: Aravind Gopalakrishnan
AuthorDate: Wed, 4 Nov 2015 12:49:42 +0100
Committer: Thomas Gleixner
CommitDate: Wed, 4 Nov 2015 12:52:06 +0100
x86/AMD: Fix
Commit-ID: e5e84a26ef2909964d964224b805236293fb4c63
Gitweb: http://git.kernel.org/tip/e5e84a26ef2909964d964224b805236293fb4c63
Author: Aravind Gopalakrishnan <aravind.gopalakrish...@amd.com>
AuthorDate: Wed, 4 Nov 2015 12:49:42 +0100
Committer: Thomas Gleixner <t...@linu
-off-by: Aravind Gopalakrishnan
---
Changes in V2:
- Move LLC calculation logic to amd_detect_cmp() and change patch
header as a result. (This in turn fixes the issue found by
kbuild bot on the V1 patch)
arch/x86/kernel/cpu/amd.c | 13 +
1 file changed, 13 insertions(+)
diff
On 11/3/2015 1:52 PM, Borislav Petkov wrote:
On Tue, Nov 03, 2015 at 01:41:53PM -0600, Aravind Gopalakrishnan wrote:
cpu_llc_id references should be wrapped under #ifdef CONFIG_SMP.
Did that and kernel build worked with the attached config.
Will send a V2 with the fix.
Why aren't you doing
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