Re: [PATCH 2/4] RISC-V: Support per-hart timebase-frequency

2018-12-07 Thread Atish Patra
. Signed-off-by: Atish Patra --- arch/riscv/kernel/time.c | 9 + drivers/clocksource/riscv_timer.c | 22 ++ 2 files changed, 23 insertions(+), 8 deletions(-) diff --git a/arch/riscv/kernel/time.c b/arch/riscv/kernel/time.c index 1911c8f6..225fe743 100644

Re: [PATCH 4/4] RISC-V: Fix non-smp kernel boot on SMP systems

2018-12-07 Thread Atish Patra
if hartid is invalid. Take this opprtunity to print appropriate error strings for different failure cases. Signed-off-by: Atish Patra --- drivers/clocksource/riscv_timer.c | 13 ++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/clocksource/riscv_timer.c b/drivers

[PATCH 3/4] RISC-V: Remove per cpu clocksource

2018-12-03 Thread Atish Patra
There is only one clocksource in RISC-V. The boot cpu initializes that clocksource. No need to keep a percpu data structure. Signed-off-by: Atish Patra --- drivers/clocksource/riscv_timer.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/clocksource

[PATCH 2/4] RISC-V: Support per-hart timebase-frequency

2018-12-03 Thread Atish Patra
Follow the updated DT specs and read the timebase-frequency from the boot cpu. Keep the old DT reading as well for backward compatibility. This patch is rework of old patch from Palmer. Signed-off-by: Atish Patra --- arch/riscv/kernel/time.c | 9 + drivers/clocksource

[PATCH 1/4] dt-bindings: Correct RISC-V's timebase-frequency

2018-12-03 Thread Atish Patra
From: Palmer Dabbelt Someone must have read the device tree specification incorrectly, because we were putting timebase-frequency in the wrong place. This corrects the issue, moving it from / { cpus { timebase-frequency = X; } } to / { cpus {

[PATCH 4/4] RISC-V: Fix non-smp kernel boot on SMP systems

2018-12-03 Thread Atish Patra
-by: Atish Patra --- drivers/clocksource/riscv_timer.c | 13 ++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/clocksource/riscv_timer.c b/drivers/clocksource/riscv_timer.c index 39de6e49..4af4af47 100644 --- a/drivers/clocksource/riscv_timer.c +++ b/drivers

[PATCH 0/4] Timer code cleanup.

2018-12-03 Thread Atish Patra
This patch series provides an assorted timer cleanups in RISC-V. Atish Patra (3): RISC-V: Support per-hart timebase-frequency RISC-V: Remove per cpu clocksource RISC-V: Fix non-smp kernel boot on SMP systems Palmer Dabbelt (1): dt-bindings: Correct RISC-V's timebase-frequency Documentation

Re: [RFT PATCH v1 2/4] dt-binding: cpu-topology: Move cpu-map to a common binding.

2018-12-03 Thread Atish Patra
On 12/3/18 9:33 AM, Sudeep Holla wrote: On Mon, Dec 03, 2018 at 09:23:42AM -0800, Atish Patra wrote: On 12/3/18 8:55 AM, Sudeep Holla wrote: On Thu, Nov 29, 2018 at 03:28:18PM -0800, Atish Patra wrote: cpu-map binding can be used to described cpu topology for both RISC-V & ARM. It makes

Re: [RFT PATCH v1 3/4] cpu-topology: Move cpu topology code to common code.

2018-12-03 Thread Atish Patra
On 12/3/18 9:16 AM, Sudeep Holla wrote: On Thu, Nov 29, 2018 at 03:28:19PM -0800, Atish Patra wrote: Both RISC-V & ARM64 are using cpu-map device tree to describe their cpu topology. It's better to move the relevant code to a common place instead of duplicate code. Signed-off-by: Atish P

Re: [RFT PATCH v1 2/4] dt-binding: cpu-topology: Move cpu-map to a common binding.

2018-12-03 Thread Atish Patra
On 12/3/18 8:55 AM, Sudeep Holla wrote: On Thu, Nov 29, 2018 at 03:28:18PM -0800, Atish Patra wrote: cpu-map binding can be used to described cpu topology for both RISC-V & ARM. It makes more sense to move the binding to document to a common place. The relevant discussion can be found

Re: [PATCH v2 4/4] irqchip: sifive-plic: Implement irq_set_affinity() for SMP host

2018-11-29 Thread Atish Patra
On 11/29/18 9:59 PM, Atish Patra wrote: On 11/27/18 2:04 AM, Anup Patel wrote: Currently on SMP host, all CPUs take external interrupts routed via PLIC. All CPUs will try to claim a given external interrupt but only one of them will succeed while other CPUs would simply resume whatever

Re: [PATCH v2 4/4] irqchip: sifive-plic: Implement irq_set_affinity() for SMP host

2018-11-29 Thread Atish Patra
On 11/27/18 2:04 AM, Anup Patel wrote: Currently on SMP host, all CPUs take external interrupts routed via PLIC. All CPUs will try to claim a given external interrupt but only one of them will succeed while other CPUs would simply resume whatever they were doing before. This means if we have N

Re: [PATCH v2 3/4] irqchip: sifive-plic: Differentiate between PLIC handler and context

2018-11-29 Thread Atish Patra
On 11/27/18 2:04 AM, Anup Patel wrote: We explicitly differentiate between PLIC handler and context because PLIC context is for given mode of HART whereas PLIC handler is per-CPU software construct meant for handling interrupts from a particular PLIC context. Signed-off-by: Anup Patel ---

Re: [PATCH v2 2/4] irqchip: sifive-plic: More flexible plic_irq_toggle()

2018-11-29 Thread Atish Patra
On 11/27/18 2:03 AM, Anup Patel wrote: We make plic_irq_toggle() more generic so that we can enable/disable hwirq for given cpumask. This generic plic_irq_toggle() will be eventually used to implement set_affinity for PLIC driver. Signed-off-by: Anup Patel ---

Re: [PATCH v2 1/4] irqchip: sifive-plic: Pre-compute context hart base and enable base

2018-11-29 Thread Atish Patra
On 11/27/18 2:03 AM, Anup Patel wrote: This patch does following optimizations: 1. Pre-compute hart base for each context handler 2. Pre-compute enable base for each context handler 3. Have enable lock for each context handler instead of global plic_toggle_lock Signed-off-by: Anup Patel ---

[RFT PATCH v1 2/4] dt-binding: cpu-topology: Move cpu-map to a common binding.

2018-11-29 Thread Atish Patra
cpu-map binding can be used to described cpu topology for both RISC-V & ARM. It makes more sense to move the binding to document to a common place. The relevant discussion can be found here. https://lkml.org/lkml/2018/11/6/19 Signed-off-by: Atish Patra --- .../{arm/topology.txt =>

[RFT PATCH v1 1/4] Documentation: DT: arm: add support for sockets defining package boundaries

2018-11-29 Thread Atish Patra
From: Sudeep Holla The current ARM DT topology description provides the operating system with a topological view of the system that is based on leaf nodes representing either cores or threads (in an SMT system) and a hierarchical set of cluster nodes that creates a hierarchical topology view of

[RFT PATCH v1 3/4] cpu-topology: Move cpu topology code to common code.

2018-11-29 Thread Atish Patra
Both RISC-V & ARM64 are using cpu-map device tree to describe their cpu topology. It's better to move the relevant code to a common place instead of duplicate code. Signed-off-by: Atish Patra --- arch/arm64/include/asm/topology.h | 22 --- arch/arm64/kernel/topology.c |

[RFT PATCH v1 4/4] RISC-V: Parse cpu topology during boot.

2018-11-29 Thread Atish Patra
/sys/devices/system/cpu/cpu3/topology/physical_package_id 0 $cat /sys/devices/system/cpu/cpu3/topology/core_id 3 Signed-off-by: Atish Patra --- arch/riscv/Kconfig | 1 + arch/riscv/kernel/smpboot.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv

[RFT PATCH v1 0/4] Unify CPU topology across ARM64 & RISC-V

2018-11-29 Thread Atish Patra
qemu/tree/cpu_topo Apologies for the previous patch series with incorrect title and was sent only to kernel mailing list due to a bug in my config. Please ignore that. Atish Patra (3): dt-binding: cpu-topology: Move cpu-map to a common binding. cpu-topology: Move cpu topology code to common code. RI

[RFT PATCH 1/4] Documentation: DT: arm: add support for sockets defining package boundaries

2018-11-29 Thread Atish Patra
From: Sudeep Holla The current ARM DT topology description provides the operating system with a topological view of the system that is based on leaf nodes representing either cores or threads (in an SMT system) and a hierarchical set of cluster nodes that creates a hierarchical topology view of

[RFT PATCH 0/4] Unify CPU topology across ARM64 & RISC-V

2018-11-29 Thread Atish Patra
qemu/tree/cpu_topo Atish Patra (3): dt-binding: cpu-topology: Move cpu-map to a common binding. cpu-topology: Move cpu topology code to common code. RISC-V: Parse cpu topology during boot. Sudeep Holla (1): Documentation: DT: arm: add support for sockets defining package boundaries .../{arm/topology

[RFT PATCH 2/4] dt-binding: cpu-topology: Move cpu-map to a common binding.

2018-11-29 Thread Atish Patra
cpu-map binding can be used to described cpu topology for both RISC-V & ARM. It makes more sense to move the binding to document to a common place. The relevant discussion can be found here. https://lkml.org/lkml/2018/11/6/19 Signed-off-by: Atish Patra --- .../{arm/topology.txt =>

[RFT PATCH 3/4] cpu-topology: Move cpu topology code to common code.

2018-11-29 Thread Atish Patra
Both RISC-V & ARM64 are using cpu-map device tree to describe their cpu topology. It's better to move the relevant code to a common place instead of duplicate code. Signed-off-by: Atish Patra --- arch/arm64/include/asm/topology.h | 22 --- arch/arm64/kernel/topology.c |

[RFT PATCH 4/4] RISC-V: Parse cpu topology during boot.

2018-11-29 Thread Atish Patra
/sys/devices/system/cpu/cpu3/topology/physical_package_id 0 $cat /sys/devices/system/cpu/cpu3/topology/core_id 3 Signed-off-by: Atish Patra --- arch/riscv/Kconfig | 1 + arch/riscv/kernel/smpboot.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv

Re: [PATCH] dt-bindings: sifive: describe sifive-blocks versioning

2018-11-21 Thread Atish Patra
On 11/21/18 5:07 PM, Paul Walmsley wrote: For IP blocks that are generated from the public, open-source sifive-blocks repository, describe the version numbering policy that its maintainers intend to use, upon request from Rob Herring . Cc: Rob Herring Cc: Palmer Dabbelt Cc: Megan Wachs Cc:

[PATCH] RISC-V: Fix of_node_* refcount

2018-11-20 Thread Atish Patra
Fix of_node* refcount at various places by using of_node_put. Signed-off-by: Atish Patra --- arch/riscv/kernel/cacheinfo.c | 11 +++ arch/riscv/kernel/cpu.c| 1 + arch/riscv/kernel/cpufeature.c | 2 ++ arch/riscv/kernel/perf_event.c | 1 + arch/riscv/kernel/smpboot.c| 6

Re: [RFC PATCH] Documentation: DT: arm: add support for sockets defining package boundaries

2018-11-19 Thread Atish Patra
On 11/12/18 3:37 PM, Rob Herring wrote: On Wed, Nov 07, 2018 at 05:13:44PM +, Sudeep Holla wrote: The current ARM DT topology description provides the operating system with a topological view of the system that is based on leaf nodes representing either cores or threads (in an SMT system)

Re: [RFC 1/3] dt-binding: cpu-topology: Move cpu-map to a common binding.

2018-11-19 Thread Atish Patra
On 11/17/18 8:33 AM, Rob Herring wrote: On Thu, Nov 08, 2018 at 05:50:07PM -0800, Atish Patra wrote: cpu-map binding can be used to described cpu topology for both RISC-V & ARM. It makes more sense to move the binding to document to a common place. The relevant discussion can be found

Re: [RFC 0/3] Unify CPU topology across ARM64 & RISC-V

2018-11-19 Thread Atish Patra
On 11/15/18 10:31 AM, Jeffrey Hugo wrote: On 11/8/2018 6:50 PM, Atish Patra wrote: The cpu-map DT entry in ARM64 can describe the CPU topology in much better way compared to other existing approaches. RISC-V can easily adopt this binding to represent it's own CPU topology. Thus, both cpu-map DT

[RFC 3/3] RISC-V: Parse cpu topology during boot.

2018-11-08 Thread Atish Patra
/sys/devices/system/cpu/cpu3/topology/physical_package_id 0 $cat /sys/devices/system/cpu/cpu3/topology/core_id 3 Signed-off-by: Atish Patra --- arch/riscv/Kconfig | 1 + arch/riscv/kernel/smpboot.c | 6 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/riscv

[RFC 0/3] Unify CPU topology across ARM64 & RISC-V

2018-11-08 Thread Atish Patra
. The patches have been tested for RISC-V and compile tested for ARM64. The socket changes[2] can be merged on top of this series or vice versa. [1] https://lkml.org/lkml/2018/11/6/19 [2] https://lkml.org/lkml/2018/11/7/918 Atish Patra (3): dt-binding: cpu-topology: Move cpu-map to a common

[RFC 1/3] dt-binding: cpu-topology: Move cpu-map to a common binding.

2018-11-08 Thread Atish Patra
cpu-map binding can be used to described cpu topology for both RISC-V & ARM. It makes more sense to move the binding to document to a common place. The relevant discussion can be found here. https://lkml.org/lkml/2018/11/6/19 Signed-off-by: Atish Patra --- Documentation/devicetree/bindings

[RFC 2/3] cpu-topology: Move cpu topology code to common code.

2018-11-08 Thread Atish Patra
Both RISC-V & ARM64 are using cpu-map device tree to describe their cpu topology. It's better to move the relevant code to a common place instead of duplicate code. No functional changes done. Signed-off-by: Atish Patra --- arch/arm64/include/asm/topology.h | 23 +-- arch/arm64/ke

Re: [RFC 1/2] dt-bindings: topology: Add RISC-V cpu topology.

2018-11-05 Thread Atish Patra
On 11/5/18 12:11 PM, Rob Herring wrote: On Mon, Nov 5, 2018 at 1:39 PM Palmer Dabbelt wrote: On Fri, 02 Nov 2018 06:09:39 PDT (-0700), robh...@kernel.org wrote: On Thu, Nov 1, 2018 at 6:04 PM Atish Patra wrote: Define a RISC-V cpu topology. This is based on cpu-map in ARM world

Re: [RFC 0/2] Add RISC-V cpu topology

2018-11-02 Thread Atish Patra
On 11/2/18 11:59 AM, Nick Kossifidis wrote: Hello All, Στις 2018-11-02 01:04, Atish Patra έγραψε: This patch series adds the cpu topology for RISC-V. It contains both the DT binding and actual source code. It has been tested on QEMU & Unleashed board. The idea is based on cpu-map in

Re: [RFC 1/2] dt-bindings: topology: Add RISC-V cpu topology.

2018-11-02 Thread Atish Patra
On 11/2/18 8:50 AM, Sudeep Holla wrote: On Fri, Nov 02, 2018 at 10:11:38AM -0500, Rob Herring wrote: On Fri, Nov 2, 2018 at 8:31 AM Sudeep Holla wrote: On Fri, Nov 02, 2018 at 08:09:39AM -0500, Rob Herring wrote: On Thu, Nov 1, 2018 at 6:04 PM Atish Patra wrote: Define a RISC-V cpu

Re: [RFC 1/2] dt-bindings: topology: Add RISC-V cpu topology.

2018-11-02 Thread Atish Patra
On 11/2/18 6:09 AM, Rob Herring wrote: On Thu, Nov 1, 2018 at 6:04 PM Atish Patra wrote: Define a RISC-V cpu topology. This is based on cpu-map in ARM world. But it doesn't need a separate thread node for defining SMT systems. Multiple cpu phandle properties can be parsed to identify

[RFC 0/2] Add RISC-V cpu topology

2018-11-01 Thread Atish Patra
as I feel it provides a very clear way of defining the topology compared to parsing cache nodes to figure out which cpus share the same package or core. I am open to any other idea to implement cpu-topology as well. Atish Patra (2): dt-bindings: topology: Add RISC-V cpu topology. RISC-V: Intro

[RFC 2/2] RISC-V: Introduce cpu topology.

2018-11-01 Thread Atish Patra
r applying the patch. $cat /sys/devices/system/cpu/cpu2/topology/core_siblings_list 0-3 $cat /sys/devices/system/cpu/cpu3/topology/core_siblings_list 0-3 $cat /sys/devices/system/cpu/cpu3/topology/physical_package_id 0 $cat /sys/devices/system/cpu/cpu3/topology/core_id 3 Signed-off-by: Atish Patra

[RFC 1/2] dt-bindings: topology: Add RISC-V cpu topology.

2018-11-01 Thread Atish Patra
is a better word choice than cluster for RISC-V. Signed-off-by: Atish Patra --- .../devicetree/bindings/riscv/topology.txt | 154 + 1 file changed, 154 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/topology.txt diff --git a/Documentation/devicetree

Re: [RFC 1/4] pwm: sifive: Add DT documentation for SiFive PWM Controller.

2018-10-17 Thread Atish Patra
On 10/17/18 8:58 AM, Rob Herring wrote: On Tue, Oct 16, 2018 at 03:20:34PM -0700, Atish Patra wrote: On 10/16/18 3:04 PM, Thierry Reding wrote: On Tue, Oct 16, 2018 at 10:31:42AM -0700, Paul Walmsley wrote: On 10/16/18 4:01 AM, Thierry Reding wrote: On Mon, Oct 15, 2018 at 03:57:35PM -0700

Re: [RFC 4/4] gpio: sifive: Add GPIO driver for SiFive SoCs

2018-10-16 Thread Atish Patra
On 10/10/18 5:35 AM, Linus Walleij wrote: Hi Atish, thanks for your patch! On Tue, Oct 9, 2018 at 8:51 PM Atish Patra wrote: From: "Wesley W. Terpstra" Adds the GPIO driver for SiFive RISC-V SoCs. Signed-off-by: Wesley W. Terpstra [Atish: Various fixes and code cleanup]

Re: [RFC 1/4] pwm: sifive: Add DT documentation for SiFive PWM Controller.

2018-10-16 Thread Atish Patra
On 10/16/18 3:51 AM, Thierry Reding wrote: On Mon, Oct 15, 2018 at 03:45:46PM -0700, Atish Patra wrote: On 10/10/18 6:51 AM, Thierry Reding wrote: On Tue, Oct 09, 2018 at 11:51:22AM -0700, Atish Patra wrote: [...] +- interrupts: one interrupt per PWM channel (currently unused in the driver

Re: [RFC 1/4] pwm: sifive: Add DT documentation for SiFive PWM Controller.

2018-10-16 Thread Atish Patra
On 10/16/18 3:04 PM, Thierry Reding wrote: On Tue, Oct 16, 2018 at 10:31:42AM -0700, Paul Walmsley wrote: On 10/16/18 4:01 AM, Thierry Reding wrote: On Mon, Oct 15, 2018 at 03:57:35PM -0700, Atish Patra wrote: On 10/10/18 6:49 AM, Thierry Reding wrote: On Tue, Oct 09, 2018 at 11:51:22AM

Re: [RFC 2/4] pwm: sifive: Add a driver for SiFive SoC PWM

2018-10-16 Thread Atish Patra
On 10/10/18 6:11 AM, Christoph Hellwig wrote: Thanks for getting these drivers submitted upstream! I don't really know anything about PWM, so just some random nitpicking below.. + iowrite32(frac, pwm->regs + REG_PWMCMP0 + (dev->hwpwm * SIZE_PWMCMP)); * already has a higher precedence

Re: [RFC 2/4] pwm: sifive: Add a driver for SiFive SoC PWM

2018-10-16 Thread Atish Patra
On 10/10/18 7:13 AM, Thierry Reding wrote: On Tue, Oct 09, 2018 at 11:51:23AM -0700, Atish Patra wrote: From: "Wesley W. Terpstra" Adds a PWM driver for PWM chip present in SiFive's HiFive Unleashed SoC. Signed-off-by: Wesley W. Terpstra [Atish: Various fixes and code cleanup]

Re: [RFC 1/4] pwm: sifive: Add DT documentation for SiFive PWM Controller.

2018-10-15 Thread Atish Patra
On 10/10/18 6:49 AM, Thierry Reding wrote: On Tue, Oct 09, 2018 at 11:51:22AM -0700, Atish Patra wrote: From: "Wesley W. Terpstra" DT documentation for PWM controller added with updated compatible string. Signed-off-by: Wesley W. Terpstra [Atish: Compatible string update]

Re: [RFC 1/4] pwm: sifive: Add DT documentation for SiFive PWM Controller.

2018-10-15 Thread Atish Patra
On 10/10/18 6:51 AM, Thierry Reding wrote: On Tue, Oct 09, 2018 at 11:51:22AM -0700, Atish Patra wrote: [...] +- interrupts: one interrupt per PWM channel (currently unused in the driver) This should probably say what the interrupt is used for. And once you have that, remove the comment about

[RFC 1/4] pwm: sifive: Add DT documentation for SiFive PWM Controller.

2018-10-09 Thread Atish Patra
From: "Wesley W. Terpstra" DT documentation for PWM controller added with updated compatible string. Signed-off-by: Wesley W. Terpstra [Atish: Compatible string update] Signed-off-by: Atish Patra --- .../devicetree/bindings/pwm/pwm-sifive.txt | 32

[RFC 4/4] gpio: sifive: Add GPIO driver for SiFive SoCs

2018-10-09 Thread Atish Patra
From: "Wesley W. Terpstra" Adds the GPIO driver for SiFive RISC-V SoCs. Signed-off-by: Wesley W. Terpstra [Atish: Various fixes and code cleanup] Signed-off-by: Atish Patra --- drivers/gpio/Kconfig | 7 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-sifi

[RFC 3/4] gpio: sifive: Add DT documentation for SiFive GPIO.

2018-10-09 Thread Atish Patra
From: "Wesley W. Terpstra" DT documentation for GPIO added with updated compatible string. Signed-off-by: Wesley W. Terpstra [Atish: Compatible string update] Signed-off-by: Atish Patra --- .../devicetree/bindings/gpio/gpio-sifive.txt | 28 ++ 1 file c

[RFC 2/4] pwm: sifive: Add a driver for SiFive SoC PWM

2018-10-09 Thread Atish Patra
From: "Wesley W. Terpstra" Adds a PWM driver for PWM chip present in SiFive's HiFive Unleashed SoC. Signed-off-by: Wesley W. Terpstra [Atish: Various fixes and code cleanup] Signed-off-by: Atish Patra --- drivers/pwm/Kconfig | 10 ++ drivers/pwm/Makefile | 1 + drive

[RFC 0/4] GPIO & PWM support for HiFive Unleashed

2018-10-09 Thread Atish Patra
This patch series adds GPIO & PWM drivers and DT documentation for HiFive Unleashed board. The patches are mostly based on Wesley's patch. Wesley W. Terpstra (4): pwm: sifive: Add DT documentation for SiFive PWM Controller. pwm: sifive: Add a driver for SiFive SoC PWM gpio: sifive: Add DT

Re: [PATCH v3] RISC-V: Show IPI stats

2018-10-02 Thread Atish Patra
On 10/1/18 8:29 PM, Anup Patel wrote: On Tue, Oct 2, 2018 at 8:45 AM Atish Patra wrote: On 9/28/18 11:26 PM, Anup Patel wrote: This patch provides arch_show_interrupts() implementation to show IPI stats via /proc/interrupts. Now the contents of /proc/interrupts" will look like

Re: [PATCH v3] RISC-V: Show IPI stats

2018-10-02 Thread Atish Patra
On 10/1/18 9:42 AM, Palmer Dabbelt wrote: On Fri, 28 Sep 2018 23:26:05 PDT (-0700), a...@brainfault.org wrote: This patch provides arch_show_interrupts() implementation to show IPI stats via /proc/interrupts. Now the contents of /proc/interrupts" will look like below: CPU0

[PATCH v6 03/14] RISC-V: Filter ISA and MMU values in cpuinfo

2018-10-02 Thread Atish Patra
-by: Atish Patra Reviewed-by: Christoph Hellwig --- arch/riscv/kernel/cpu.c | 68 - 1 file changed, 61 insertions(+), 7 deletions(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index ca6c81e5..1c0bf662 100644 --- a/arch/riscv

[PATCH v6 00/14] SMP cleanup and new features

2018-10-02 Thread Atish Patra
No need to pass scause as arg to do_IRQ() RISC-V: Show CPU ID and Hart ID separately in /proc/cpuinfo RISC-V: Show IPI stats Atish Patra (4): RISC-V: Disable preemption before enabling interrupts RISC-V: Use WRITE_ONCE instead of direct access RISC-V: Add logical CPU indexing for RISC-V R

[PATCH v6 02/14] RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}

2018-10-02 Thread Atish Patra
From: Palmer Dabbelt These are just hard coded in the RISC-V port, which doesn't make any sense. We should probably be setting these from device tree entries when they exist, but for now I think it's saner to just leave them all as their default values. Signed-off-by: Palmer Dabbelt

[PATCH v6 04/14] RISC-V: Comment on the TLB flush in smp_callin()

2018-10-02 Thread Atish Patra
From: Palmer Dabbelt This isn't readily apparent from reading the code. Signed-off-by: Palmer Dabbelt [Atish: code comment formatting update] Signed-off-by: Atish Patra Reviewed-by: Christoph Hellwig --- arch/riscv/kernel/smpboot.c | 4 1 file changed, 4 insertions(+) diff --git

[PATCH v6 13/14] RISC-V: Show CPU ID and Hart ID separately in /proc/cpuinfo

2018-10-02 Thread Atish Patra
mmu : sv48 Signed-off-by: Anup Patel Signed-off-by: Atish Patra --- arch/riscv/kernel/cpu.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 6f61..3a5a2ee3 100644 --- a/arch/riscv/kernel/cpu.c

[PATCH v6 07/14] RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid

2018-10-02 Thread Atish Patra
Dabbelt [Atish: code comment formatting update] Signed-off-by: Atish Patra Reviewed-by: Christoph Hellwig --- arch/riscv/include/asm/processor.h | 2 +- arch/riscv/kernel/cpu.c| 7 +-- arch/riscv/kernel/smpboot.c| 2 +- drivers/clocksource/riscv_timer.c | 2 +- drivers

[PATCH v6 08/14] RISC-V: Rename im_okay_therefore_i_am to found_boot_cpu

2018-10-02 Thread Atish Patra
From: Palmer Dabbelt The old name was a bit odd. Signed-off-by: Palmer Dabbelt Signed-off-by: Atish Patra Reviewed-by: Christoph Hellwig --- arch/riscv/kernel/smpboot.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv

[PATCH v6 01/14] RISC-V: No need to pass scause as arg to do_IRQ()

2018-10-02 Thread Atish Patra
From: Anup Patel The scause is already part of pt_regs so no need to pass scause as separate arg to do_IRQ(). Reviewed-by: Christoph Hellwig Signed-off-by: Anup Patel --- arch/riscv/kernel/entry.S | 1 - arch/riscv/kernel/irq.c | 4 ++-- 2 files changed, 2 insertions(+), 3 deletions(-)

[PATCH v6 09/14] RISC-V: Use mmgrab()

2018-10-02 Thread Atish Patra
From: Palmer Dabbelt commit f1f1007644ff ("mm: add new mmgrab() helper") added a helper that we missed out on. Signed-off-by: Palmer Dabbelt Reviewed-by: Christoph Hellwig Signed-off-by: Atish Patra --- arch/riscv/kernel/smpboot.c | 3 ++- 1 file changed, 2 insertions(+),

[PATCH v6 11/14] RISC-V: Add logical CPU indexing for RISC-V

2018-10-02 Thread Atish Patra
these two. Always mark the boot processor as CPU0 and all other CPUs get the logical CPU id based on their booting order. Signed-off-by: Atish Patra Reviewed-by: Anup Patel Reviewed-by: Christoph Hellwig --- arch/riscv/include/asm/smp.h | 24 +++- arch/riscv/kernel/setup.c

[PATCH v6 14/14] RISC-V: Show IPI stats

2018-10-02 Thread Atish Patra
d-off-by: Atish Patra Reviewed-by: Palmer Dabbelt Changes since v2: - Remove use of IPI_CALL_WAKEUP because it's being removed Changes since v1: - Add stub inline show_ipi_stats() function for !CONFIG_SMP - Make ipi_names[] dynamically sized at compile time - Minor beautification of ipi_

[PATCH v6 10/14] RISC-V: Use WRITE_ONCE instead of direct access

2018-10-02 Thread Atish Patra
The secondary harts spin on couple of per cpu variables until both of these are non-zero so it's not necessary to have any ordering here. However, WRITE_ONCE should be used to avoid tearing. Signed-off-by: Atish Patra Reviewed-by: Christoph Hellwig --- arch/riscv/kernel/smpboot.c | 5 +++-- 1

[PATCH v6 05/14] RISC-V: Disable preemption before enabling interrupts

2018-10-02 Thread Atish Patra
Currently, irq is enabled before preemption disabling happens. If the scheduler fired right here and cpu is scheduled then it may blow up. Signed-off-by: Palmer Dabbelt [Atish: Commit text and code comment formatting update] Signed-off-by: Atish Patra Reviewed-by: Christoph Hellwig --- arch

[PATCH v6 12/14] RISC-V: Use Linux logical CPU number instead of hartid

2018-10-02 Thread Atish Patra
Setup the cpu_logical_map during boot. Moreover, every SBI call and PLIC context are based on the physical hartid. Use the logical CPU to hartid mapping to pass correct hartid to respective functions. Signed-off-by: Atish Patra Reviewed-by: Anup Patel Reviewed-by: Christoph Hellwig --- arch

[PATCH v6 06/14] RISC-V: Provide a cleaner raw_smp_processor_id()

2018-10-02 Thread Atish Patra
From: Palmer Dabbelt I'm not sure how I managed to miss this the first time, but this is much better. Signed-off-by: Palmer Dabbelt [Atish: code comment formatting and other fixes] Signed-off-by: Atish Patra Reviewed-by: Christoph Hellwig --- arch/riscv/include/asm/smp.h | 14

Re: [PATCH v3] RISC-V: Show IPI stats

2018-10-01 Thread Atish Patra
On 9/28/18 11:26 PM, Anup Patel wrote: This patch provides arch_show_interrupts() implementation to show IPI stats via /proc/interrupts. Now the contents of /proc/interrupts" will look like below: CPU0 CPU1 CPU2 CPU3 8: 17 7 6

Re: [PATCH v2] RISC-V: Show CPU ID and Hart ID separately in /proc/cpuinfo

2018-09-27 Thread Atish Patra
On 9/25/18 9:17 PM, Anup Patel wrote: On Tue, Sep 25, 2018 at 11:29 PM Atish Patra wrote: On 9/23/18 6:37 AM, Anup Patel wrote: Currently, /proc/cpuinfo show logical CPU ID as Hart ID which is in-correct. This patch shows CPU ID and Hart ID separately in /proc/cpuinfo using

Re: [PATCH v2] RISC-V: Show CPU ID and Hart ID separately in /proc/cpuinfo

2018-09-25 Thread Atish Patra
On 9/23/18 6:37 AM, Anup Patel wrote: Currently, /proc/cpuinfo show logical CPU ID as Hart ID which is in-correct. This patch shows CPU ID and Hart ID separately in /proc/cpuinfo using cpuid_to_hardid_map(). I noticed it should be cpuid_to_hartid_map instead of cpuid_to_hardid_map. It was a

Re: [PATCH] RISCV: Fix end PFN for low memory

2018-09-24 Thread Atish Patra
On 9/17/18 7:08 AM, Christoph Hellwig wrote: On Tue, Sep 11, 2018 at 11:30:18AM -0700, Atish Patra wrote: Use memblock_end_of_DRAM which provides correct last low memory PFN. Without that, DMA32 region becomes empty resulting in zero pages being allocated for DMA32. This patch is based

Re: [RFC 1/3] dt-bindings: Correct RISC-V's timebase-frequency

2018-09-17 Thread Atish Patra
On 9/17/18 7:20 AM, Christoph Hellwig wrote: On Fri, Sep 14, 2018 at 02:54:54PM -0700, Atish Patra wrote: From: Palmer Dabbelt Someone must have read the device tree specification incorrectly, because we were putting timebase-frequency in the wrong place. This corrects the issue, moving

Re: [RFC 2/3] RISC-V:Support per-hart timebase-frequency

2018-09-17 Thread Atish Patra
On 9/17/18 7:23 AM, Christoph Hellwig wrote: On Fri, Sep 14, 2018 at 02:54:55PM -0700, Atish Patra wrote: Follow the updated DT specs and read the timebase-frequency from the boot cpu. Keep the old DT reading as well for backward compatibility. This patch is rework of old patch from Palmer

Re: [RFC 3/3] RISC-V: Remove per cpu clocksource

2018-09-17 Thread Atish Patra
On 9/17/18 8:01 AM, Christoph Hellwig wrote: On Mon, Sep 17, 2018 at 04:52:44PM +0200, Thomas Gleixner wrote: If this really does not need configuration and all actual implementations are not "allowed" to screw the timer up, then this surely can do without DT. That would be the plan. Just

[RFC 0/3] Timer code cleanup

2018-09-14 Thread Atish Patra
This patch series address some required timer cleanups in RISC-V. Atish Patra (2): RISC-V:Support per-hart timebase-frequency RISC-V: Remove per cpu clocksource Palmer Dabbelt (1): dt-bindings: Correct RISC-V's timebase-frequency Documentation/devicetree/bindings/riscv/cpus.txt | 4

[RFC 1/3] dt-bindings: Correct RISC-V's timebase-frequency

2018-09-14 Thread Atish Patra
From: Palmer Dabbelt Someone must have read the device tree specification incorrectly, because we were putting timebase-frequency in the wrong place. This corrects the issue, moving it from / { cpus { timebase-frequency = X; } } to / { cpus {

[RFC 3/3] RISC-V: Remove per cpu clocksource

2018-09-14 Thread Atish Patra
There is only one clocksource in RISC-V. The boot cpu initializes that clocksource. No need to keep a percpu data structure. Signed-off-by: Atish Patra --- drivers/clocksource/riscv_timer.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/clocksource

[RFC 2/3] RISC-V:Support per-hart timebase-frequency

2018-09-14 Thread Atish Patra
Follow the updated DT specs and read the timebase-frequency from the boot cpu. Keep the old DT reading as well for backward compatibility. This patch is rework of old patch from Palmer. Signed-off-by: Atish Patra --- arch/riscv/kernel/time.c | 9 + drivers/clocksource

[PATCH v5 00/12] SMP cleanup and new features

2018-09-13 Thread Atish Patra
>v5: 1. Minor typo fixes in commit text. Anup Patel (1): RISC-V: No need to pass scause as arg to do_IRQ() Atish Patra (4): RISC-V: Disable preemption before enabling interrupts RISC-V: Use WRITE_ONCE instead of direct access RISC-V: Add logical CPU indexing for RISC-V RISC-V: Use Lin

[PATCH v5 01/12] RISC-V: No need to pass scause as arg to do_IRQ()

2018-09-13 Thread Atish Patra
From: Anup Patel The scause is already part of pt_regs so no need to pass scause as separate arg to do_IRQ(). Reviewed-by: Christoph Hellwig Signed-off-by: Anup Patel --- arch/riscv/kernel/entry.S | 1 - arch/riscv/kernel/irq.c | 4 ++-- 2 files changed, 2 insertions(+), 3 deletions(-)

[PATCH v5 03/12] RISC-V: Filter ISA and MMU values in cpuinfo

2018-09-13 Thread Atish Patra
-by: Atish Patra Reviewed-by: Christoph Hellwig --- arch/riscv/kernel/cpu.c | 68 - 1 file changed, 61 insertions(+), 7 deletions(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index ca6c81e5..1c0bf662 100644 --- a/arch/riscv

[PATCH v5 06/12] RISC-V: Provide a cleaner raw_smp_processor_id()

2018-09-13 Thread Atish Patra
From: Palmer Dabbelt I'm not sure how I managed to miss this the first time, but this is much better. Signed-off-by: Palmer Dabbelt [Atish: code comment formatting and other fixes] Signed-off-by: Atish Patra Reviewed-by: Christoph Hellwig --- arch/riscv/include/asm/smp.h | 14

[PATCH v5 02/12] RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}

2018-09-13 Thread Atish Patra
From: Palmer Dabbelt These are just hard coded in the RISC-V port, which doesn't make any sense. We should probably be setting these from device tree entries when they exist, but for now I think it's saner to just leave them all as their default values. Signed-off-by: Palmer Dabbelt

[PATCH v5 04/12] RISC-V: Comment on the TLB flush in smp_callin()

2018-09-13 Thread Atish Patra
From: Palmer Dabbelt This isn't readily apparent from reading the code. Signed-off-by: Palmer Dabbelt [Atish: code comment formatting update] Signed-off-by: Atish Patra Reviewed-by: Christoph Hellwig --- arch/riscv/kernel/smpboot.c | 4 1 file changed, 4 insertions(+) diff --git

[PATCH v5 07/12] RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid

2018-09-13 Thread Atish Patra
Dabbelt [Atish: code comment formatting update] Signed-off-by: Atish Patra Reviewed-by: Christoph Hellwig --- arch/riscv/include/asm/processor.h | 2 +- arch/riscv/kernel/cpu.c| 7 +-- arch/riscv/kernel/smpboot.c| 2 +- drivers/clocksource/riscv_timer.c | 2 +- drivers

[PATCH v5 05/12] RISC-V: Disable preemption before enabling interrupts

2018-09-13 Thread Atish Patra
Currently, irq is enabled before preemption disabling happens. If the scheduler fired right here and cpu is scheduled then it may blow up. Signed-off-by: Palmer Dabbelt [Atish: Commit text and code comment formatting update] Signed-off-by: Atish Patra Reviewed-by: Christoph Hellwig --- arch

[PATCH v5 09/12] RISC-V: Use mmgrab()

2018-09-13 Thread Atish Patra
From: Palmer Dabbelt commit f1f1007644ff ("mm: add new mmgrab() helper") added a helper that we missed out on. Signed-off-by: Palmer Dabbelt Reviewed-by: Christoph Hellwig Signed-off-by: Atish Patra --- arch/riscv/kernel/smpboot.c | 3 ++- 1 file changed, 2 insertions(+),

[PATCH v5 11/12] RISC-V: Add logical CPU indexing for RISC-V

2018-09-13 Thread Atish Patra
these two. Always mark the boot processor as CPU0 and all other CPUs get the logical CPU id based on their booting order. Signed-off-by: Atish Patra Reviewed-by: Anup Patel Reviewed-by: Christoph Hellwig --- arch/riscv/include/asm/smp.h | 24 +++- arch/riscv/kernel/setup.c

[PATCH v5 10/12] RISC-V: Use WRITE_ONCE instead of direct access

2018-09-13 Thread Atish Patra
The secondary harts spin on couple of per cpu variables until both of these are non-zero so it's not necessary to have any ordering here. However, WRITE_ONCE should be used to avoid tearing. Signed-off-by: Atish Patra Reviewed-by: Christoph Hellwig --- arch/riscv/kernel/smpboot.c | 5 +++-- 1

[PATCH v5 08/12] RISC-V: Rename im_okay_therefore_i_am to found_boot_cpu

2018-09-13 Thread Atish Patra
From: Palmer Dabbelt The old name was a bit odd. Signed-off-by: Palmer Dabbelt Signed-off-by: Atish Patra Reviewed-by: Christoph Hellwig --- arch/riscv/kernel/smpboot.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv

[PATCH v5 12/12] RISC-V: Use Linux logical CPU number instead of hartid

2018-09-13 Thread Atish Patra
Setup the cpu_logical_map during boot. Moreover, every SBI call and PLIC context are based on the physical hartid. Use the logical CPU to hartid mapping to pass correct hartid to respective functions. Signed-off-by: Atish Patra Reviewed-by: Anup Patel Reviewed-by: Christoph Hellwig --- arch

Re: [PATCH v4 10/12] RISC-V: User WRITE_ONCE instead of direct access

2018-09-13 Thread Atish Patra
On 9/11/18 1:33 PM, Andreas Schwab wrote: s/User/Use/ Andreas. Fixed. Thanks. Regards, Atish

Re: [PATCH v2] RISC-V: Show IPI stats

2018-09-13 Thread Atish Patra
On 9/12/18 7:37 AM, Anup Patel wrote: This patch provides arch_show_interrupts() implementation to show IPI stats via /proc/interrupts. Now the contents of /proc/interrupts" will look like below: CPU0 CPU1 CPU2 CPU3 8: 17 7 6 14

Re: [PATCH] RISC-V: Show CPU ID and Hart ID separately in /proc/cpuinfo

2018-09-12 Thread Atish Patra
On 9/12/18 7:38 AM, Anup Patel wrote: Currently, /proc/cpuinfo show logical CPU ID as Hart ID which is in-correct. This patch shows CPU ID and Hart ID separately in /proc/cpuinfo using cpuid_to_hardid_map(). With this patch, contents of /proc/cpuinfo looks as follows: cpu : 0 hart: 1

[PATCH v4 00/12] SMP cleanup and new features

2018-09-11 Thread Atish Patra
. Anup Patel (1): RISC-V: No need to pass scause as arg to do_IRQ() Atish Patra (4): RISC-V: Disable preemption before enabling interrupts RISC-V: User WRITE_ONCE instead of direct access RISC-V: Add logical CPU indexing for RISC-V RISC-V: Use Linux logical cpu number instead of hartid

[PATCH v4 06/12] RISC-V: Provide a cleaner raw_smp_processor_id()

2018-09-11 Thread Atish Patra
From: Palmer Dabbelt I'm not sure how I managed to miss this the first time, but this is much better. Signed-off-by: Palmer Dabbelt [Atish: code comment formatting and other fixes] Signed-off-by: Atish Patra Reviewed-by: Christoph Hellwig --- arch/riscv/include/asm/smp.h | 14

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