Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access

RAM directly on that hardware. > > As far as I know ASICs with support for this are Tonga, Fiji and all Polaris > variants. > > Christian. > > > Am 15.03.2017 um 08:23 schrieb Ayyappa Ch: >> >> Is it possible on Carrizo asics? Or only supports on newer asics?

Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access

rdware. > > As far as I know ASICs with support for this are Tonga, Fiji and all Polaris > variants. > > Christian. > > > Am 15.03.2017 um 08:23 schrieb Ayyappa Ch: >> >> Is it possible on Carrizo asics? Or only supports on newer asics? >> >> On M

Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access

Is it possible on Carrizo asics? Or only supports on newer asics? On Mon, Mar 13, 2017 at 6:11 PM, Christian König wrote: > From: Christian König > > Try to resize BAR0 to let CPU access all of VRAM. > > Signed-off-by: Christian König

Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access

Is it possible on Carrizo asics? Or only supports on newer asics? On Mon, Mar 13, 2017 at 6:11 PM, Christian König wrote: > From: Christian König > > Try to resize BAR0 to let CPU access all of VRAM. > > Signed-off-by: Christian König > --- > drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +

Porting dma-fence and dma-buf from 4.1 to 3.10 kernel

Hello All, We need to port dma fence and dma buf frame work to 3.10 kernel from 4.1 kernel. It seems a huge changes happened to 4.1 to 3.10. I am trying to figure out difficulties before porting the same. Can you please point out difficulties to port dma-fence and dma-buf to 3.10 kernel?

Porting dma-fence and dma-buf from 4.1 to 3.10 kernel

Hello All, We need to port dma fence and dma buf frame work to 3.10 kernel from 4.1 kernel. It seems a huge changes happened to 4.1 to 3.10. I am trying to figure out difficulties before porting the same. Can you please point out difficulties to port dma-fence and dma-buf to 3.10 kernel?

Clarification needed regarding memory barrier

Hello All, I am reading memory-barrier.txt file as mentioned below. Please clarify my doubt . 1) For example if CPU1 got the lock , How PCI bridge can see STORE *ADDR = 4 before STORE *DATA = 1? ACQUIRES VS I/O ACCESSES Under certain circumstances (especially

Clarification needed regarding memory barrier

Hello All, I am reading memory-barrier.txt file as mentioned below. Please clarify my doubt . 1) For example if CPU1 got the lock , How PCI bridge can see STORE *ADDR = 4 before STORE *DATA = 1? ACQUIRES VS I/O ACCESSES Under certain circumstances (especially